AM243x Motor Control SDK  09.00.00
hdsl_drv.h
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1 /*
2  * Copyright (C) 2021-2023 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
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14  * distribution.
15  *
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18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef HDSL_DRV_H_
34 #define HDSL_DRV_H_
35 
45 /* ========================================================================== */
46 /* Include Files */
47 /* ========================================================================== */
48 
49 #include <stdio.h>
50 #include <stdlib.h>
51 
52 #include <kernel/dpl/DebugP.h>
53 
54 #include <drivers/pruicss.h>
55 #include <drivers/hw_include/cslr_soc.h>
56 #include <drivers/hw_include/hw_types.h>
57 
58 #ifdef __cplusplus
59 extern "C" {
60 #endif
61 
62 /* ========================================================================== */
63 /* Macros & Typedefs */
64 /* ========================================================================== */
65 
66 #define MAX_WAIT 20000
67 
68 #define HDSL_ICSSG0_INST 0U
69 #define HDSL_ICSSG1_INST 1U
70 
71 #define HWREG(x) \
72  (*((volatile uint32_t *)(x)))
73 #define HWREGB(x) \
74  (*((volatile uint8_t *)(x)))
75 #define HWREGH(x) \
76  (*((volatile uint16_t *)(x)))
77 /*TSR configuration:*/
78 
79 /*inEvent value:*/
80 /* ICSSG_0_EDC1_SYNC0 ICSSG0 IEP1 sync event 0 Pulse */
81 #define SYNCEVENT_INTRTR_IN_27 27
82 
83 /*outEvent values:*/
84 /*SYNC0_OUT Pin Selectable timesync event 24 Edge (4+(24*4)) */
85 #define SYNCEVT_RTR_SYNC28_EVT 0x64
86 /* SYNC1_OUT Pin Selectable timesync event 25 Edge (4+(25*4)) */
87 #define SYNCEVT_RTR_SYNC29_EVT 0x68
88 /* SYNC2_OUT Pin Selectable timesync event 26 Edge (4+(26*4)) */
89 #define SYNCEVT_RTR_SYNC30_EVT 0x6C
90 /* SYNC3_OUT Pin Selectable timesync event 27 Edge (4+(27*4)) */
91 #define SYNCEVT_RTR_SYNC31_EVT 0x70
92 /* ICSSG0_PR1_EDC1_LATCH0_IN PRU_ICSSG0 (4+(10*4)) */
93 #define SYNCEVT_RTR_SYNC10_EVT 0x2C
94 
95 #define ONLINE_STATUS_1_L_FRES (1<<0)
96 
97 enum {
114 };
115 
116 typedef struct HDSL_Config_s *HDSL_Handle;
117 
118 /* ========================================================================== */
119 /* Structure Declarations & Definitions */
120 /* ========================================================================== */
121 
127 typedef struct {
128  volatile uint8_t SYS_CTRL;
129  volatile uint8_t SYNC_CTRL;
130  volatile uint8_t resvd0;
131  volatile uint8_t MASTER_QM;
132  volatile uint8_t EVENT_H;
133  volatile uint8_t EVENT_L;
134  volatile uint8_t MASK_H;
135  volatile uint8_t MASK_L;
136  volatile uint8_t MASK_SUM;
137  volatile uint8_t EDGES;
138  volatile uint8_t DELAY;
139  volatile uint8_t VERSION;
140  volatile uint8_t resvd1;
141  volatile uint8_t ENC_ID2;
142  volatile uint8_t ENC_ID1;
143  volatile uint8_t ENC_ID0;
144  volatile uint8_t POS4;
145  volatile uint8_t POS3;
146  volatile uint8_t POS2;
147  volatile uint8_t POS1;
148  volatile uint8_t POS0;
149  volatile uint8_t VEL2;
150  volatile uint8_t VEL1;
151  volatile uint8_t VEL0;
152  volatile uint8_t resvd2;
153  volatile uint8_t VPOS4;
154  volatile uint8_t VPOS3;
155  volatile uint8_t VPOS2;
156  volatile uint8_t VPOS1;
157  volatile uint8_t VPOS0;
158  volatile uint8_t VPOSCRC_H;
159  volatile uint8_t VPOSCRC_L;
160  volatile uint8_t PC_BUFFER0;
161  volatile uint8_t PC_BUFFER1;
162  volatile uint8_t PC_BUFFER2;
163  volatile uint8_t PC_BUFFER3;
164  volatile uint8_t PC_BUFFER4;
165  volatile uint8_t PC_BUFFER5;
166  volatile uint8_t PC_BUFFER6;
167  volatile uint8_t PC_BUFFER7;
168  volatile uint8_t PC_ADD_H;
169  volatile uint8_t PC_ADD_L;
170  volatile uint8_t PC_OFF_H;
171  volatile uint8_t PC_OFF_L;
172  volatile uint8_t PC_CTRL;
173  volatile uint8_t PIPE_S;
174  volatile uint8_t PIPE_D;
175  volatile uint8_t PC_DATA;
176  volatile uint8_t resvd3;
177  volatile uint8_t resvd4;
178  volatile uint8_t resvd5;
179  volatile uint8_t resvd6;
180  volatile uint8_t resvd7;
181  volatile uint8_t SAFE_CTRL;
182  volatile uint8_t SAFE_SUM;
183  volatile uint8_t S_PC_DATA;
184  volatile uint8_t ACC_ERR_CNT;
185  volatile uint8_t resvd8;
186  volatile uint8_t resvd9;
187  volatile uint8_t resvd10;
188  volatile uint8_t resvd11;
189  volatile uint8_t EVENT_S;
190  volatile uint8_t MASK_S;
191  volatile uint8_t DUMMY;
192  volatile uint8_t SLAVE_REG_CTRL;
193  volatile uint8_t ACC_ERR_CNT_THRESH;
194  volatile uint8_t resvd12;
195  volatile uint8_t resvd13;
196  /*Safe 2 Interface */
197  volatile uint8_t VERSION2;
198  volatile uint8_t ENC2_ID;
199  volatile uint8_t STATUS2;
200  volatile uint8_t VPOS24;
201  volatile uint8_t VPOS23;
202  volatile uint8_t VPOS22;
203  volatile uint8_t VPOS21;
204  volatile uint8_t VPOS20;
205  volatile uint8_t VPOSCRC2_H;
206  volatile uint8_t VPOSCRC2_L;
207  volatile uint8_t POSTX;
208  volatile uint8_t resvd14;
209  /* Online Status*/
210  volatile uint8_t ONLINE_STATUS_D_H;
211  volatile uint8_t ONLINE_STATUS_D_L;
212  volatile uint8_t ONLINE_STATUS_1_H;
213  volatile uint8_t ONLINE_STATUS_1_L;
214  volatile uint8_t ONLINE_STATUS_2_H;
215  volatile uint8_t ONLINE_STATUS_2_L;
224 typedef struct HDSL_Config_s {
225  PRUICSS_Handle icssgHandle;
227  uint32_t icssCore;
231  uint32_t *baseMemAddr; // icssgHandle->hwAttrs->baseAddr + PRUICSS_DATARAM(PRUICSS_PRUx)
235  uint32_t multi_turn;
237  uint32_t res;
239  uint64_t mask;
242  // intc_initdata // ** - needs to be common for all channels and fixed (configure for all 3 channels in starting)
243 
244 } HDSL_Config;
247 /* ========================================================================== */
248 /* Function Declarations */
249 /* ========================================================================== */
257 void hdsl_enable_load_share_mode(void *gPru_cfg ,uint32_t PRU_SLICE);
268 // HDSL_ICSSG0_INST, HDSL_ICSSG1_INST
269 HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore,uint8_t PRU_mode);
270 
277 void HDSL_iep_init(HDSL_Handle hdslHandle);
278 
291 int HDSL_enable_sync_signal(uint8_t ES, uint32_t period);
292 
301 uint64_t HDSL_get_pos(HDSL_Handle hdslHandle, int position_id);
302 
309 uint8_t HDSL_get_qm(HDSL_Handle hdslHandle);
310 
318 uint16_t HDSL_get_events(HDSL_Handle hdslHandle);
319 
328 uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle);
329 
330 
340 
350 
360 
368 uint8_t HDSL_get_sum(HDSL_Handle hdslHandle);
369 
377 uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle);
378 
386 uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle);
387 
399 int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t data, uint64_t timeout);
400 
412 int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle,uint8_t addr, uint8_t *data, uint64_t timeout);
413 
424 void HDSL_set_pc_addr(HDSL_Handle hdslHandle, uint8_t pc_addrh, uint8_t pc_addrl, uint8_t pc_offh, uint8_t pc_offl);
425 
433 void HDSL_set_pc_ctrl(HDSL_Handle hdslHandle, uint8_t value);
434 
449 void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7);
450 
459 uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off);
460 
469 uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle);
470 
478 void HDSL_set_sync_ctrl(HDSL_Handle hdslHandle, uint8_t val);
479 
487 uint8_t HDSL_get_master_qm(HDSL_Handle hdslHandle);
488 
496 uint8_t HDSL_get_edges(HDSL_Handle hdslHandle);
497 
505 uint8_t HDSL_get_delay(HDSL_Handle hdslHandle);
506 
515 uint8_t HDSL_get_enc_id(HDSL_Handle hdslHandle, int byte);
516 
524 
532 void* HDSL_get_src_loc(HDSL_Handle hdslHandle);
533 
541 uint32_t HDSL_get_length(HDSL_Handle hdslHandle);
542 
543 #ifdef __cplusplus
544 }
545 #endif
546 
548 #endif
HDSL_Config
Definition: hdsl_drv.h:224
HDSL_Interface::POSTX
volatile uint8_t POSTX
Definition: hdsl_drv.h:207
HDSL_Interface::resvd3
volatile uint8_t resvd3
Definition: hdsl_drv.h:176
MENU_SAFE_POSITION
@ MENU_SAFE_POSITION
Definition: hdsl_drv.h:98
HDSL_iep_init
void HDSL_iep_init(HDSL_Handle hdslHandle)
Initialize IEP and Use OCP as IEP CLK src.
HDSL_Interface::VPOSCRC2_L
volatile uint8_t VPOSCRC2_L
Definition: hdsl_drv.h:206
HDSL_Interface::PC_OFF_H
volatile uint8_t PC_OFF_H
Definition: hdsl_drv.h:170
HDSL_Interface::VERSION
volatile uint8_t VERSION
Definition: hdsl_drv.h:139
HDSL_Interface::resvd2
volatile uint8_t resvd2
Definition: hdsl_drv.h:152
HDSL_Interface::ONLINE_STATUS_D_H
volatile uint8_t ONLINE_STATUS_D_H
Definition: hdsl_drv.h:210
HDSL_Interface::VPOS20
volatile uint8_t VPOS20
Definition: hdsl_drv.h:204
HDSL_Interface::VPOS23
volatile uint8_t VPOS23
Definition: hdsl_drv.h:201
HDSL_Config::baseMemAddr
uint32_t * baseMemAddr
Definition: hdsl_drv.h:231
MENU_DIRECT_READ_RID81_LENGTH8
@ MENU_DIRECT_READ_RID81_LENGTH8
Definition: hdsl_drv.h:107
hdsl_enable_load_share_mode
void hdsl_enable_load_share_mode(void *gPru_cfg, uint32_t PRU_SLICE)
enable load share mode for multi-channel HDSL
HDSL_Interface::SAFE_CTRL
volatile uint8_t SAFE_CTRL
Definition: hdsl_drv.h:181
HDSL_enable_sync_signal
int HDSL_enable_sync_signal(uint8_t ES, uint32_t period)
Enable IEP *Enable SYNC0 and program pulse width Enable cyclic mod Program CMP1 TSR configura...
HDSL_Interface::EVENT_L
volatile uint8_t EVENT_L
Definition: hdsl_drv.h:133
HDSL_Interface::resvd14
volatile uint8_t resvd14
Definition: hdsl_drv.h:208
HDSL_Interface::resvd11
volatile uint8_t resvd11
Definition: hdsl_drv.h:188
HDSL_Config::icssCore
uint32_t icssCore
Definition: hdsl_drv.h:227
HDSL_Interface::resvd1
volatile uint8_t resvd1
Definition: hdsl_drv.h:140
HDSL_Interface::EDGES
volatile uint8_t EDGES
Definition: hdsl_drv.h:137
HDSL_Interface::PC_BUFFER5
volatile uint8_t PC_BUFFER5
Definition: hdsl_drv.h:165
HDSL_get_sync_ctrl
uint8_t HDSL_get_sync_ctrl(HDSL_Handle hdslHandle)
Returns Synchronization control value.
HDSL_Config::mask
uint64_t mask
Definition: hdsl_drv.h:239
HDSL_Interface::PC_ADD_H
volatile uint8_t PC_ADD_H
Definition: hdsl_drv.h:168
MENU_PC_SHORT_MSG_WRITE
@ MENU_PC_SHORT_MSG_WRITE
Definition: hdsl_drv.h:104
HDSL_Interface::ONLINE_STATUS_1_H
volatile uint8_t ONLINE_STATUS_1_H
Definition: hdsl_drv.h:212
HDSL_Interface::VPOS0
volatile uint8_t VPOS0
Definition: hdsl_drv.h:157
HDSL_Interface::resvd10
volatile uint8_t resvd10
Definition: hdsl_drv.h:187
HDSL_Interface
Definition: hdsl_drv.h:127
HDSL_Interface::VPOSCRC_H
volatile uint8_t VPOSCRC_H
Definition: hdsl_drv.h:158
HDSL_Interface::VPOS3
volatile uint8_t VPOS3
Definition: hdsl_drv.h:154
HDSL_Interface::resvd0
volatile uint8_t resvd0
Definition: hdsl_drv.h:130
HDSL_set_pc_addr
void HDSL_set_pc_addr(HDSL_Handle hdslHandle, uint8_t pc_addrh, uint8_t pc_addrl, uint8_t pc_offh, uint8_t pc_offl)
Write PC_AAD_L ,PC_ADD_H ,PC_OFF_L,PC_OFF_H and PC_CTRL values in hdsl interface.
HDSL_Config::res
uint32_t res
Definition: hdsl_drv.h:237
HDSL_get_acc_err_cnt
uint8_t HDSL_get_acc_err_cnt(HDSL_Handle hdslHandle)
Acceleration error counter.
HDSL_Interface::resvd6
volatile uint8_t resvd6
Definition: hdsl_drv.h:179
HDSL_set_sync_ctrl
void HDSL_set_sync_ctrl(HDSL_Handle hdslHandle, uint8_t val)
Writes Synchronization control value.
HDSL_Interface::ENC_ID2
volatile uint8_t ENC_ID2
Definition: hdsl_drv.h:141
HDSL_get_sum
uint8_t HDSL_get_sum(HDSL_Handle hdslHandle)
Getting Summarized slave status.
HDSL_Interface::ONLINE_STATUS_2_H
volatile uint8_t ONLINE_STATUS_2_H
Definition: hdsl_drv.h:214
HDSL_Interface::POS0
volatile uint8_t POS0
Definition: hdsl_drv.h:148
HDSL_Interface::PC_DATA
volatile uint8_t PC_DATA
Definition: hdsl_drv.h:175
HDSL_Interface::S_PC_DATA
volatile uint8_t S_PC_DATA
Definition: hdsl_drv.h:183
HDSL_Interface::MASTER_QM
volatile uint8_t MASTER_QM
Definition: hdsl_drv.h:131
HDSL_Interface::SAFE_SUM
volatile uint8_t SAFE_SUM
Definition: hdsl_drv.h:182
HDSL_Interface::EVENT_H
volatile uint8_t EVENT_H
Definition: hdsl_drv.h:132
HDSL_get_src_loc
void * HDSL_get_src_loc(HDSL_Handle hdslHandle)
Get memory location for HDSL interface struct.
MENU_DIRECT_READ_RID0_LENGTH8
@ MENU_DIRECT_READ_RID0_LENGTH8
Definition: hdsl_drv.h:106
HDSL_set_pc_ctrl
void HDSL_set_pc_ctrl(HDSL_Handle hdslHandle, uint8_t value)
To set the direction read/write for long message communication.
HDSL_Interface::ONLINE_STATUS_1_L
volatile uint8_t ONLINE_STATUS_1_L
Definition: hdsl_drv.h:213
MENU_HDSL_REG_INTO_MEMORY
@ MENU_HDSL_REG_INTO_MEMORY
Definition: hdsl_drv.h:111
HDSL_Interface::resvd5
volatile uint8_t resvd5
Definition: hdsl_drv.h:178
HDSL_Interface::PIPE_S
volatile uint8_t PIPE_S
Definition: hdsl_drv.h:173
MENU_EVENTS
@ MENU_EVENTS
Definition: hdsl_drv.h:100
HDSL_Interface::resvd4
volatile uint8_t resvd4
Definition: hdsl_drv.h:177
HDSL_Interface::ACC_ERR_CNT
volatile uint8_t ACC_ERR_CNT
Definition: hdsl_drv.h:184
HDSL_get_edges
uint8_t HDSL_get_edges(HDSL_Handle hdslHandle)
Returns Cable bit sampling time control.
HDSL_Interface::PC_OFF_L
volatile uint8_t PC_OFF_L
Definition: hdsl_drv.h:171
HDSL_Config::multi_turn
uint32_t multi_turn
Definition: hdsl_drv.h:235
HDSL_Interface::VPOS1
volatile uint8_t VPOS1
Definition: hdsl_drv.h:156
HDSL_Interface::SLAVE_REG_CTRL
volatile uint8_t SLAVE_REG_CTRL
Definition: hdsl_drv.h:192
MENU_INVALID
@ MENU_INVALID
Definition: hdsl_drv.h:113
HDSL_get_pos
uint64_t HDSL_get_pos(HDSL_Handle hdslHandle, int position_id)
Calculate fast position,safe position1,safe position2.
HDSL_Interface::PC_BUFFER2
volatile uint8_t PC_BUFFER2
Definition: hdsl_drv.h:162
HDSL_Interface::VPOS24
volatile uint8_t VPOS24
Definition: hdsl_drv.h:200
HDSL_Interface::VPOSCRC_L
volatile uint8_t VPOSCRC_L
Definition: hdsl_drv.h:159
HDSL_Interface::MASK_H
volatile uint8_t MASK_H
Definition: hdsl_drv.h:134
HDSL_Interface::MASK_S
volatile uint8_t MASK_S
Definition: hdsl_drv.h:190
HDSL_Interface::resvd7
volatile uint8_t resvd7
Definition: hdsl_drv.h:180
HDSL_get_enc_id
uint8_t HDSL_get_enc_id(HDSL_Handle hdslHandle, int byte)
Read encoder id bytes(byte no. 0-2)
HDSL_Interface::PC_BUFFER1
volatile uint8_t PC_BUFFER1
Definition: hdsl_drv.h:161
MENU_INDIRECT_WRITE_RID0_LENGTH8
@ MENU_INDIRECT_WRITE_RID0_LENGTH8
Definition: hdsl_drv.h:110
HDSL_Interface::PC_BUFFER6
volatile uint8_t PC_BUFFER6
Definition: hdsl_drv.h:166
HDSL_Interface::PC_BUFFER0
volatile uint8_t PC_BUFFER0
Definition: hdsl_drv.h:160
HDSL_get_rssi
uint8_t HDSL_get_rssi(HDSL_Handle hdslHandle)
Read RSSI value.
HDSL_Interface::resvd13
volatile uint8_t resvd13
Definition: hdsl_drv.h:195
HDSL_Interface::ENC_ID0
volatile uint8_t ENC_ID0
Definition: hdsl_drv.h:143
HDSL_Interface::PIPE_D
volatile uint8_t PIPE_D
Definition: hdsl_drv.h:174
HDSL_Interface::ONLINE_STATUS_D_L
volatile uint8_t ONLINE_STATUS_D_L
Definition: hdsl_drv.h:211
HDSL_Handle
struct HDSL_Config_s * HDSL_Handle
Definition: hdsl_drv.h:116
MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
@ MENU_INDIRECT_WRITE_RID0_LENGTH8_OFFSET0
Definition: hdsl_drv.h:109
HDSL_Interface::resvd9
volatile uint8_t resvd9
Definition: hdsl_drv.h:186
HDSL_get_qm
uint8_t HDSL_get_qm(HDSL_Handle hdslHandle)
Getting quality monitoring value.
HDSL_Interface::VERSION2
volatile uint8_t VERSION2
Definition: hdsl_drv.h:197
HDSL_get_length
uint32_t HDSL_get_length(HDSL_Handle hdslHandle)
Get size of memory used by HDSL interface struct.
HDSL_Interface::MASK_SUM
volatile uint8_t MASK_SUM
Definition: hdsl_drv.h:136
HDSL_Config::icssgHandle
PRUICSS_Handle icssgHandle
Definition: hdsl_drv.h:225
HDSL_get_online_status_d
uint16_t HDSL_get_online_status_d(HDSL_Handle hdslHandle)
Taking values of Online Status D (ONLINE_STATUS_D) register.
HDSL_Interface::EVENT_S
volatile uint8_t EVENT_S
Definition: hdsl_drv.h:189
HDSL_Interface::DELAY
volatile uint8_t DELAY
Definition: hdsl_drv.h:138
HDSL_Interface::ENC_ID1
volatile uint8_t ENC_ID1
Definition: hdsl_drv.h:142
HDSL_Interface::VPOS2
volatile uint8_t VPOS2
Definition: hdsl_drv.h:155
HDSL_Interface::PC_ADD_L
volatile uint8_t PC_ADD_L
Definition: hdsl_drv.h:169
HDSL_Interface::ACC_ERR_CNT_THRESH
volatile uint8_t ACC_ERR_CNT_THRESH
Definition: hdsl_drv.h:193
HDSL_get_online_status_1
uint16_t HDSL_get_online_status_1(HDSL_Handle hdslHandle)
Taking values of Online Status D (ONLINE_STATUS_D) register.
HDSL_Interface::POS3
volatile uint8_t POS3
Definition: hdsl_drv.h:145
HDSL_Interface::PC_BUFFER4
volatile uint8_t PC_BUFFER4
Definition: hdsl_drv.h:164
HDSL_Interface::resvd8
volatile uint8_t resvd8
Definition: hdsl_drv.h:185
HDSL_read_pc_buffer
uint8_t HDSL_read_pc_buffer(HDSL_Handle hdslHandle, uint8_t buff_off)
Returns Parameters channel buffer for different bytes(bytes 0-7)
HDSL_get_safe_events
uint8_t HDSL_get_safe_events(HDSL_Handle hdslHandle)
Taking values of Safe Event (EVENT_S) register.
HDSL_get_online_status_2
uint16_t HDSL_get_online_status_2(HDSL_Handle hdslHandle)
Taking values of Online Status D (ONLINE_STATUS_D) register.
HDSL_Interface::VPOS4
volatile uint8_t VPOS4
Definition: hdsl_drv.h:153
HDSL_Interface::VEL1
volatile uint8_t VEL1
Definition: hdsl_drv.h:150
HDSL_Interface::resvd12
volatile uint8_t resvd12
Definition: hdsl_drv.h:194
HDSL_Interface::ONLINE_STATUS_2_L
volatile uint8_t ONLINE_STATUS_2_L
Definition: hdsl_drv.h:215
HDSL_read_pc_short_msg
int32_t HDSL_read_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t *data, uint64_t timeout)
Read Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) and write Short m...
MENU_SUMMARY
@ MENU_SUMMARY
Definition: hdsl_drv.h:101
HDSL_get_delay
uint8_t HDSL_get_delay(HDSL_Handle hdslHandle)
Returns Run time delay of system cable and signal strength.
HDSL_Config::hdslInterface
HDSL_Interface * hdslInterface
Definition: hdsl_drv.h:233
MENU_LIMIT
@ MENU_LIMIT
Definition: hdsl_drv.h:112
MENU_DIRECT_READ_RID81_LENGTH2
@ MENU_DIRECT_READ_RID81_LENGTH2
Definition: hdsl_drv.h:108
HDSL_Interface::SYS_CTRL
volatile uint8_t SYS_CTRL
Definition: hdsl_drv.h:128
HDSL_Interface::POS2
volatile uint8_t POS2
Definition: hdsl_drv.h:146
MENU_RSSI
@ MENU_RSSI
Definition: hdsl_drv.h:103
HDSL_open
HDSL_Handle HDSL_open(PRUICSS_Handle icssgHandle, uint32_t icssCore, uint8_t PRU_mode)
Open HDSL handle for the specified core (interrupt mapping should already be completed)
HDSL_Interface::PC_CTRL
volatile uint8_t PC_CTRL
Definition: hdsl_drv.h:172
HDSL_Interface::POS4
volatile uint8_t POS4
Definition: hdsl_drv.h:144
HDSL_Interface::PC_BUFFER7
volatile uint8_t PC_BUFFER7
Definition: hdsl_drv.h:167
HDSL_Interface::POS1
volatile uint8_t POS1
Definition: hdsl_drv.h:147
HDSL_write_pc_buffer
void HDSL_write_pc_buffer(HDSL_Handle hdslHandle, uint8_t pc_buf0, uint8_t pc_buf1, uint8_t pc_buf2, uint8_t pc_buf3, uint8_t pc_buf4, uint8_t pc_buf5, uint8_t pc_buf6, uint8_t pc_buf7)
Write Parameters channel buffer for different bytes(bytes 0-7)
HDSL_Interface::VPOS21
volatile uint8_t VPOS21
Definition: hdsl_drv.h:203
HDSL_generate_memory_image
void HDSL_generate_memory_image(HDSL_Handle hdslHandle)
Generates memory image.
HDSL_Interface::SYNC_CTRL
volatile uint8_t SYNC_CTRL
Definition: hdsl_drv.h:129
HDSL_Interface::ENC2_ID
volatile uint8_t ENC2_ID
Definition: hdsl_drv.h:198
HDSL_get_events
uint16_t HDSL_get_events(HDSL_Handle hdslHandle)
Taking values of High bytes event (EVENT_H) and Low bytes event(EVENT_L)
MENU_QUALITY_MONITORING
@ MENU_QUALITY_MONITORING
Definition: hdsl_drv.h:99
HDSL_Interface::PC_BUFFER3
volatile uint8_t PC_BUFFER3
Definition: hdsl_drv.h:163
MENU_ACC_ERR_CNT
@ MENU_ACC_ERR_CNT
Definition: hdsl_drv.h:102
HDSL_Interface::VEL0
volatile uint8_t VEL0
Definition: hdsl_drv.h:151
HDSL_Interface::MASK_L
volatile uint8_t MASK_L
Definition: hdsl_drv.h:135
MENU_PC_SHORT_MSG_READ
@ MENU_PC_SHORT_MSG_READ
Definition: hdsl_drv.h:105
HDSL_Interface::DUMMY
volatile uint8_t DUMMY
Definition: hdsl_drv.h:191
HDSL_Interface::VPOSCRC2_H
volatile uint8_t VPOSCRC2_H
Definition: hdsl_drv.h:205
HDSL_write_pc_short_msg
int32_t HDSL_write_pc_short_msg(HDSL_Handle hdslHandle, uint8_t addr, uint8_t data, uint64_t timeout)
Write Response of Short message parameters channel Read for safe1 channel(S_PC_DATA) with gPc_data an...
HDSL_Interface::STATUS2
volatile uint8_t STATUS2
Definition: hdsl_drv.h:199
HDSL_Interface::VPOS22
volatile uint8_t VPOS22
Definition: hdsl_drv.h:202
HDSL_get_master_qm
uint8_t HDSL_get_master_qm(HDSL_Handle hdslHandle)
Returns Quality monitoring value.
HDSL_Interface::VEL2
volatile uint8_t VEL2
Definition: hdsl_drv.h:149