HDSL

Table of Contents

• Introduction
• Features Supported
• Features Not Supported
• SysConfig Features
• HDSL Design
• Register List
• Exceptions
• Example
• API

Introduction

The HDSL firmware running on ICSS-PRU provides a defined well interface to execute the HDSL protocol.

Features Supported

• Safe position
• Fast position, speed
• Communication status
• External pulse synchronization
• Register interface to be compatible with SICK HDSL FPGA IP Core (apart from the differences listed in TI HDSL Exceptions List)
• Parameter channel communication
  • Short message
  • Long message
• Safety
• Two channels support on am243x-evm
• Single channel support on am243x-lp
• Tested with three different encoder makes (EDM35, EKS36, EKM36)

Features Not Supported

In general, peripherals or features not mentioned as part of "Features Supported" section are not supported, including the below

• 100m cable
• Three channel support using single PRU-ICSSG slice
• Pipeline Channel

SysConfig Features

Note

It is strongly recommend to use SysConfig where it is available instead of using direct SW API calls. This will help simplify the SW application and also catch common mistakes early in the development cycle.

SysConfig can be used to configure things mentioned below:

• Selecting the ICSSG0PRUx instance.(Tested on ICSSG0-PRU1)
• Configuring PINMUX
• Channel selection
• Mode Selection (Free run/Sync mode)
• Hardware selection (Booster Pack for am243x-lp)

HDSL Design

HDSL Protocol Design explains the design in detail.

Register List

TI HDSL Register List contains the description of registers in TI's HDSL implementation. Please note that all the corresponding register fields are not implemented.

Exceptions

TI HDSL Exceptions List lists the exceptions TI's HDSL implementation when compared with SICK HDSL FPGA IP Core. Please note that all the corresponding register fields are not implemented.

Example

HDSL Diagnostic

API

APIs for HDSL Encoder