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AM263x MCU+ SDK
09.00.00
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63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
66 #include <drivers/hw_include/cslr_epwm.h>
79 #define EPWM_SYNC_OUT_SOURCE_M ((uint16_t)CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK |\
80 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK |\
81 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK |\
82 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK |\
83 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK |\
84 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK |\
85 (uint16_t)CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK)
94 #define EPWM_SYNC_OUT_PULSE_ON_SOFTWARE CSL_EPWM_EPWMSYNCOUTEN_SWEN_MASK
95 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO CSL_EPWM_EPWMSYNCOUTEN_ZEROEN_MASK
97 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_B CSL_EPWM_EPWMSYNCOUTEN_CMPBEN_MASK
99 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_C CSL_EPWM_EPWMSYNCOUTEN_CMPCEN_MASK
101 #define EPWM_SYNC_OUT_PULSE_ON_CNTR_COMPARE_D CSL_EPWM_EPWMSYNCOUTEN_CMPDEN_MASK
103 #define EPWM_SYNC_OUT_PULSE_ON_DCA_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCAEVT1EN_MASK
105 #define EPWM_SYNC_OUT_PULSE_ON_DCB_EVT1_SYNC CSL_EPWM_EPWMSYNCOUTEN_DCBEVT1EN_MASK
107 #define EPWM_SYNC_OUT_PULSE_ON_ALL EPWM_SYNC_OUT_SOURCE_M
376 #define EPWM_TIME_BASE_STATUS_COUNT_DOWN (0U)
377 #define EPWM_TIME_BASE_STATUS_COUNT_UP (1U)
780 #define EPWM_DB_INPUT_EPWMA (0U)
781 #define EPWM_DB_INPUT_EPWMB (1U)
783 #define EPWM_DB_INPUT_DB_RED (2U)
864 #define EPWM_TZ_SIGNAL_CBC1 (0x1U)
865 #define EPWM_TZ_SIGNAL_CBC2 (0x2U)
867 #define EPWM_TZ_SIGNAL_CBC3 (0x4U)
869 #define EPWM_TZ_SIGNAL_CBC4 (0x8U)
871 #define EPWM_TZ_SIGNAL_CBC5 (0x10U)
873 #define EPWM_TZ_SIGNAL_CBC6 (0x20U)
875 #define EPWM_TZ_SIGNAL_DCAEVT2 (0x40U)
877 #define EPWM_TZ_SIGNAL_DCBEVT2 (0x80U)
879 #define EPWM_TZ_SIGNAL_OSHT1 (0x100U)
881 #define EPWM_TZ_SIGNAL_OSHT2 (0x200U)
883 #define EPWM_TZ_SIGNAL_OSHT3 (0x400U)
885 #define EPWM_TZ_SIGNAL_OSHT4 (0x800U)
887 #define EPWM_TZ_SIGNAL_OSHT5 (0x1000U)
889 #define EPWM_TZ_SIGNAL_OSHT6 (0x2000U)
891 #define EPWM_TZ_SIGNAL_DCAEVT1 (0x4000U)
893 #define EPWM_TZ_SIGNAL_DCBEVT1 (0x8000U)
895 #define EPWM_TZ_SIGNAL_CAPEVT_OST (0x10000U)
897 #define EPWM_TZ_SIGNAL_CAPEVT_CBC (0x1000000U)
1020 #define EPWM_TZ_INTERRUPT_CBC (0x2U)
1021 #define EPWM_TZ_INTERRUPT_OST (0x4U)
1023 #define EPWM_TZ_INTERRUPT_DCAEVT1 (0x8U)
1025 #define EPWM_TZ_INTERRUPT_DCAEVT2 (0x10U)
1027 #define EPWM_TZ_INTERRUPT_DCBEVT1 (0x20U)
1029 #define EPWM_TZ_INTERRUPT_DCBEVT2 (0x40U)
1031 #define EPWM_TZ_INTERRUPT_CAPEVT (0x80U)
1040 #define EPWM_TZ_FLAG_CBC (0x2U)
1041 #define EPWM_TZ_FLAG_OST (0x4U)
1043 #define EPWM_TZ_FLAG_DCAEVT1 (0x8U)
1045 #define EPWM_TZ_FLAG_DCAEVT2 (0x10U)
1047 #define EPWM_TZ_FLAG_DCBEVT1 (0x20U)
1049 #define EPWM_TZ_FLAG_DCBEVT2 (0x40U)
1051 #define EPWM_TZ_FLAG_CAPEVT (0x80U)
1061 #define EPWM_TZ_INTERRUPT (0x1U)
1071 #define EPWM_TZ_CBC_FLAG_1 (0x1U)
1072 #define EPWM_TZ_CBC_FLAG_2 (0x2U)
1074 #define EPWM_TZ_CBC_FLAG_3 (0x4U)
1076 #define EPWM_TZ_CBC_FLAG_4 (0x8U)
1078 #define EPWM_TZ_CBC_FLAG_5 (0x10U)
1080 #define EPWM_TZ_CBC_FLAG_6 (0x20U)
1082 #define EPWM_TZ_CBC_FLAG_DCAEVT2 (0x40U)
1084 #define EPWM_TZ_CBC_FLAG_DCBEVT2 (0x80U)
1086 #define EPWM_TZ_CBC_FLAG_CAPEVT (0x100U)
1097 #define EPWM_TZ_OST_FLAG_OST1 (0x1U)
1098 #define EPWM_TZ_OST_FLAG_OST2 (0x2U)
1100 #define EPWM_TZ_OST_FLAG_OST3 (0x4U)
1102 #define EPWM_TZ_OST_FLAG_OST4 (0x8U)
1104 #define EPWM_TZ_OST_FLAG_OST5 (0x10U)
1106 #define EPWM_TZ_OST_FLAG_OST6 (0x20U)
1108 #define EPWM_TZ_OST_FLAG_DCAEVT1 (0x40U)
1110 #define EPWM_TZ_OST_FLAG_DCBEVT1 (0x80U)
1112 #define EPWM_TZ_OST_FLAG_CAPEVT (0x100U)
1138 #define EPWM_TZ_FORCE_EVENT_CBC (0x2U)
1139 #define EPWM_TZ_FORCE_EVENT_OST (0x4U)
1141 #define EPWM_TZ_FORCE_EVENT_DCAEVT1 (0x8U)
1143 #define EPWM_TZ_FORCE_EVENT_DCAEVT2 (0x10U)
1145 #define EPWM_TZ_FORCE_EVENT_DCBEVT1 (0x20U)
1147 #define EPWM_TZ_FORCE_EVENT_DCBEVT2 (0x40U)
1149 #define EPWM_TZ_FORCE_EVENT_CAPEVT (0x80U)
1159 #define EPWM_TZ_SELECT_TRIPOUT_OST (0x1)
1160 #define EPWM_TZ_SELECT_TRIPOUT_CBC (0x2)
1162 #define EPWM_TZ_SELECT_TRIPOUT_TZ1 (0x4)
1164 #define EPWM_TZ_SELECT_TRIPOUT_TZ2 (0x8)
1166 #define EPWM_TZ_SELECT_TRIPOUT_TZ3 (0x10)
1168 #define EPWM_TZ_SELECT_TRIPOUT_TZ4 (0x20)
1170 #define EPWM_TZ_SELECT_TRIPOUT_TZ5 (0x40)
1172 #define EPWM_TZ_SELECT_TRIPOUT_TZ6 (0x80)
1174 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT1 (0x100)
1176 #define EPWM_TZ_SELECT_TRIPOUT_DCAEVT2 (0x200)
1178 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT1 (0x400)
1180 #define EPWM_TZ_SELECT_TRIPOUT_DCBEVT2 (0x800)
1182 #define EPWM_TZ_SELECT_TRIPOUT_CAPEVT (0x1000)
1192 #define EPWM_INT_TBCTR_ZERO (1U)
1193 #define EPWM_INT_TBCTR_PERIOD (2U)
1195 #define EPWM_INT_TBCTR_ETINTMIX (3U)
1197 #define EPWM_INT_TBCTR_U_CMPA (4U)
1199 #define EPWM_INT_TBCTR_U_CMPC (8U)
1201 #define EPWM_INT_TBCTR_D_CMPA (5U)
1203 #define EPWM_INT_TBCTR_D_CMPC (10U)
1205 #define EPWM_INT_TBCTR_U_CMPB (6U)
1207 #define EPWM_INT_TBCTR_U_CMPD (12U)
1209 #define EPWM_INT_TBCTR_D_CMPB (7U)
1211 #define EPWM_INT_TBCTR_D_CMPD (14U)
1221 #define EPWM_INT_MIX_TBCTR_ZERO (0x1)
1222 #define EPWM_INT_MIX_TBCTR_PERIOD (0x2)
1224 #define EPWM_INT_MIX_TBCTR_U_CMPA (0x4)
1226 #define EPWM_INT_MIX_TBCTR_D_CMPA (0x8)
1228 #define EPWM_INT_MIX_TBCTR_U_CMPB (0x10)
1230 #define EPWM_INT_MIX_TBCTR_D_CMPB (0x20)
1232 #define EPWM_INT_MIX_TBCTR_U_CMPC (0x40)
1234 #define EPWM_INT_MIX_TBCTR_D_CMPC (0x80)
1236 #define EPWM_INT_MIX_TBCTR_U_CMPD (0x100)
1238 #define EPWM_INT_MIX_TBCTR_D_CMPD (0x200)
1240 #define EPWM_INT_MIX_DCAEVT1 (0x400)
1351 #define EPWM_DC_COMBINATIONAL_TRIPIN1 (0x1U)
1352 #define EPWM_DC_COMBINATIONAL_TRIPIN2 (0x2U)
1354 #define EPWM_DC_COMBINATIONAL_TRIPIN3 (0x4U)
1356 #define EPWM_DC_COMBINATIONAL_TRIPIN4 (0x8U)
1358 #define EPWM_DC_COMBINATIONAL_TRIPIN5 (0x10U)
1360 #define EPWM_DC_COMBINATIONAL_TRIPIN6 (0x20U)
1362 #define EPWM_DC_COMBINATIONAL_TRIPIN7 (0x40U)
1364 #define EPWM_DC_COMBINATIONAL_TRIPIN8 (0x80U)
1366 #define EPWM_DC_COMBINATIONAL_TRIPIN9 (0x100U)
1368 #define EPWM_DC_COMBINATIONAL_TRIPIN10 (0x200U)
1370 #define EPWM_DC_COMBINATIONAL_TRIPIN11 (0x400U)
1372 #define EPWM_DC_COMBINATIONAL_TRIPIN12 (0x800U)
1374 #define EPWM_DC_COMBINATIONAL_TRIPIN13 (0x1000U)
1376 #define EPWM_DC_COMBINATIONAL_TRIPIN14 (0x2000U)
1378 #define EPWM_DC_COMBINATIONAL_TRIPIN15 (0x4000U)
1406 #define EPWM_DC_TBCTR_ZERO (0x1)
1407 #define EPWM_DC_TBCTR_PERIOD (0x2)
1409 #define EPWM_DC_TBCTR_U_CMPA (0x4)
1411 #define EPWM_DC_TBCTR_D_CMPA (0x8)
1413 #define EPWM_DC_TBCTR_U_CMPB (0x10)
1415 #define EPWM_DC_TBCTR_D_CMPB (0x20)
1417 #define EPWM_DC_TBCTR_U_CMPC (0x40)
1419 #define EPWM_DC_TBCTR_D_CMPC (0x80)
1421 #define EPWM_DC_TBCTR_U_CMPD (0x100)
1423 #define EPWM_DC_TBCTR_D_CMPD (0x200)
1570 #define EPWM_GL_REGISTER_TBPRD_TBPRDHR (0x1U)
1571 #define EPWM_GL_REGISTER_CMPA_CMPAHR (0x2U)
1573 #define EPWM_GL_REGISTER_CMPB_CMPBHR (0x4U)
1575 #define EPWM_GL_REGISTER_CMPC (0x8U)
1577 #define EPWM_GL_REGISTER_CMPD (0x10U)
1579 #define EPWM_GL_REGISTER_DBRED_DBREDHR (0x20U)
1581 #define EPWM_GL_REGISTER_DBFED_DBFEDHR (0x40U)
1583 #define EPWM_GL_REGISTER_DBCTL (0x80U)
1585 #define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 (0x100U)
1587 #define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 (0x200U)
1589 #define EPWM_GL_REGISTER_AQCSFRC (0x400U)
1723 #define EPWM_MINDB_BLOCK_A (0x0)
1724 #define EPWM_MINDB_BLOCK_B (0x1)
1733 #define EPWM_MINDB_NO_INVERT (0x0)
1734 #define EPWM_MINDB_INVERT (0x1)
1743 #define EPWM_MINDB_INVERT_LOGICAL_AND (0x0)
1744 #define EPWM_MINDB_LOGICAL_OR (0x1)
1753 #define EPWM_MINDB_PWMB (0x0)
1754 #define EPWM_MINDB_PWM_OUTXBAR_OUT1 (0x1)
1756 #define EPWM_MINDB_PWM_OUTXBAR_OUT2 (0x2)
1758 #define EPWM_MINDB_PWM_OUTXBAR_OUT3 (0x3)
1760 #define EPWM_MINDB_PWM_OUTXBAR_OUT4 (0x4)
1762 #define EPWM_MINDB_PWM_OUTXBAR_OUT5 (0x5)
1764 #define EPWM_MINDB_PWM_OUTXBAR_OUT6 (0x6)
1766 #define EPWM_MINDB_PWM_OUTXBAR_OUT7 (0x7)
1768 #define EPWM_MINDB_PWM_OUTXBAR_OUT8 (0x8)
1770 #define EPWM_MINDB_PWM_OUTXBAR_OUT9 (0x9)
1772 #define EPWM_MINDB_PWM_OUTXBAR_OUT10 (0xA)
1774 #define EPWM_MINDB_PWM_OUTXBAR_OUT11 (0xB)
1776 #define EPWM_MINDB_PWM_OUTXBAR_OUT12 (0xC)
1778 #define EPWM_MINDB_PWM_OUTXBAR_OUT13 (0xD)
1780 #define EPWM_MINDB_PWM_OUTXBAR_OUT14 (0xE)
1782 #define EPWM_MINDB_PWM_OUTXBAR_OUT15 (0xF)
1791 #define EPWM_MINDB_BLOCKING_SIGNAL_SAME (0x0)
1792 #define EPWM_MINDB_BLOCKING_SIGNAL_DIFF (0x1)
1801 #define EPWM_MINDB_ICSS_XBAR_OUT0 (0x0)
1802 #define EPWM_MINDB_ICSS_XBAR_OUT1 (0x1)
1804 #define EPWM_MINDB_ICSS_XBAR_OUT2 (0x2)
1806 #define EPWM_MINDB_ICSS_XBAR_OUT3 (0x3)
1808 #define EPWM_MINDB_ICSS_XBAR_OUT4 (0x4)
1810 #define EPWM_MINDB_ICSS_XBAR_OUT5 (0x5)
1812 #define EPWM_MINDB_ICSS_XBAR_OUT6 (0x6)
1814 #define EPWM_MINDB_ICSS_XBAR_OUT7 (0x7)
1816 #define EPWM_MINDB_ICSS_XBAR_OUT8 (0x8)
1818 #define EPWM_MINDB_ICSS_XBAR_OUT9 (0x9)
1820 #define EPWM_MINDB_ICSS_XBAR_OUT10 (0xA)
1822 #define EPWM_MINDB_ICSS_XBAR_OUT11 (0xB)
1824 #define EPWM_MINDB_ICSS_XBAR_OUT12 (0xC)
1826 #define EPWM_MINDB_ICSS_XBAR_OUT13 (0xD)
1828 #define EPWM_MINDB_ICSS_XBAR_OUT14 (0xE)
1830 #define EPWM_MINDB_ICSS_XBAR_OUT15 (0xF)
2052 #define EPWM_XCMP_ACTIVE (0x0)
2053 #define EPWM_XCMP_SHADOW1 (0x1)
2055 #define EPWM_XCMP_SHADOW2 (0x2)
2057 #define EPWM_XCMP_SHADOW3 (0x3)
2468 #define EPWM_DE_CHANNEL_A (0x0)
2469 #define EPWM_DE_CHANNEL_B (0x1)
2479 #define EPWM_DE_COUNT_UP (0x0)
2480 #define EPWM_DE_COUNT_DOWN (0x1)
2490 #define EPWM_DE_TRIPL (0x1)
2491 #define EPWM_DE_TRIPH (0x0)
2501 #define EPWM_CAPGATE_INPUT_ALWAYS_ON (0U)
2502 #define EPWM_CAPGATE_INPUT_ALWAYS_OFF (1U)
2504 #define EPWM_CAPGATE_INPUT_SYNC (2U)
2506 #define EPWM_CAPGATE_INPUT_SYNC_INVERT (3U)
2516 #define EPWM_CAPTURE_INPUT_CAPIN_SYNC (0U)
2517 #define EPWM_CAPTURE_INPUT_CAPIN_SYNC_INVERT (1U)
2529 #define EPWM_CAPTURE_GATE (1U)
2530 #define EPWM_CAPTURE_INPUT (0U)
2540 #define EPWM_AQ_A_SW_DISABLED_B_SW_DISABLED (0x0U)
2541 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_DISABLED (0x1U)
2543 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_DISABLED (0x2U)
2545 #define EPWM_AQ_A_SW_DISABLED_B_SW_OUTPUT_LOW (0x4U)
2547 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_OUTPUT_LOW (0x5U)
2549 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_OUTPUT_LOW (0x6U)
2551 #define EPWM_AQ_A_SW_DISABLED_B_SW_OUTPUT_HIGH (0x8U)
2553 #define EPWM_AQ_A_SW_OUTPUT_LOW_B_SW_OUTPUT_HIGH (0x9U)
2555 #define EPWM_AQ_A_SW_OUTPUT_HIGH_B_SW_OUTPUT_HIGH (0xAU)
2564 #define EPWM_DCxCTL_STEP (CSL_EPWM_DCBCTL - CSL_EPWM_DCACTL)
2565 #define EPWM_DCxxTRIPSEL (CSL_EPWM_DCALTRIPSEL - CSL_EPWM_DCAHTRIPSEL)
2566 #define EPWM_XREGSHDWxSTS_STEP (CSL_EPWM_XREGSHDW2STS-CSL_EPWM_XREGSHDW1STS)
2567 #define EPWM_XCMPx_ACTIVE_STEP (CSL_EPWM_XCMP2_ACTIVE-CSL_EPWM_XCMP1_ACTIVE)
2568 #define EPWM_XCMPx_STEP (CSL_EPWM_XCMP1_SHDW2-CSL_EPWM_XCMP1_SHDW1)
2569 #define EPWM_XCMPx_SHDWx_STEP (CSL_EPWM_XCMP2_SHDW1-CSL_EPWM_XCMP1_SHDW1)
2570 #define EPWM_LOCK_KEY (0xA5A50000U)
2611 HW_WR_REG16(base + CSL_EPWM_TBCTR, count);
2638 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2639 (HW_RD_REG16(base + CSL_EPWM_TBCTL) |
2640 CSL_EPWM_TBCTL_PHSDIR_MASK));
2647 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2648 (HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2649 ~CSL_EPWM_TBCTL_PHSDIR_MASK));
2683 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2684 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2685 ~(CSL_EPWM_TBCTL_CLKDIV_MASK | CSL_EPWM_TBCTL_HSPCLKDIV_MASK)) |
2686 (((uint16_t)prescaler << CSL_EPWM_TBCTL_CLKDIV_SHIFT) |
2687 ((uint16_t)highSpeedPrescaler << CSL_EPWM_TBCTL_HSPCLKDIV_SHIFT))));
2709 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2710 HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_SWFSYNC_MASK);
2749 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCINSEL,
2750 ((HW_RD_REG16(base + CSL_EPWM_EPWMSYNCINSEL) &
2751 (~CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)) |
2752 ((uint16_t)source & CSL_EPWM_EPWMSYNCINSEL_SEL_MASK)));
2801 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2802 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) |
2846 HW_WR_REG16(base + CSL_EPWM_EPWMSYNCOUTEN,
2847 (HW_RD_REG16(base + CSL_EPWM_EPWMSYNCOUTEN) &
2848 ~((uint16_t)source)));
2875 HW_WR_REG16(base + CSL_EPWM_TBCTL3,
2876 ((HW_RD_REG16(base + CSL_EPWM_TBCTL3) &
2877 ~(CSL_EPWM_TBCTL3_OSSFRCEN_MASK)) |
2878 (uint16_t)trigger));
2905 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2906 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PRDLD_MASK));
2913 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2914 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PRDLD_MASK));
2936 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2937 (HW_RD_REG16(base + CSL_EPWM_TBCTL) | CSL_EPWM_TBCTL_PHSEN_MASK));
2957 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2958 (HW_RD_REG16(base + CSL_EPWM_TBCTL) & ~CSL_EPWM_TBCTL_PHSEN_MASK));
2984 HW_WR_REG16(base + CSL_EPWM_TBCTL,
2985 ((HW_RD_REG16(base + CSL_EPWM_TBCTL) &
2986 ~(CSL_EPWM_TBCTL_CTRMODE_MASK)) | ((uint16_t)counterMode)));
3016 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3017 ((HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
3018 ~(CSL_EPWM_TBCTL2_PRDLDSYNC_MASK)) |
3019 ((uint16_t)shadowLoadMode << CSL_EPWM_TBCTL2_PRDLDSYNC_SHIFT)));
3038 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3039 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) |
3040 CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
3060 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3061 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) &
3062 ~CSL_EPWM_TBCTL2_OSHTSYNCMODE_MASK));
3082 HW_WR_REG16(base + CSL_EPWM_TBCTL2,
3083 (HW_RD_REG16(base + CSL_EPWM_TBCTL2) | CSL_EPWM_TBCTL2_OSHTSYNC_MASK));
3097 static inline uint16_t
3103 return(HW_RD_REG16(base + CSL_EPWM_TBCTR));
3124 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) &
3125 CSL_EPWM_TBSTS_CTRMAX_MASK) ==
3126 CSL_EPWM_TBSTS_CTRMAX_MASK) ?
true :
false);
3147 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3148 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_CTRMAX_MASK));
3169 return(((HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_SYNCI_MASK) ==
3170 CSL_EPWM_TBSTS_SYNCI_MASK) ?
true :
false);
3190 HW_WR_REG16(base + CSL_EPWM_TBSTS,
3191 (HW_RD_REG16(base + CSL_EPWM_TBSTS) | CSL_EPWM_TBSTS_SYNCI_MASK));
3207 static inline uint16_t
3213 return(HW_RD_REG16(base + CSL_EPWM_TBSTS) & CSL_EPWM_TBSTS_CTRDIR_MASK);
3237 HW_WR_REG32(base + CSL_EPWM_TBPHS,
3238 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
3239 ~((uint32_t)CSL_EPWM_TBPHS_TBPHS_MASK)) |
3240 ((uint32_t)phaseCount << CSL_EPWM_TBPHS_TBPHS_SHIFT)));
3266 HW_WR_REG16(base + CSL_EPWM_TBPRD, periodCount);
3280 static inline uint16_t
3286 return(HW_RD_REG16(base + CSL_EPWM_TBPRD));
3357 uint32_t registerOffset;
3361 registerOffset = base + CSL_EPWM_EPWMXLINK2;
3366 registerOffset = base + CSL_EPWM_EPWMXLINKXLOAD;
3371 registerOffset = base + CSL_EPWM_EPWMXLINK;
3377 HW_WR_REG32(registerOffset,
3378 ((HW_RD_REG32(registerOffset) &
3379 ~((uint32_t)CSL_EPWM_EPWMXLINK_TBPRDLINK_MASK << linkComp)) |
3380 ((uint32_t)epwmLink << linkComp)));
3418 uint16_t syncModeOffset;
3419 uint16_t loadModeOffset;
3420 uint16_t shadowModeOffset;
3421 uint32_t registerOffset;
3426 syncModeOffset = CSL_EPWM_CMPCTL_LOADASYNC_SHIFT;
3427 loadModeOffset = CSL_EPWM_CMPCTL_LOADAMODE_SHIFT;
3428 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3432 syncModeOffset = CSL_EPWM_CMPCTL_LOADBSYNC_SHIFT;
3433 loadModeOffset = CSL_EPWM_CMPCTL_LOADBMODE_SHIFT;
3434 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3444 registerOffset = base + CSL_EPWM_CMPCTL;
3448 registerOffset = base + CSL_EPWM_CMPCTL2;
3455 HW_WR_REG16(registerOffset,
3456 ((HW_RD_REG16(registerOffset) &
3457 ~((CSL_EPWM_CMPCTL_LOADASYNC_MAX << syncModeOffset) |
3458 (CSL_EPWM_CMPCTL_LOADAMODE_MAX << loadModeOffset) |
3459 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset))) |
3460 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3461 (((uint16_t)loadMode & CSL_EPWM_CMPCTL_LOADASYNC_MAX) <<
3487 uint16_t shadowModeOffset;
3488 uint32_t registerOffset;
3493 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWAMODE_SHIFT;
3497 shadowModeOffset = CSL_EPWM_CMPCTL_SHDWBMODE_SHIFT;
3507 registerOffset = base + CSL_EPWM_CMPCTL;
3511 registerOffset = base + CSL_EPWM_CMPCTL2;
3517 HW_WR_REG16(registerOffset,
3518 (HW_RD_REG16(registerOffset) |
3519 (CSL_EPWM_CMPCTL_SHDWAMODE_MAX << shadowModeOffset)));
3545 uint32_t registerOffset;
3550 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3561 HW_WR_REG16(registerOffset + 0x2U, compCount);
3568 HW_WR_REG16(registerOffset, compCount);
3587 HW_WR_REG16(base + CSL_EPWM_CMPA + 0x2U, compCount);
3606 HW_WR_REG16(base + CSL_EPWM_CMPB + 0x2U, compCount);
3625 HW_WR_REG16(base + CSL_EPWM_CMPC, compCount);
3644 HW_WR_REG16(base + CSL_EPWM_CMPD, compCount);
3664 static inline uint16_t
3667 uint32_t registerOffset;
3673 registerOffset = base + CSL_EPWM_CMPA + (uint16_t)compModule;
3684 compCount = (uint16_t)((HW_RD_REG32(registerOffset) &
3685 (uint32_t)CSL_EPWM_CMPA_CMPA_MASK) >>
3686 CSL_EPWM_CMPA_CMPA_SHIFT);
3693 compCount = HW_RD_REG16(registerOffset);
3727 return((((HW_RD_REG32(base + CSL_EPWM_CMPCTL) >>
3728 ((((uint16_t)compModule >> 1U) & 0x2U) +
3729 CSL_EPWM_CMPCTL_SHDWAFULL_SHIFT)) &
3730 0x1U) == 0x1U) ?
true:
false);
3771 uint16_t syncModeOffset;
3772 uint16_t shadowModeOffset;
3774 syncModeOffset = CSL_EPWM_AQCTL_LDAQASYNC_SHIFT + (uint16_t)aqModule;
3775 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3781 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3782 ((HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3783 (~((CSL_EPWM_AQCTL_LDAQAMODE_MASK << (uint16_t)aqModule) |
3784 (CSL_EPWM_AQCTL_LDAQASYNC_MAX << (uint16_t)syncModeOffset))) |
3785 (CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)) |
3786 ((((uint16_t)loadMode >> 2U) << syncModeOffset) |
3787 (((uint16_t)loadMode & CSL_EPWM_AQCTL_LDAQAMODE_MASK) <<
3788 (uint16_t)aqModule))));
3811 uint16_t shadowModeOffset;
3813 shadowModeOffset = CSL_EPWM_AQCTL_SHDWAQAMODE_SHIFT + (uint16_t)aqModule;
3819 HW_WR_REG16(base + CSL_EPWM_AQCTL,
3820 (HW_RD_REG16(base + CSL_EPWM_AQCTL) &
3821 ~(CSL_EPWM_AQCTL_SHDWAQAMODE_MAX << shadowModeOffset)));
3853 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3854 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3855 (~CSL_EPWM_AQTSRCSEL_T1SEL_MASK)) |
3856 ((uint16_t)trigger)));
3888 HW_WR_REG16(base + CSL_EPWM_AQTSRCSEL,
3889 ((HW_RD_REG16(base + CSL_EPWM_AQTSRCSEL) &
3890 (~CSL_EPWM_AQTSRCSEL_T2SEL_MASK)) |
3891 ((uint16_t)trigger << CSL_EPWM_AQTSRCSEL_T2SEL_SHIFT)));
3942 uint32_t registerOffset;
3943 uint32_t registerTOffset;
3948 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
3949 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
3954 if(((uint16_t)
event & 0x1U) == 1U)
3959 HW_WR_REG16(base + registerTOffset,
3960 ((HW_RD_REG16(base + registerTOffset) &
3961 ~(CSL_EPWM_AQCTLA_ZRO_MAX << ((uint16_t)event - 1U))) |
3962 ((uint16_t)output << ((uint16_t)event - 1U))));
3969 HW_WR_REG16(base + registerOffset,
3970 ((HW_RD_REG16(base + registerOffset) &
3971 ~(CSL_EPWM_AQCTLA_ZRO_MAX << (uint16_t)event)) |
3972 ((uint16_t)output << (uint16_t)event)));
4065 uint32_t registerOffset;
4070 registerOffset = CSL_EPWM_AQCTLA + (uint16_t)epwmOutput;
4075 HW_WR_REG16(base + registerOffset, action);
4144 uint32_t registerTOffset;
4149 registerTOffset = CSL_EPWM_AQCTLA2 + (uint16_t)epwmOutput;
4154 HW_WR_REG16(base + registerTOffset, action);
4187 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4188 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4189 ~CSL_EPWM_AQSFRC_RLDCSF_MASK) |
4190 ((uint16_t)mode << CSL_EPWM_AQSFRC_RLDCSF_SHIFT)));
4225 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4226 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4227 ~CSL_EPWM_AQCSFRC_CSFA_MASK) |
4228 ((uint16_t)output)));
4232 HW_WR_REG16(base + CSL_EPWM_AQCSFRC,
4233 ((HW_RD_REG16(base + CSL_EPWM_AQCSFRC) &
4234 ~CSL_EPWM_AQCSFRC_CSFB_MASK) |
4235 ((uint16_t)output << CSL_EPWM_AQCSFRC_CSFB_SHIFT)));
4274 HW_WR_REG8(base + CSL_EPWM_AQCSFRC, outputAB);
4311 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4312 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4313 ~CSL_EPWM_AQSFRC_ACTSFA_MASK) |
4314 ((uint16_t)output)));
4318 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4319 ((HW_RD_REG16(base + CSL_EPWM_AQSFRC) &
4320 ~CSL_EPWM_AQSFRC_ACTSFB_MASK) |
4321 ((uint16_t)output << CSL_EPWM_AQSFRC_ACTSFB_SHIFT)));
4350 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4351 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4352 CSL_EPWM_AQSFRC_OTSFA_MASK));
4356 HW_WR_REG16(base + CSL_EPWM_AQSFRC,
4357 (HW_RD_REG16(base + CSL_EPWM_AQSFRC) |
4358 CSL_EPWM_AQSFRC_OTSFB_MASK));
4389 bool enableSwapMode)
4393 mask = (uint16_t)1U << ((uint16_t)output + CSL_EPWM_DBCTL_OUTSWAP_SHIFT);
4400 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4401 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4408 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4409 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4437 bool enableDelayMode)
4441 mask = 1U << ((uint16_t)(delayMode + CSL_EPWM_DBCTL_OUT_MODE_SHIFT));
4448 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4449 (HW_RD_REG16(base + CSL_EPWM_DBCTL) | mask));
4456 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4457 (HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~mask));
4489 shift = (((uint16_t)delayMode ^ 0x1U) + CSL_EPWM_DBCTL_POLSEL_SHIFT);
4494 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4495 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) & ~ (1U << shift)) |
4496 ((uint16_t)polarity << shift)));
4528 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4529 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4530 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT))) |
4531 (input << CSL_EPWM_DBCTL_IN_MODE_SHIFT)));
4569 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4570 (HW_RD_REG16(base + CSL_EPWM_DBCTL) |
4571 CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4578 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4579 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4580 ~CSL_EPWM_DBCTL_DEDB_MODE_MASK));
4585 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4586 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4587 ~(1U << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))) |
4588 (input << (CSL_EPWM_DBCTL_IN_MODE_SHIFT + 1U))));
4618 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4619 ((HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4620 ~CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK) |
4621 (CSL_EPWM_DBCTL2_LOADDBCTLMODE_MASK | (uint16_t)loadMode)));
4642 HW_WR_REG16(base + CSL_EPWM_DBCTL2,
4643 (HW_RD_REG16(base + CSL_EPWM_DBCTL2) &
4644 ~CSL_EPWM_DBCTL2_SHDWDBCTLMODE_MASK));
4672 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4673 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4674 ~CSL_EPWM_DBCTL_LOADREDMODE_MASK) |
4675 ((uint16_t)CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK |
4676 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADREDMODE_SHIFT))));
4697 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4698 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4699 ~CSL_EPWM_DBCTL_SHDWDBREDMODE_MASK));
4727 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4728 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4729 ~CSL_EPWM_DBCTL_LOADFEDMODE_MASK) |
4730 (CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK |
4731 ((uint16_t)loadMode << CSL_EPWM_DBCTL_LOADFEDMODE_SHIFT))));
4752 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4753 (HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4754 ~CSL_EPWM_DBCTL_SHDWDBFEDMODE_MASK));
4782 HW_WR_REG16(base + CSL_EPWM_DBCTL,
4783 ((HW_RD_REG16(base + CSL_EPWM_DBCTL) &
4784 ~CSL_EPWM_DBCTL_HALFCYCLE_MASK) |
4785 ((uint16_t)clockMode << CSL_EPWM_DBCTL_HALFCYCLE_SHIFT)));
4812 HW_WR_REG16(base + CSL_EPWM_DBRED, redCount);
4839 HW_WR_REG16(base + CSL_EPWM_DBFED, fedCount);
4862 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4863 (HW_RD_REG16(base + CSL_EPWM_PCCTL) | CSL_EPWM_PCCTL_CHPEN_MASK));
4883 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4884 (HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPEN_MASK));
4913 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4914 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) & ~CSL_EPWM_PCCTL_CHPDUTY_MASK) |
4915 (dutyCycleCount << CSL_EPWM_PCCTL_CHPDUTY_SHIFT)));
4944 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4945 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4946 ~(uint16_t)CSL_EPWM_PCCTL_CHPFREQ_MASK) |
4947 (freqDiv << CSL_EPWM_PCCTL_CHPFREQ_SHIFT)));
4971 DebugP_assert(firstPulseWidth <= CSL_EPWM_PCCTL_OSHTWTH_MAX);
4976 HW_WR_REG16(base + CSL_EPWM_PCCTL,
4977 ((HW_RD_REG16(base + CSL_EPWM_PCCTL) &
4978 ~(uint16_t)CSL_EPWM_PCCTL_OSHTWTH_MASK) |
4979 (firstPulseWidth << CSL_EPWM_PCCTL_OSHTWTH_SHIFT)));
5024 HW_WR_REG32(base + CSL_EPWM_TZSEL,
5025 (HW_RD_REG32(base + CSL_EPWM_TZSEL) | tzSignal));
5067 HW_WR_REG32(base + CSL_EPWM_TZSEL,
5068 (HW_RD_REG32(base + CSL_EPWM_TZSEL) & ~tzSignal));
5111 HW_WR_REG16(base + CSL_EPWM_TZDCSEL,
5112 ((HW_RD_REG16(base + CSL_EPWM_TZDCSEL) &
5113 ~(CSL_EPWM_TZDCSEL_DCAEVT1_MASK << (uint16_t)dcType)) |
5114 ((uint16_t)dcEvent << (uint16_t)dcType)));
5136 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5137 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5157 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5158 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) & ~CSL_EPWM_TZCTL2_ETZE_MASK));
5200 HW_WR_REG16(base + CSL_EPWM_TZCTL,
5201 ((HW_RD_REG16(base + CSL_EPWM_TZCTL) &
5202 ~(CSL_EPWM_TZCTL_TZA_MASK << (uint16_t)tzEvent)) |
5203 ((uint16_t)tzAction << (uint16_t)tzEvent)));
5251 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5252 ((HW_RD_REG16(base + CSL_EPWM_TZCTL2) &
5253 ~(CSL_EPWM_TZCTL2_TZAU_MASK << (uint16_t)tzAdvEvent)) |
5254 ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)));
5256 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5257 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5303 HW_WR_REG16(base + CSL_EPWM_TZCTLDCA,
5304 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCA) &
5305 ~(CSL_EPWM_TZCTLDCA_DCAEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5306 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5308 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5309 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5354 HW_WR_REG16(base + CSL_EPWM_TZCTLDCB,
5355 ((HW_RD_REG16(base + CSL_EPWM_TZCTLDCB) &
5356 ~(CSL_EPWM_TZCTLDCB_DCBEVT1U_MASK << (uint16_t)tzAdvDCEvent)) |
5357 ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)));
5359 HW_WR_REG16(base + CSL_EPWM_TZCTL2,
5360 (HW_RD_REG16(base + CSL_EPWM_TZCTL2) | CSL_EPWM_TZCTL2_ETZE_MASK));
5392 DebugP_assert((tzInterrupt >= 0U) && (tzInterrupt <= 0x80U));
5397 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5398 (HW_RD_REG16(base + CSL_EPWM_TZEINT) | tzInterrupt));
5430 DebugP_assert((tzInterrupt > 0U) && (tzInterrupt <= 0x80U));
5435 HW_WR_REG16(base + CSL_EPWM_TZEINT,
5436 (HW_RD_REG16(base + CSL_EPWM_TZEINT) & ~tzInterrupt));
5460 static inline uint16_t
5466 return(HW_RD_REG16(base + CSL_EPWM_TZFLG) & 0xFFU);
5492 static inline uint16_t
5498 return(HW_RD_REG16(base + CSL_EPWM_TZCBCFLG) & 0x1FFU);
5522 static inline uint16_t
5528 return(HW_RD_REG16(base + CSL_EPWM_TZOSTFLG) & 0x1FFU);
5558 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5559 ((HW_RD_REG16(base + CSL_EPWM_TZCLR) &
5560 ~CSL_EPWM_TZCLR_CBCPULSE_MASK) |
5561 ((uint16_t)clearEvent << CSL_EPWM_TZCLR_CBCPULSE_SHIFT)));
5599 HW_WR_REG16(base + CSL_EPWM_TZCLR,
5600 (HW_RD_REG16(base + CSL_EPWM_TZCLR) | tzFlags));
5637 HW_WR_REG16(base + CSL_EPWM_TZCBCCLR,
5638 (HW_RD_REG16(base + CSL_EPWM_TZCBCCLR) | tzCBCFlags));
5674 HW_WR_REG16(base + CSL_EPWM_TZOSTCLR,
5675 (HW_RD_REG16(base + CSL_EPWM_TZOSTCLR) | tzOSTFlags));
5709 HW_WR_REG16(base + CSL_EPWM_TZFRC,
5710 (HW_RD_REG16(base + CSL_EPWM_TZFRC) | tzForceEvent));
5736 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5737 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) | tzOutput));
5763 HW_WR_REG16(base + CSL_EPWM_TZTRIPOUTSEL,
5764 (HW_RD_REG16(base + CSL_EPWM_TZTRIPOUTSEL) & ~tzOutput));
5787 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5788 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_INTEN_MASK));
5808 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5809 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_INTEN_MASK));
5840 uint16_t mixedSource)
5847 DebugP_assert(((interruptSource > 0U) && (interruptSource < 9U)) ||
5848 (interruptSource == 10U) || (interruptSource == 12U) ||
5849 (interruptSource == 14U));
5859 intSource = interruptSource >> 1U;
5864 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5865 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
5866 CSL_EPWM_ETSEL_INTSELCMP_MASK));
5873 intSource = interruptSource;
5878 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5879 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5880 ~CSL_EPWM_ETSEL_INTSELCMP_MASK));
5884 intSource = interruptSource;
5889 HW_WR_REG16(base + CSL_EPWM_ETINTMIXEN, mixedSource);
5893 intSource = interruptSource;
5899 HW_WR_REG16(base + CSL_EPWM_ETSEL,
5900 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
5901 ~CSL_EPWM_ETSEL_INTSEL_MASK) | intSource));
5929 HW_WR_REG16(base + CSL_EPWM_ETPS,
5930 (HW_RD_REG16(base + CSL_EPWM_ETPS) | CSL_EPWM_ETPS_INTPSSEL_MASK));
5932 HW_WR_REG16(base + CSL_EPWM_ETINTPS,
5933 ((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
5934 ~CSL_EPWM_ETINTPS_INTPRD2_MASK) | eventCount));
5956 return(((HW_RD_REG16(base + CSL_EPWM_ETFLG) & 0x1U) ==
5957 0x1U) ?
true :
false);
5977 HW_WR_REG16(base + CSL_EPWM_ETCLR, (CSL_EPWM_ETCLR_INT_MASK));
6000 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6001 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6002 CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
6023 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6024 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6025 ~CSL_EPWM_ETCNTINITCTL_INTINITEN_MASK));
6049 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6050 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6051 CSL_EPWM_ETCNTINITCTL_INTINITFRC_MASK));
6074 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_INTINIT_MAX);
6079 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6080 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6081 ~CSL_EPWM_ETCNTINIT_INTINIT_MASK) |
6082 (uint16_t)(eventCount & CSL_EPWM_ETCNTINIT_INTINIT_MASK)));
6096 static inline uint16_t
6102 return(((HW_RD_REG16(base + CSL_EPWM_ETINTPS) &
6103 CSL_EPWM_ETINTPS_INTCNT2_MASK) >>
6104 CSL_EPWM_ETINTPS_INTCNT2_SHIFT));
6124 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6125 (HW_RD_REG16(base + CSL_EPWM_ETFRC) | CSL_EPWM_ETFRC_INT_MASK));
6154 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6155 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCAEN_MASK));
6159 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6160 (HW_RD_REG16(base + CSL_EPWM_ETSEL) | CSL_EPWM_ETSEL_SOCBEN_MASK));
6187 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6188 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCAEN_MASK));
6192 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6193 (HW_RD_REG16(base + CSL_EPWM_ETSEL) & ~CSL_EPWM_ETSEL_SOCBEN_MASK));
6233 uint16_t mixedSource)
6242 source = (uint16_t)socSource >> 1U;
6246 source = (uint16_t)socSource;
6254 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6255 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6256 ~CSL_EPWM_ETSEL_SOCASEL_MASK) |
6257 (source << CSL_EPWM_ETSEL_SOCASEL_SHIFT)));
6270 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6271 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6272 ~CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6282 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6283 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6284 CSL_EPWM_ETSEL_SOCASELCMP_MASK));
6291 HW_WR_REG16(base + CSL_EPWM_ETSOCAMIXEN, mixedSource);
6305 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6306 ((HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6307 ~CSL_EPWM_ETSEL_SOCBSEL_MASK) |
6308 (source << CSL_EPWM_ETSEL_SOCBSEL_SHIFT)));
6321 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6322 (HW_RD_REG16(base + CSL_EPWM_ETSEL) &
6323 ~CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6333 HW_WR_REG16(base + CSL_EPWM_ETSEL,
6334 (HW_RD_REG16(base + CSL_EPWM_ETSEL) |
6335 CSL_EPWM_ETSEL_SOCBSELCMP_MASK));
6342 HW_WR_REG16(base + CSL_EPWM_ETSOCBMIXEN, mixedSource);
6379 uint16_t preScaleCount)
6384 DebugP_assert(preScaleCount <= CSL_EPWM_ETSOCPS_SOCAPRD2_MAX);
6389 HW_WR_REG16(base + CSL_EPWM_ETPS,
6390 (HW_RD_REG16(base + CSL_EPWM_ETPS) |
6391 CSL_EPWM_ETPS_SOCPSSEL_MASK));
6398 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6399 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6400 ~CSL_EPWM_ETSOCPS_SOCAPRD2_MASK) |
6408 HW_WR_REG16(base + CSL_EPWM_ETSOCPS,
6409 ((HW_RD_REG16(base + CSL_EPWM_ETSOCPS) &
6410 ~CSL_EPWM_ETSOCPS_SOCBPRD2_MASK) |
6411 (preScaleCount << CSL_EPWM_ETSOCPS_SOCBPRD2_SHIFT)));
6438 return((((HW_RD_REG16(base + CSL_EPWM_ETFLG) >>
6439 ((uint16_t)adcSOCType + CSL_EPWM_ETFLG_SOCA_SHIFT)) &
6440 0x1U) == 0x1U) ?
true :
false);
6465 HW_WR_REG16(base + CSL_EPWM_ETCLR,
6466 (HW_RD_REG16(base + CSL_EPWM_ETCLR) |
6467 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETCLR_SOCA_SHIFT)));
6496 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6497 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) | 1U <<
6498 ((uint16_t)adcSOCType + CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT)));
6526 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6527 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) &
6528 ~(1U << ((uint16_t)adcSOCType +
6529 CSL_EPWM_ETCNTINITCTL_SOCAINITEN_SHIFT))));
6555 HW_WR_REG16(base + CSL_EPWM_ETCNTINITCTL,
6556 (HW_RD_REG16(base + CSL_EPWM_ETCNTINITCTL) |
6557 1U << ((uint16_t)adcSOCType +
6558 CSL_EPWM_ETCNTINITCTL_SOCAINITFRC_SHIFT)));
6581 uint16_t eventCount)
6586 DebugP_assert(eventCount <= CSL_EPWM_ETCNTINIT_SOCAINIT_MAX);
6593 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6594 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6595 ~CSL_EPWM_ETCNTINIT_SOCAINIT_MASK) |
6596 (uint16_t)(eventCount << CSL_EPWM_ETCNTINIT_SOCAINIT_SHIFT)));
6600 HW_WR_REG16(base + CSL_EPWM_ETCNTINIT,
6601 ((HW_RD_REG16(base + CSL_EPWM_ETCNTINIT) &
6602 ~CSL_EPWM_ETCNTINIT_SOCBINIT_MASK) |
6603 (eventCount << CSL_EPWM_ETCNTINIT_SOCBINIT_SHIFT)));
6622 static inline uint16_t
6626 uint16_t eventCount;
6633 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6634 CSL_EPWM_ETSOCPS_SOCACNT2_SHIFT) &
6635 CSL_EPWM_ETSOCPS_SOCACNT2_MAX;
6639 eventCount = (HW_RD_REG16(base + CSL_EPWM_ETSOCPS) >>
6640 CSL_EPWM_ETSOCPS_SOCBCNT2_SHIFT) &
6641 CSL_EPWM_ETSOCPS_SOCBCNT2_MAX;
6668 HW_WR_REG16(base + CSL_EPWM_ETFRC,
6669 (HW_RD_REG16(base + CSL_EPWM_ETFRC) |
6670 1U << ((uint16_t)adcSOCType + CSL_EPWM_ETFRC_SOCA_SHIFT)));
6709 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
6710 ((HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) &
6711 ~(CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK <<
6712 ((uint16_t)dcType << 2U))) |
6713 ((uint16_t)tripSource << ((uint16_t)dcType << 2U))));
6736 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6737 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKE_MASK));
6757 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6758 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_BLANKE_MASK));
6779 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6780 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) | CSL_EPWM_DCFCTL_BLANKINV_MASK));
6800 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6801 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6802 ~CSL_EPWM_DCFCTL_BLANKINV_MASK));
6827 uint16_t mixedSource)
6834 HW_WR_REG16(base + CSL_EPWM_BLANKPULSEMIXSEL, mixedSource);
6840 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6841 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6842 ~CSL_EPWM_DCFCTL_PULSESEL_MASK) |
6843 ((uint16_t)((uint32_t)blankingPulse <<
6844 CSL_EPWM_DCFCTL_PULSESEL_SHIFT))));
6872 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6873 ((HW_RD_REG16(base + CSL_EPWM_DCFCTL) & ~CSL_EPWM_DCFCTL_SRCSEL_MASK) |
6874 ((uint16_t)filterInput)));
6898 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6899 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) |
6900 CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6920 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6921 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6922 ~CSL_EPWM_DCFCTL_EDGEFILTSEL_MASK));
6948 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6949 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6950 ~CSL_EPWM_DCFCTL_EDGEMODE_MASK) |
6951 (edgeMode << CSL_EPWM_DCFCTL_EDGEMODE_SHIFT));
6982 HW_WR_REG16(base + CSL_EPWM_DCFCTL,
6983 (HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
6984 ~CSL_EPWM_DCFCTL_EDGECOUNT_MASK) |
6985 (edgeCount << CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT));
7000 static inline uint16_t
7006 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7007 CSL_EPWM_DCFCTL_EDGECOUNT_MASK) >>
7008 CSL_EPWM_DCFCTL_EDGECOUNT_SHIFT);
7023 static inline uint16_t
7029 return((HW_RD_REG16(base + CSL_EPWM_DCFCTL) &
7030 CSL_EPWM_DCFCTL_EDGESTATUS_MASK) >>
7031 CSL_EPWM_DCFCTL_EDGESTATUS_SHIFT);
7054 HW_WR_REG16(base + CSL_EPWM_DCFOFFSET, windowOffsetCount);
7076 HW_WR_REG16(base + CSL_EPWM_DCFWINDOW, windowLengthCount);
7090 static inline uint16_t
7096 return(HW_RD_REG16(base + CSL_EPWM_DCFOFFSETCNT));
7110 static inline uint16_t
7116 return(HW_RD_REG16(base + CSL_EPWM_DCFWINDOWCNT));
7154 uint32_t registerOffset;
7163 HW_WR_REG16(base + registerOffset,
7164 ((HW_RD_REG16(base + registerOffset) &
7165 ~CSL_EPWM_DCACTL_EVT1SRCSEL_MASK) |
7166 (uint16_t)dcEventSource));
7170 HW_WR_REG16(base + registerOffset,
7171 ((HW_RD_REG16(base + registerOffset) &
7172 ~CSL_EPWM_DCACTL_EVT2SRCSEL_MASK) |
7173 ((uint16_t)dcEventSource << CSL_EPWM_DCACTL_EVT2SRCSEL_SHIFT)));
7209 uint32_t registerOffset;
7218 HW_WR_REG16(base + registerOffset,
7219 ((HW_RD_REG16(base + registerOffset) &
7220 ~CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_MASK) |
7221 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT1FRCSYNCSEL_SHIFT)));
7225 HW_WR_REG16(base + registerOffset,
7226 ((HW_RD_REG16(base + registerOffset) &
7227 ~CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_MASK) |
7228 ((uint16_t)syncMode << CSL_EPWM_DCACTL_EVT2FRCSYNCSEL_SHIFT)));
7252 uint32_t registerOffset;
7259 HW_WR_REG16(base + registerOffset,
7260 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7283 uint32_t registerOffset;
7290 HW_WR_REG16(base + registerOffset,
7291 (HW_RD_REG16(base + registerOffset) & ~CSL_EPWM_DCACTL_EVT1SOCE_MASK));
7314 uint32_t registerOffset;
7321 HW_WR_REG16(base + registerOffset,
7322 (HW_RD_REG16(base + registerOffset) | CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7345 uint32_t registerOffset;
7352 HW_WR_REG16(base + registerOffset,
7353 (HW_RD_REG16(base + registerOffset) &
7354 ~CSL_EPWM_DCACTL_EVT1SYNCE_MASK));
7387 uint32_t registerOffset;
7396 HW_WR_REG16(base + registerOffset,
7397 ((HW_RD_REG16(base + registerOffset) &
7398 ~CSL_EPWM_DCACTL_EVT1LATSEL_MASK) |
7399 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT1LATSEL_SHIFT)));
7403 HW_WR_REG16(base + registerOffset,
7404 ((HW_RD_REG16(base + registerOffset) &
7405 ~CSL_EPWM_DCACTL_EVT2LATSEL_MASK) |
7406 ((uint16_t)latchMode << CSL_EPWM_DCACTL_EVT2LATSEL_SHIFT)));
7445 uint32_t registerOffset;
7454 HW_WR_REG16(base + registerOffset,
7455 ((HW_RD_REG16(base + registerOffset) &
7456 ~CSL_EPWM_DCACTL_EVT1LATCLRSEL_MASK) |
7457 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT1LATCLRSEL_SHIFT)));
7461 HW_WR_REG16(base + registerOffset,
7462 ((HW_RD_REG16(base + registerOffset) &
7463 ~CSL_EPWM_DCACTL_EVT2LATCLRSEL_MASK) |
7464 ((uint16_t)clearEvent << CSL_EPWM_DCACTL_EVT2LATCLRSEL_SHIFT)));
7496 uint32_t registerOffset;
7506 status = HW_RD_REG16(base + registerOffset) &
7507 CSL_EPWM_DCACTL_EVT1LAT_MASK;
7511 status = HW_RD_REG16(base + registerOffset) &
7512 CSL_EPWM_DCACTL_EVT2LAT_MASK;
7515 return(status != 0U);
7538 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7539 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) | CSL_EPWM_DCCAPCTL_CAPE_MASK));
7559 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7560 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7561 ~CSL_EPWM_DCCAPCTL_CAPE_MASK));
7582 if(enableShadowMode)
7587 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7588 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7589 ~CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7596 HW_WR_REG16(base + CSL_EPWM_DCCAPCTL,
7597 (HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) |
7598 CSL_EPWM_DCCAPCTL_SHDWMODE_MASK));
7622 return((HW_RD_REG16(base + CSL_EPWM_DCCAPCTL) &
7623 CSL_EPWM_DCCAPCTL_CAPSTS_MASK) == CSL_EPWM_DCCAPCTL_CAPSTS_MASK);
7639 static inline uint16_t
7645 return(HW_RD_REG16(base + CSL_EPWM_DCCAP));
7674 uint32_t registerOffset;
7680 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7686 HW_WR_REG16(base + registerOffset,
7687 (HW_RD_REG16(base + registerOffset) | tripInput));
7692 HW_WR_REG16(base + CSL_EPWM_DCTRIPSEL,
7693 (HW_RD_REG16(base + CSL_EPWM_DCTRIPSEL) |
7694 (CSL_EPWM_DCTRIPSEL_DCAHCOMPSEL_MASK << ((uint16_t)dcType << 2U))));
7723 uint32_t registerOffset;
7729 registerOffset = CSL_EPWM_DCAHTRIPSEL +
7735 HW_WR_REG16(base + registerOffset,
7736 (HW_RD_REG16(base + registerOffset) & ~tripInput));
7762 base + CSL_EPWM_CAPCTL,
7763 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) | CSL_EPWM_CAPCTL_SRCSEL_MASK)
7786 base + CSL_EPWM_CAPCTL,
7787 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_SRCSEL_MASK))
7816 base + CSL_EPWM_CAPCTL,
7817 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_CAPGATEPOL_MASK)) |
7818 ((uint16_t)polSel << CSL_EPWM_CAPCTL_CAPGATEPOL_SHIFT));
7844 base + CSL_EPWM_CAPCTL,
7845 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_CAPINPOL_MASK)) |
7846 ((uint16_t)polSel << CSL_EPWM_CAPCTL_CAPINPOL_SHIFT));
7867 base + CSL_EPWM_CAPCTL,
7868 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) & (~CSL_EPWM_CAPCTL_PULSECTL_MASK)) |
7869 (((uint16_t)1U) << CSL_EPWM_CAPCTL_PULSECTL_SHIFT));
7891 base + CSL_EPWM_CAPCTL,
7892 (HW_RD_REG16(base + CSL_EPWM_CAPCTL) | (CSL_EPWM_CAPCTL_PULSECTL_MASK)) &
7893 (~(((uint16_t)1U) << CSL_EPWM_CAPCTL_PULSECTL_SHIFT)));
7914 base + CSL_EPWM_CAPCTL,
7915 HW_RD_REG16(base + CSL_EPWM_CAPCTL) | (CSL_EPWM_CAPCTL_FRCLOAD_MASK));
7952 base + CSL_EPWM_CAPTRIPSEL,
7953 (HW_RD_REG16(base + CSL_EPWM_CAPTRIPSEL) & (~CSL_EPWM_CAPTRIPSEL_CAPGATECOMPSEL_MASK)) |
7954 (((uint16_t)tripSource) << CSL_EPWM_CAPTRIPSEL_CAPGATECOMPSEL_SHIFT));
7959 base + CSL_EPWM_CAPTRIPSEL,
7960 (HW_RD_REG16(base + CSL_EPWM_CAPTRIPSEL) & (~CSL_EPWM_CAPTRIPSEL_CAPINCOMPSEL_MASK)) |
7961 (((uint16_t)tripSource) << CSL_EPWM_CAPTRIPSEL_CAPINCOMPSEL_SHIFT));
7997 base + CSL_EPWM_CAPGATETRIPSEL, tripInput);
8006 base + CSL_EPWM_CAPINTRIPSEL, tripInput);
8045 base + CSL_EPWM_CAPGATETRIPSEL,
8046 HW_RD_REG16(base + CSL_EPWM_CAPGATETRIPSEL) & (~tripInput));
8055 base + CSL_EPWM_CAPINTRIPSEL,
8056 HW_RD_REG16(base + CSL_EPWM_CAPGATETRIPSEL) & (~tripInput));
8080 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8081 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) | CSL_EPWM_VCAPCTL_VCAPE_MASK));
8101 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8102 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) & ~CSL_EPWM_VCAPCTL_VCAPE_MASK));
8126 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8127 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
8128 CSL_EPWM_VCAPCTL_VCAPSTART_MASK));
8152 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8153 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8154 ~CSL_EPWM_VCAPCTL_TRIGSEL_MASK) |
8155 ((uint16_t)trigger << CSL_EPWM_VCAPCTL_TRIGSEL_SHIFT)));
8190 HW_WR_REG16(base + CSL_EPWM_VCNTCFG,
8191 ((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8192 ~(CSL_EPWM_VCNTCFG_STARTEDGE_MASK | CSL_EPWM_VCNTCFG_STOPEDGE_MASK)) |
8193 (startCount | (stopCount << CSL_EPWM_VCNTCFG_STOPEDGE_SHIFT))));
8213 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8214 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) |
8215 CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
8235 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8236 (HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8237 ~CSL_EPWM_VCAPCTL_EDGEFILTDLYSEL_MASK));
8258 HW_WR_REG16(base + CSL_EPWM_SWVDELVAL, delayOffsetValue);
8279 HW_WR_REG16(base + CSL_EPWM_VCAPCTL,
8280 ((HW_RD_REG16(base + CSL_EPWM_VCAPCTL) &
8281 ~CSL_EPWM_VCAPCTL_VDELAYDIV_MASK) |
8282 ((uint16_t)delayMode << CSL_EPWM_VCAPCTL_VDELAYDIV_SHIFT)));
8309 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8310 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ==
8311 CSL_EPWM_VCNTCFG_STARTEDGESTS_MASK) ?
true :
false);
8318 return(((HW_RD_REG16(base + CSL_EPWM_VCNTCFG) &
8319 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ==
8320 CSL_EPWM_VCNTCFG_STOPEDGESTS_MASK) ?
true :
false);
8338 static inline uint16_t
8344 return(HW_RD_REG16(base + CSL_EPWM_VCNTVAL));
8358 static inline uint16_t
8364 return(HW_RD_REG16(base + CSL_EPWM_HWVDELVAL));
8386 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8387 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_GLD_MASK));
8408 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8409 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLD_MASK));
8447 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8448 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
8449 ~CSL_EPWM_GLDCTL_GLDMODE_MASK) |
8450 ((uint16_t)loadTrigger << CSL_EPWM_GLDCTL_GLDMODE_SHIFT)));
8480 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8481 ((HW_RD_REG16(base + CSL_EPWM_GLDCTL) & ~CSL_EPWM_GLDCTL_GLDPRD_MASK) |
8482 (prescalePulseCount << CSL_EPWM_GLDCTL_GLDPRD_SHIFT)));
8498 static inline uint16_t
8504 return((HW_RD_REG16(base + CSL_EPWM_GLDCTL) >>
8505 CSL_EPWM_GLDCTL_GLDCNT_SHIFT) & CSL_EPWM_GLDCTL_GLDCNT_MAX);
8527 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8528 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) &
8529 ~CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8551 HW_WR_REG16(base + CSL_EPWM_GLDCTL,
8552 (HW_RD_REG16(base + CSL_EPWM_GLDCTL) | CSL_EPWM_GLDCTL_OSHTMODE_MASK));
8574 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8575 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_OSHTLD_MASK));
8596 HW_WR_REG16(base + CSL_EPWM_GLDCTL2,
8597 (HW_RD_REG16(base + CSL_EPWM_GLDCTL2) | CSL_EPWM_GLDCTL2_GFRCLD_MASK));
8631 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8636 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8637 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) | loadRegister));
8672 DebugP_assert((loadRegister > 0x0000U) && (loadRegister < 0x0800U));
8678 HW_WR_REG16(base + CSL_EPWM_GLDCFG,
8679 (HW_RD_REG16(base + CSL_EPWM_GLDCFG) & ~loadRegister));
8701 HW_WR_REG32(base + CSL_EPWM_EPWMLOCK,
8725 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8726 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8727 CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8731 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8732 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) |
8733 CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8754 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8755 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8756 ~CSL_EPWM_MINDBCFG_ENABLEA_MASK));
8760 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8761 (HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8762 ~CSL_EPWM_MINDBCFG_ENABLEB_MASK));
8786 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8787 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8788 ~CSL_EPWM_MINDBCFG_INVERTA_MASK) |
8789 (invert<<CSL_EPWM_MINDBCFG_INVERTA_SHIFT)));
8793 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8794 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8795 ~CSL_EPWM_MINDBCFG_INVERTB_MASK) |
8796 (invert<<CSL_EPWM_MINDBCFG_INVERTB_SHIFT)));
8817 uint32_t referenceSignal)
8821 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8822 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8823 ~CSL_EPWM_MINDBCFG_POLSELA_MASK) |
8824 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELA_SHIFT)));
8828 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8829 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8830 ~CSL_EPWM_MINDBCFG_POLSELB_MASK) |
8831 (referenceSignal<<CSL_EPWM_MINDBCFG_POLSELB_SHIFT)));
8851 uint32_t blockingSignal)
8855 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8856 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8857 ~CSL_EPWM_MINDBCFG_SELBLOCKA_MASK) |
8858 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKA_SHIFT)));
8862 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8863 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8864 ~CSL_EPWM_MINDBCFG_SELBLOCKB_MASK) |
8865 (blockingSignal<<CSL_EPWM_MINDBCFG_SELBLOCKB_SHIFT)));
8884 uint32_t referenceSignal)
8888 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8889 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8890 ~CSL_EPWM_MINDBCFG_SELA_MASK) |
8891 (referenceSignal<<CSL_EPWM_MINDBCFG_SELA_SHIFT)));
8895 HW_WR_REG32(base + CSL_EPWM_MINDBCFG,
8896 ((HW_RD_REG32(base + CSL_EPWM_MINDBCFG) &
8897 ~CSL_EPWM_MINDBCFG_SELB_MASK) |
8898 (referenceSignal<<CSL_EPWM_MINDBCFG_SELB_SHIFT)));
8914 static inline uint32_t
8921 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8922 CSL_EPWM_MINDBDLY_DELAYA_MASK);
8926 retval = (HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8927 CSL_EPWM_MINDBDLY_DELAYB_MASK);
8952 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
8953 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8954 ~CSL_EPWM_MINDBDLY_DELAYA_MASK) |
8955 (delay<<CSL_EPWM_MINDBDLY_DELAYA_SHIFT)));
8959 HW_WR_REG32(base + CSL_EPWM_MINDBDLY,
8960 ((HW_RD_REG32(base + CSL_EPWM_MINDBDLY) &
8961 ~CSL_EPWM_MINDBDLY_DELAYB_MASK) |
8962 (delay<<CSL_EPWM_MINDBDLY_DELAYB_SHIFT)));
8986 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
8987 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
8988 ~CSL_EPWM_LUTCTLA_BYPASS_MASK));
8992 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
8993 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
8994 ~CSL_EPWM_LUTCTLB_BYPASS_MASK));
9015 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9016 (HW_RD_REG32(base + CSL_EPWM_LUTCTLA) |
9017 CSL_EPWM_LUTCTLA_BYPASS_MASK));
9021 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9022 (HW_RD_REG32(base + CSL_EPWM_LUTCTLB) |
9023 CSL_EPWM_LUTCTLB_BYPASS_MASK));
9045 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9046 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9047 ~CSL_EPWM_LUTCTLA_SELXBAR_MASK) |
9048 (xbarInput<<CSL_EPWM_LUTCTLA_SELXBAR_SHIFT)));
9052 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9053 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9054 ~CSL_EPWM_LUTCTLB_SELXBAR_MASK) |
9055 (xbarInput<<CSL_EPWM_LUTCTLB_SELXBAR_SHIFT)));
9079 HW_WR_REG32(base + CSL_EPWM_LUTCTLA,
9080 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLA) &
9081 ~(CSL_EPWM_LUTCTLA_LUTDEC0_MAX <<
9082 (CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))) |
9083 (force<<(CSL_EPWM_LUTCTLA_LUTDEC0_SHIFT+decx))));
9087 HW_WR_REG32(base + CSL_EPWM_LUTCTLB,
9088 ((HW_RD_REG32(base + CSL_EPWM_LUTCTLB) &
9089 ~(CSL_EPWM_LUTCTLB_LUTDEC0_MAX <<
9090 (CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))) |
9091 (force<<(CSL_EPWM_LUTCTLB_LUTDEC0_SHIFT+decx))));
9126 HW_WR_REG32(base + CSL_EPWM_TBPHS, phaseCount<<8U);
9156 HW_WR_REG32(base + CSL_EPWM_TBPHS,
9157 ((HW_RD_REG32(base + CSL_EPWM_TBPHS) &
9158 ~((uint32_t)CSL_EPWM_TBPHS_TBPHSHR_MASK)) |
9159 ((uint32_t)hrPhaseCount << (CSL_EPWM_TBPHS_TBPHSHR_SHIFT + 8U))));
9186 DebugP_assert(hrPeriodCount <= CSL_EPWM_TBPRDHR_TBPRDHR_MAX);
9191 HW_WR_REG16(base + CSL_EPWM_TBPRDHR, hrPeriodCount << 8);
9205 static inline uint16_t
9211 return(HW_RD_REG16(base + CSL_EPWM_TBPRDHR) >> 8U);
9247 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9248 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9249 ~(CSL_EPWM_HRCNFG_EDGMODE_MAX << (uint16_t)channel)) |
9250 ((uint16_t)mepEdgeMode << (uint16_t)channel)));
9284 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9285 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9286 ~(CSL_EPWM_HRCNFG_CTLMODE_MAX << ((uint16_t)channel + 2U))) |
9287 ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))));
9322 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9323 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) &
9324 ~(CSL_EPWM_HRCNFG_HRLOAD_MAX << ((uint16_t)channel + 3U))) |
9325 ((uint16_t)loadEvent << ((uint16_t)channel + 3U))));
9348 if(enableOutputSwap)
9350 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9351 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_SWAPAB_MASK);
9355 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9356 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_SWAPAB_MASK);
9381 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9382 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~(CSL_EPWM_HRCNFG_SELOUTB_MASK)) |
9383 ((uint16_t)outputOnB << CSL_EPWM_HRCNFG_SELOUTB_SHIFT)));
9404 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9405 HW_RD_REG16(base + CSL_EPWM_HRCNFG) | CSL_EPWM_HRCNFG_AUTOCONV_MASK);
9426 HW_WR_REG16(base + CSL_EPWM_HRCNFG,
9427 HW_RD_REG16(base + CSL_EPWM_HRCNFG) & ~CSL_EPWM_HRCNFG_AUTOCONV_MASK);
9447 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9448 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_HRPE_MASK);
9468 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9469 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_HRPE_MASK);
9490 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9491 HW_RD_REG16(base + CSL_EPWM_HRPCTL) | CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9511 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9512 HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_TBPHSHRLOADE_MASK);
9551 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9552 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) &
9553 ~(CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK | CSL_EPWM_HRPCTL_PWMSYNCSEL_MASK)) |
9554 ((uint16_t)syncPulseSource << 1U)));
9558 HW_WR_REG16(base + CSL_EPWM_HRPCTL,
9559 ((HW_RD_REG16(base + CSL_EPWM_HRPCTL) & ~CSL_EPWM_HRPCTL_PWMSYNCSELX_MASK) |
9560 ((uint16_t)syncPulseSource << CSL_EPWM_HRPCTL_PWMSYNCSELX_SHIFT)));
9587 HW_WR_REG16(base + CSL_EPWM_TRREM, trremVal & CSL_EPWM_TRREM_TRREM_MASK);
9629 HW_WR_REG32(base + CSL_EPWM_CMPA, compCount << 8);
9636 HW_WR_REG32(base + CSL_EPWM_CMPB, compCount << 8);
9657 static inline uint32_t
9671 compCount = HW_RD_REG32(base + CSL_EPWM_CMPA);
9678 compCount = HW_RD_REG32(base + CSL_EPWM_CMPB);
9681 return(compCount>>8U);
9706 uint16_t hrCompCount)
9721 HW_WR_REG32(base + CSL_EPWM_CMPA,
9722 HW_RD_REG32(base + CSL_EPWM_CMPA) | ((hrCompCount & CSL_EPWM_CMPA_CMPAHR_MASK) << 8U));
9729 HW_WR_REG32(base + CSL_EPWM_CMPB,
9730 HW_RD_REG32(base + CSL_EPWM_CMPB) | ((hrCompCount & CSL_EPWM_CMPB_CMPBHR_MASK) << 8U));
9750 static inline uint16_t
9754 uint16_t hrCompCount;
9764 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPA) & CSL_EPWM_CMPA_CMPAHR_MASK);
9771 hrCompCount = (HW_RD_REG16(base + CSL_EPWM_CMPB) & CSL_EPWM_CMPB_CMPBHR_MASK);
9774 return(hrCompCount >> 8U);
9804 HW_WR_REG16(base + CSL_EPWM_DBREDHR,
9805 (HW_RD_REG16(base + CSL_EPWM_DBREDHR) & ~CSL_EPWM_DBREDHR_DBREDHR_MASK ) |
9806 (hrRedCount << CSL_EPWM_DBREDHR_DBREDHR_SHIFT));
9835 HW_WR_REG16(base + CSL_EPWM_DBFEDHR,
9836 (HW_RD_REG16(base + CSL_EPWM_DBFEDHR) &
9837 ~CSL_EPWM_DBFEDHR_DBFEDHR_MASK) |
9838 (hrFedCount << CSL_EPWM_DBFEDHR_DBFEDHR_SHIFT));
9866 HW_WR_REG16(base + CSL_OTTOCAL_HRMSTEP,
9867 ((HW_RD_REG16(base + CSL_OTTOCAL_HRMSTEP) & ~CSL_OTTOCAL_HRMSTEP_HRMSTEP_MASK) |
9868 mepCount << CSL_OTTOCAL_HRMSTEP_HRMSTEP_SHIFT));
9899 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9900 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_EDGMODEDB_MASK) |
9901 ((uint16_t)mepDBEdge << CSL_EPWM_HRCNFG2_EDGMODEDB_SHIFT)));
9929 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9930 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBRED_MASK) |
9931 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBRED_SHIFT)));
9958 HW_WR_REG16(base + CSL_EPWM_HRCNFG2,
9959 ((HW_RD_REG16(base + CSL_EPWM_HRCNFG2) & ~CSL_EPWM_HRCNFG2_CTLMODEDBFED_MASK) |
9960 ((uint16_t)loadEvent << CSL_EPWM_HRCNFG2_CTLMODEDBFED_SHIFT)));
9984 uint32_t registerOffset;
9989 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
9994 HW_WR_REG16(registerOffset, xcmpvalue);
10014 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10016 HW_WR_REG32(registerOffset,
10017 (HW_RD_REG32(registerOffset) | CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
10034 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10036 HW_WR_REG32(registerOffset,
10037 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPEN_MAX ));
10056 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10057 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
10059 HW_WR_REG32(registerOffset,
10060 (HW_RD_REG32(registerOffset) | ( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
10078 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10079 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPSPLIT_SHIFT;
10081 HW_WR_REG32(registerOffset,
10082 (HW_RD_REG32(registerOffset) & ~( CSL_EPWM_XCMPCTL1_XCMPSPLIT_MAX << offset )));
10111 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10112 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_SHIFT;
10114 HW_WR_REG32(registerOffset,
10115 ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPA_ALLOC_MASK) | ( alloctype << offset )));
10138 uint32_t registerOffset = base + CSL_EPWM_XCMPCTL1;
10139 uint32_t offset = CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_SHIFT;
10141 HW_WR_REG32(registerOffset,
10142 ( (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XCMPCTL1_XCMPB_ALLOC_MASK) | ( alloctype << offset )));
10165 uint16_t xcmpvalue)
10167 uint32_t registerOffset;
10172 registerOffset = base + CSL_EPWM_XCMP1_ACTIVE + (uint16_t)xcmpReg;
10177 HW_WR_REG16(registerOffset + 0x2U, xcmpvalue);
10204 uint32_t registerOffset;
10205 registerOffset = base + CSL_EPWM_CMPC_SHDW1 + (uint32_t)cmpReg;
10210 HW_WR_REG16(registerOffset, cmpvalue);
10235 uint16_t xcmpvalue)
10240 uint32_t registerOffset;
10241 registerOffset = base + CSL_EPWM_XMINMAX_ACTIVE + (uint16_t)xminmaxReg;
10246 HW_WR_REG16(registerOffset, xcmpvalue);
10293 uint32_t registerOffset;
10301 registerOffset = CSL_EPWM_XAQCTLA_ACTIVE + (uint16_t)(epwmOutput/2);
10303 HW_WR_REG16(base + registerOffset,
10304 ((HW_RD_REG16(base + registerOffset) &
10305 ~(CSL_EPWM_XAQCTLA_ACTIVE_XCMP1_MAX << (uint16_t)event)) |
10306 ((uint16_t)output << (uint16_t)event)));
10310 registerOffset = CSL_EPWM_XAQCTLA_SHDW1 + (uint16_t)(epwmOutput/2);
10312 HW_WR_REG16(base + registerOffset,
10313 ((HW_RD_REG16(base + registerOffset) &
10314 ~(CSL_EPWM_XAQCTLA_SHDW1_XCMP1_MAX << (uint16_t)event)) |
10315 ((uint16_t)output << (uint16_t)event)));
10319 registerOffset = CSL_EPWM_XAQCTLA_SHDW2 + (uint16_t)(epwmOutput/2);
10321 HW_WR_REG16(base + registerOffset,
10322 ((HW_RD_REG16(base + registerOffset) &
10323 ~(CSL_EPWM_XAQCTLA_SHDW2_XCMP1_MAX << (uint16_t)event)) |
10324 ((uint16_t)output << (uint16_t)event)));
10328 registerOffset = CSL_EPWM_XAQCTLA_SHDW3 + (uint16_t)(epwmOutput/2);
10330 HW_WR_REG16(base + registerOffset,
10331 ((HW_RD_REG16(base + registerOffset) &
10332 ~(CSL_EPWM_XAQCTLA_SHDW3_XCMP1_MAX << (uint16_t)event)) |
10333 ((uint16_t)output << (uint16_t)event)));
10353 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
10355 HW_WR_REG32(registerOffset,
10356 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_STARTLD_MASK ));
10373 uint32_t registerOffset = base + CSL_EPWM_XLOAD;
10375 HW_WR_REG32(registerOffset,
10376 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOAD_STARTLD_MASK ));
10396 uint32_t registerOffset;
10397 registerOffset = base + CSL_EPWM_XLOAD;
10399 HW_WR_REG32(registerOffset,
10400 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOAD_FRCLD_MASK ));
10420 uint32_t registerOffset;
10425 registerOffset = base + CSL_EPWM_XLOADCTL;
10429 HW_WR_REG32(registerOffset,
10430 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_LOADMODE_MASK));
10434 HW_WR_REG32(registerOffset,
10435 (HW_RD_REG32(registerOffset) | CSL_EPWM_XLOADCTL_LOADMODE_MASK));
10458 uint32_t registerOffset;
10463 registerOffset = base + CSL_EPWM_XLOADCTL;
10465 HW_WR_REG32(registerOffset,
10466 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWLEVEL_MASK) |
10467 ((uint16_t)level << CSL_EPWM_XLOADCTL_SHDWLEVEL_SHIFT)));
10489 uint32_t registerOffset;
10494 registerOffset = base + CSL_EPWM_XLOADCTL;
10496 HW_WR_REG32(registerOffset,
10497 ((HW_RD_REG32(registerOffset) & ~CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_MASK) |
10498 ((uint16_t)ptr << CSL_EPWM_XLOADCTL_SHDWBUFPTR_LOADONCE_SHIFT)));
10522 uint32_t registerOffset;
10526 registerOffset = base + CSL_EPWM_XLOADCTL;
10530 HW_WR_REG32(registerOffset,
10531 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF2PRD_MASK))
10532 | (count<<CSL_EPWM_XLOADCTL_RPTBUF2PRD_SHIFT)) );
10536 HW_WR_REG32(registerOffset,
10537 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_XLOADCTL_RPTBUF3PRD_MASK))
10538 | (count<<CSL_EPWM_XLOADCTL_RPTBUF3PRD_SHIFT)) );
10562 uint32_t registerOffset;
10566 registerOffset = base + CSL_EPWM_DECTL;
10568 HW_WR_REG32(registerOffset,
10569 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_ENABLE_MAX ));
10588 uint32_t registerOffset;
10592 registerOffset = base + CSL_EPWM_DECTL;
10594 HW_WR_REG32(registerOffset,
10595 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_ENABLE_MAX ));
10620 uint32_t registerOffset;
10625 registerOffset = base + CSL_EPWM_DECTL;
10629 HW_WR_REG32(registerOffset,
10630 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DECTL_MODE_MASK));
10634 HW_WR_REG32(registerOffset,
10635 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECTL_MODE_MASK));
10656 uint32_t registerOffset;
10660 registerOffset = base + CSL_EPWM_DECTL;
10662 HW_WR_REG32(registerOffset,
10663 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DECTL_REENTRYDLY_MASK))
10664 | (delay<<CSL_EPWM_DECTL_REENTRYDLY_SHIFT)) );
10690 uint32_t registerOffset;
10694 registerOffset = base + CSL_EPWM_DECOMPSEL;
10698 HW_WR_REG32(registerOffset,
10699 ((HW_RD_REG32(registerOffset) &
10700 ~CSL_EPWM_DECOMPSEL_TRIPL_MASK) |
10701 (source<<CSL_EPWM_DECOMPSEL_TRIPL_SHIFT)));
10705 HW_WR_REG32(registerOffset,
10706 ((HW_RD_REG32(registerOffset) &
10707 ~CSL_EPWM_DECOMPSEL_TRIPH_MASK) |
10708 (source<<CSL_EPWM_DECOMPSEL_TRIPH_SHIFT)));
10737 uint32_t registerOffset;
10741 registerOffset = base + CSL_EPWM_DEACTCTL;
10745 HW_WR_REG32(registerOffset,
10746 ((HW_RD_REG32(registerOffset) &
10747 ~CSL_EPWM_DEACTCTL_PWMA_MASK) |
10748 (signal<<CSL_EPWM_DEACTCTL_PWMA_SHIFT)));
10752 HW_WR_REG32(registerOffset,
10753 ((HW_RD_REG32(registerOffset) &
10754 ~CSL_EPWM_DEACTCTL_PWMB_MASK) |
10755 (signal<<CSL_EPWM_DEACTCTL_PWMB_SHIFT)));
10781 uint32_t registerOffset;
10785 registerOffset = base + CSL_EPWM_DEACTCTL;
10789 HW_WR_REG32(registerOffset,
10790 ((HW_RD_REG32(registerOffset) &
10791 ~CSL_EPWM_DEACTCTL_TRIPSELA_MASK) |
10792 (signal<<CSL_EPWM_DEACTCTL_TRIPSELA_SHIFT)));
10796 HW_WR_REG32(registerOffset,
10797 ((HW_RD_REG32(registerOffset) &
10798 ~CSL_EPWM_DEACTCTL_TRIPSELB_MASK) |
10799 (signal<<CSL_EPWM_DEACTCTL_TRIPSELB_SHIFT)));
10815 uint32_t registerOffset;
10819 registerOffset = base + CSL_EPWM_DEACTCTL;
10821 HW_WR_REG32(registerOffset,
10822 (HW_RD_REG32(registerOffset) &
10823 ~(CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10839 uint32_t registerOffset;
10843 registerOffset = base + CSL_EPWM_DEACTCTL;
10845 HW_WR_REG32(registerOffset,
10846 (HW_RD_REG32(registerOffset) |
10847 (CSL_EPWM_DEACTCTL_TRIPENABLE_MAX << CSL_EPWM_DEACTCTL_TRIPENABLE_SHIFT)));
10863 uint32_t registerOffset;
10867 registerOffset = base + CSL_EPWM_DEFRC;
10869 HW_WR_REG32(registerOffset,
10870 (HW_RD_REG32(registerOffset) | CSL_EPWM_DEFRC_DEACTIVE_MASK));
10886 uint32_t registerOffset;
10890 registerOffset = base + CSL_EPWM_DECLR;
10892 HW_WR_REG32(registerOffset,
10893 (HW_RD_REG32(registerOffset) | CSL_EPWM_DECLR_DEACTIVE_MASK));
10909 uint32_t registerOffset;
10913 registerOffset = base + CSL_EPWM_DEMONCTL;
10915 HW_WR_REG32(registerOffset,
10916 (HW_RD_REG32(registerOffset) |
10917 (CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
10932 uint32_t registerOffset;
10936 registerOffset = base + CSL_EPWM_DEMONCTL;
10938 HW_WR_REG32(registerOffset,
10939 (HW_RD_REG32(registerOffset) &
10940 ~(CSL_EPWM_DEMONCTL_ENABLE_MAX << CSL_EPWM_DEMONCTL_ENABLE_SHIFT)));
10962 uint32_t registerOffset;
10966 registerOffset = base + CSL_EPWM_DEMONSTEP;
10970 HW_WR_REG32(registerOffset,
10971 (HW_RD_REG32(registerOffset) & ~CSL_EPWM_DEMONSTEP_INCSTEP_MASK)
10972 | (stepsize<<CSL_EPWM_DEMONSTEP_INCSTEP_SHIFT));
10976 HW_WR_REG32(registerOffset,
10977 ((HW_RD_REG32(registerOffset) &
10978 ~CSL_EPWM_DEMONSTEP_DECSTEP_MASK) |
10979 (stepsize<<CSL_EPWM_DEMONSTEP_DECSTEP_SHIFT)));
10996 uint32_t registerOffset;
11000 registerOffset = base + CSL_EPWM_DEMONTHRES;
11002 HW_WR_REG32(registerOffset,
11003 ((HW_RD_REG32(registerOffset) & ~(CSL_EPWM_DEMONTHRES_THRESHOLD_MASK))
11004 | (threshold<<CSL_EPWM_DEMONTHRES_THRESHOLD_SHIFT)) );
11059 #endif // EPWM_V1_H_
@ EPWM_TZ_ACTION_HIGH
high voltage state
Definition: etpwm.h:955
@ HRPWM_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:1892
static void EPWM_disableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6018
static void EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, bool enableSwapMode)
Definition: etpwm.h:4388
@ HRPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2038
static void EPWM_enableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6490
@ EPWM_AQ_OUTPUT_HIGH_UP_T1
T1 event on count up and set output pins to high.
Definition: etpwm.h:675
static uint16_t EPWM_getValleyHWDelay(uint32_t base)
Definition: etpwm.h:8359
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base)
Definition: etpwm.h:7024
EPWM_TimeBaseCountMode
Definition: etpwm.h:346
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT22
Trip source is INPUTXBAR out22 signal.
Definition: etpwm.h:2388
@ HRPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2009
@ EPWM_TZ_ACTION_LOW
low voltage state
Definition: etpwm.h:956
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM8
Sync-in source is EPWM8 sync-out signal.
Definition: etpwm.h:204
static uint16_t EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5493
EPWM_ActionQualifierLoadMode
Definition: etpwm.h:508
@ EPWM_LINK_WITH_EPWM_5
link current ePWM with ePWM5
Definition: etpwm.h:393
@ HRPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:1987
static void EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_FallingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4721
static void EPWM_selectPeriodLoadEvent(uint32_t base, EPWM_PeriodShadowLoadMode shadowLoadMode)
Definition: etpwm.h:3010
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD
Clear CBC pulse when counter equals zero or period.
Definition: etpwm.h:1128
static void EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, EPWM_LinkComponent linkComp)
Definition: etpwm.h:3354
EPWM_XCMP_XLOADCTL_SHDWLEVEL
Definition: etpwm.h:2289
static void HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, HRPWM_MEPEdgeMode mepEdgeMode)
Definition: etpwm.h:9241
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG2
Sync-in source is FSI-RX2 RX Trigger 2 signal.
Definition: etpwm.h:300
@ EPWM_SOC_A
SOC A.
Definition: etpwm.h:1257
@ EPWM_DC_EVENT_1
Digital Compare Event number 1.
Definition: etpwm.h:1467
@ EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:514
@ EPWM_AQ_SW_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:600
@ EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD
Time base counter equals zero or period.
Definition: etpwm.h:1394
@ EPWM_DE_TRIP_SRC_CMPSSB1
Trip source is CMPSSB1 signal.
Definition: etpwm.h:2430
@ EPWM_HSCLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:168
@ EPWM_LINK_WITH_EPWM_9
link current ePWM with ePWM9
Definition: etpwm.h:397
static void HRPWM_setMEPStep(uint32_t base, uint16_t mepCount)
Definition: etpwm.h:9856
@ HRPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2006
static void EPWM_startValleyCapture(uint32_t base)
Definition: etpwm.h:8121
static void EPWM_setXCMPShadowRepeatBufxCount(uint32_t base, uint32_t bufferset, uint8_t count)
Definition: etpwm.h:10520
static void EPWM_disableOneShotSync(uint32_t base)
Definition: etpwm.h:3055
@ EPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2128
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_U
load when counter is equal to cmpc and cmpc is incrementing
Definition: etpwm.h:1552
static void EPWM_enableValleyHWDelay(uint32_t base)
Definition: etpwm.h:8208
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT18
Trip source is INPUTXBAR out18 signal.
Definition: etpwm.h:2380
static void EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, EPWM_CycleByCycleTripZoneClearMode clearEvent)
Definition: etpwm.h:5552
static void EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv)
Definition: etpwm.h:4934
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT1
Sync-in source is C2K Timesync xbar sync pwm out1 signal.
Definition: etpwm.h:278
static void EPWM_enableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5731
@ EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO
shadow to active load occurs when time base counter reaches 0.
Definition: etpwm.h:362
@ EPWM_DE_TRIP_SRC_CMPSSB0
Trip source is CMPSSB0 signal.
Definition: etpwm.h:2428
@ EPWM_REGISTER_GROUP_TRIP_ZONE
Trip zone register group.
Definition: etpwm.h:1709
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM24
Sync-in source is EPWM24 sync-out signal.
Definition: etpwm.h:236
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U
Digital Compare event A/B 1 while counting up.
Definition: etpwm.h:1004
static void EPWM_forceDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10861
@ EPWM_COMP_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:469
EPWM_ActionQualifierContForce
Definition: etpwm.h:726
@ EPWM_DE_SYNC_INV_TRIPHorL
synchronized and inverted version of TRIPH or TRIPL signal
Definition: etpwm.h:2455
static uint16_t EPWM_getTimeBaseCounterValue(uint32_t base)
Definition: etpwm.h:3098
static uint16_t EPWM_getADCTriggerEventCount(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6623
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT16
Trip source is INPUTXBAR out16 signal.
Definition: etpwm.h:2376
@ EPWM_DE_HIGH
a constant high signal
Definition: etpwm.h:2459
static void EPWM_enableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:5131
static void EPWM_setCounterCompareValue_opt_cmpA(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3585
@ HRPWM_PWMSYNC_SOURCE_ZERO
Counter equals zero.
Definition: etpwm.h:1922
@ HRPWM_PWMSYNC_SOURCE_COMPD_UP
Counter equals COMPD when counting up.
Definition: etpwm.h:1928
static void HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount)
Definition: etpwm.h:9825
static void EPWM_setActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierEventAction action)
Definition: etpwm.h:4061
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_ZERO_PERIOD
Clear CBC latch when counter equals zero or period.
Definition: etpwm.h:1526
@ EPWM_CLOCK_DIVIDER_32
Divide clock by 32.
Definition: etpwm.h:154
static void EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount)
Definition: etpwm.h:4829
@ EPWM_XCMP_4_CMPA
Allocate XCMP1 - XCMP4 registers to CMPA.
Definition: etpwm.h:2238
#define EPWM_XCMP_SHADOW1
XCMP set = Shadow 2.
Definition: etpwm.h:2054
@ EPWM_XMIN_SHADOW1
XMIN_SHADOW1.
Definition: etpwm.h:2184
static void EPWM_setCounterCompareValue_opt_cmpD(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3642
@ EPWM_COMP_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:475
@ EPWM_SYNC_IN_PULSE_SRC_C2K_TIMESYNC_XBAR_PWM_OUT0
Sync-in source is C2K Timesync xbar sync pwm out0 signal.
Definition: etpwm.h:276
@ EPWM_DE_TRIP_SRC_CMPSSB2
Trip source is CMPSSB2 signal.
Definition: etpwm.h:2432
@ EPWM_DC_EDGEFILT_EDGECNT_6
Digital Compare Edge filter edge count = 7.
Definition: etpwm.h:1694
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT12
Trip source is INPUTXBAR out12 signal.
Definition: etpwm.h:2368
Float32 dutyValA
Desired ePWMxA Signal Duty.
Definition: etpwm.h:2581
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO
load on sync or when counter equals zero
Definition: etpwm.h:518
HRPWM_XCMPReg
Definition: etpwm.h:1969
static void EPWM_forceActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput)
Definition: etpwm.h:4342
@ EPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:2071
@ EPWM_DC_CBC_LATCH_CLR_CNTR_ZERO
Clear CBC latch when counter equals zero.
Definition: etpwm.h:1522
@ EPWM_LINK_WITH_EPWM_22
link current ePWM with ePWM22
Definition: etpwm.h:410
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1
T1 event on count down and no change in the output pins.
Definition: etpwm.h:679
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
@ HRPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2000
@ EPWM_LINK_WITH_EPWM_16
link current ePWM with ePWM16
Definition: etpwm.h:404
EPWM_DigitalCompareEdgeFilterEdgeCount
Definition: etpwm.h:1680
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA
Time base counter down equals COMPA and set output pins to high.
Definition: etpwm.h:640
static void EPWM_selectDigitalCompareTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:6702
EPWM_TripZoneDigitalCompareOutput
Definition: etpwm.h:907
EPWM_TripZoneAdvancedEvent
Definition: etpwm.h:967
@ EPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2134
@ EPWM_FED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:833
static void EPWM_clearADCTriggerFlag(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6459
@ EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:473
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP9
Sync-in source is ECAP9 sync-out signal.
Definition: etpwm.h:270
@ EPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:2088
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP0
Sync-in source is ECAP0 sync-out signal.
Definition: etpwm.h:252
#define EPWM_XCMP_ACTIVE
< XCMP set = Active
Definition: etpwm.h:2052
static void HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, HRPWM_MEPCtrlMode mepCtrlMode)
Definition: etpwm.h:9278
static void EPWM_setDigitalCompareEventSyncMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareSyncMode syncMode)
Definition: etpwm.h:7204
@ EPWM_DB_POLARITY_ACTIVE_HIGH
DB polarity is not inverted.
Definition: etpwm.h:769
static void EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, EPWM_ActionQualifierContForce mode)
Definition: etpwm.h:4180
@ EPWM_DB_RED
DB RED (Rising Edge Delay) mode.
Definition: etpwm.h:757
EPWM_XCompareReg
Definition: etpwm.h:2153
@ EPWM_LINK_WITH_EPWM_24
link current ePWM with ePWM24
Definition: etpwm.h:412
EPWM_ActionQualifierTriggerSource
Definition: etpwm.h:534
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP1
Time base counter equals XCMP1.
Definition: etpwm.h:2204
@ HRPWM_MEP_PHASE_CTRL
TBPHSHR controls MEP edge.
Definition: etpwm.h:1875
#define EPWM_SYNC_OUT_SOURCE_M
Definition: etpwm.h:79
@ EPWM_COUNTER_COMPARE_D
counter compare D
Definition: etpwm.h:457
@ EPWM_CMPD_SHADOW1
CMPD_SHADOW1.
Definition: etpwm.h:2157
@ EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW
Event when DCxL high DCxH low.
Definition: etpwm.h:927
EPWM_XMinMaxReg
Definition: etpwm.h:2176
@ EPWM_LINK_TBPRD
link TBPRD:TBPRDHR registers
Definition: etpwm.h:430
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT29
Trip source is INPUTXBAR out29 signal.
Definition: etpwm.h:2402
#define EPWM_INT_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1212
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_U
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up.
Definition: etpwm.h:975
@ EPWM_SOC_TBCTR_PERIOD
Time-base counter equal to period.
Definition: etpwm.h:1274
static uint16_t EPWM_getGlobalLoadEventCount(uint32_t base)
Definition: etpwm.h:8499
@ HRPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:1998
static void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5347
@ HRPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2032
@ EPWM_AQ_OUTPUT_TOGGLE_ZERO
Time base counter equals zero and toggle the output pins.
Definition: etpwm.h:618
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM18
Sync-in source is EPWM18 sync-out signal.
Definition: etpwm.h:224
static void HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, HRPWM_MEPDeadBandEdgeMode mepDBEdge)
Definition: etpwm.h:9893
@ EPWM_DE_TRIP_SRC_CMPSSB4
Trip source is CMPSSB4 signal.
Definition: etpwm.h:2436
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DC_EVTFILT
Digital compare filter event.
Definition: etpwm.h:543
@ HRPWM_DB_MEP_CTRL_RED
MEP controls Rising Edge Delay.
Definition: etpwm.h:1956
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM0
Sync-in source is EPWM0 sync-out signal.
Definition: etpwm.h:188
@ EPWM_SOC_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1284
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT14
Trip source is INPUTXBAR out14 signal.
Definition: etpwm.h:2372
static void EPWM_setOneShotSyncOutTrigger(uint32_t base, EPWM_OneShotSyncOutTrigger trigger)
Definition: etpwm.h:2869
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA
Time base counter down equals COMPA.
Definition: etpwm.h:561
EPWM_ActionQualifierEventAction
Definition: etpwm.h:610
static void EPWM_disableXCMPMode(uint32_t base)
Definition: etpwm.h:10032
static void EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount)
Definition: etpwm.h:7049
@ EPWM_XCMP_6_CMPA
Allocate XCMP1 - XCMP6 registers to CMPA.
Definition: etpwm.h:2242
@ EPWM_CMPD_SHADOW3
CMPD_SHADOW3.
Definition: etpwm.h:2165
EPWM_ClockDivider tbClkDiv
Time Base Counter Clock Divider.
Definition: etpwm.h:2586
@ EPWM_AQ_OUTPUT_NO_CHANGE
No change in the output pins.
Definition: etpwm.h:584
@ EPWM_DE_TRIP_SRC_CMPSSA0
Trip source is CMPSSA0 signal.
Definition: etpwm.h:2408
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1
Digital compare event B 1.
Definition: etpwm.h:537
static void HRPWM_setHiResRisingEdgeDelay(uint32_t base, uint16_t hrRedCount)
Definition: etpwm.h:9794
@ EPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2142
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG1
Sync-in source is FSI-RX1 RX Trigger 1 signal.
Definition: etpwm.h:290
@ HRPWM_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:1888
static void EPWM_setMinDeadBandDelay(uint32_t base, uint32_t block, uint32_t delay)
Definition: etpwm.h:8948
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM27
Sync-in source is EPWM27 sync-out signal.
Definition: etpwm.h:242
@ EPWM_XCMP3_SHADOW3
XCMP3_SHADOW3.
Definition: etpwm.h:2130
@ EPWM_LINK_WITH_EPWM_12
link current ePWM with ePWM12
Definition: etpwm.h:400
static void HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB)
Definition: etpwm.h:9376
static void EPWM_enableInterrupt(uint32_t base)
Definition: etpwm.h:5782
static void EPWM_setCMPShadowRegValue(uint32_t base, EPWM_XCompareReg cmpReg, uint16_t cmpvalue)
Definition: etpwm.h:10198
static void EPWM_disableTripZoneAdvAction(uint32_t base)
Definition: etpwm.h:5152
static void EPWM_clearDiodeEmulationActive(uint32_t base)
Definition: etpwm.h:10884
#define EPWM_DB_INPUT_EPWMA
Input signal is ePWMA.
Definition: etpwm.h:780
@ HRPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:1979
static void EPWM_setDeadBandCounterClock(uint32_t base, EPWM_DeadBandClockMode clockMode)
Definition: etpwm.h:4776
@ EPWM_OSHT_SYNC_OUT_TRIG_RELOAD
Trigger is OSHT reload.
Definition: etpwm.h:322
@ EPWM_AQ_OUTPUT_HIGH_ZERO
Time base counter equals zero and set output pins to high.
Definition: etpwm.h:616
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD
load on sync event or when counter is equal to period
Definition: etpwm.h:1548
HRPWM_ChannelBOutput
Definition: etpwm.h:1904
@ EPWM_LINK_WITH_EPWM_2
link current ePWM with ePWM2
Definition: etpwm.h:390
static void EPWM_enableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:8982
static void HRPWM_disablePeriodControl(uint32_t base)
Definition: etpwm.h:9463
@ EPWM_DB_OUTPUT_A
DB output is ePWMA.
Definition: etpwm.h:745
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD
Clear CBC pulse when counter equals period.
Definition: etpwm.h:1126
EPWM_TripZoneDigitalCompareOutputEvent
Definition: etpwm.h:921
@ EPWM_SHADOW_LOAD_MODE_SYNC
shadow to active load occurs only when a SYNC occurs
Definition: etpwm.h:367
static void EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode)
Definition: etpwm.h:2979
EPWM_PeriodLoadMode
Definition: etpwm.h:332
Float32 sysClkInHz
SYSCLK Frequency(in Hz)
Definition: etpwm.h:2584
EPWM_CurrentLink
Definition: etpwm.h:387
static void EPWM_setDeadBandDelayPolarity(uint32_t base, EPWM_DeadBandDelayMode delayMode, EPWM_DeadBandPolarity polarity)
Definition: etpwm.h:4483
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM15
Sync-in source is EPWM15 sync-out signal.
Definition: etpwm.h:218
@ EPWM_HSCLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:167
static void EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth)
Definition: etpwm.h:4966
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM4
Sync-in source is EPWM4 sync-out signal.
Definition: etpwm.h:196
@ EPWM_HSCLOCK_DIVIDER_14
Divide clock by 14.
Definition: etpwm.h:174
@ EPWM_AQ_OUTPUT_LOW_DOWN_T2
T2 event on count down and set output pins to low.
Definition: etpwm.h:697
#define EPWM_DCxxTRIPSEL
Definition: etpwm.h:2565
HRPWM_MEPCtrlMode
Definition: etpwm.h:1871
EPWM_DiodeEmulationSignal
Definition: etpwm.h:2450
@ EPWM_REGISTER_GROUP_DIGITAL_COMPARE
Digital compare group.
Definition: etpwm.h:1711
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG0
Sync-in source is FSI-RX3 RX Trigger 0 signal.
Definition: etpwm.h:304
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP8
Time base counter equals XCMP8.
Definition: etpwm.h:2218
@ EPWM_XCMP_7_CMPA
Allocate XCMP1 - XCMP7 registers to CMPA.
Definition: etpwm.h:2244
static void EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4747
static void EPWM_clearEventTriggerInterruptFlag(uint32_t base)
Definition: etpwm.h:5972
EPWM_DigitalCompareTripInput
Definition: etpwm.h:1322
@ HRPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:1977
@ EPWM_AQ_SW_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:599
static void EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7670
EPWM_SyncInPulseSource
Definition: etpwm.h:184
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2
T2 event on count down and toggle the output pins.
Definition: etpwm.h:701
static void EPWM_selectMinimumDeadBandReferenceSignal(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8883
EPWM_DeadBandControlLoadMode
Definition: etpwm.h:793
EPWM_ActionQualifierSWOutput
Definition: etpwm.h:597
static void EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode)
Definition: etpwm.h:8274
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_UP
T1 event on count up.
Definition: etpwm.h:567
static void EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags)
Definition: etpwm.h:5589
static void HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9953
EPWM_ADCStartOfConversionType
Definition: etpwm.h:1256
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT28
Trip source is INPUTXBAR out28 signal.
Definition: etpwm.h:2400
@ EPWM_XCMP_2_CMPA
Allocate XCMP1 - XCMP2 registers to CMPA.
Definition: etpwm.h:2234
static void EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger)
Definition: etpwm.h:8147
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY
Definition: etpwm.h:1645
static void EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode)
Definition: etpwm.h:2631
static void EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, EPWM_TripZoneAdvancedAction tzAdvAction)
Definition: etpwm.h:5245
@ EPWM_GL_LOAD_PULSE_SYNC
load on sync event
Definition: etpwm.h:1544
static void EPWM_disableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6795
@ EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO
load on sync event or when counter is equal to zero
Definition: etpwm.h:1546
static void EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount)
Definition: etpwm.h:4903
#define EPWM_INT_TBCTR_ETINTMIX
Time-base counter based on mix events.
Definition: etpwm.h:1196
@ EPWM_XCMP5_SHADOW1
XCMP5_SHADOW1.
Definition: etpwm.h:2096
@ EPWM_LINK_WITH_EPWM_18
link current ePWM with ePWM18
Definition: etpwm.h:406
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA
Time base counter down equals COMPA and no change in the output pins.
Definition: etpwm.h:636
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT25
Trip source is INPUTXBAR out25 signal.
Definition: etpwm.h:2394
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_0
Only Active register is available.
Definition: etpwm.h:2291
static void EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:5919
static void EPWM_nobypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10813
@ EPWM_CLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:152
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT3
Trip source is INPUTXBAR out3 signal.
Definition: etpwm.h:2350
@ EPWM_TZ_ADV_ACTION_EVENT_TZA_D
TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down.
Definition: etpwm.h:973
static bool EPWM_getSyncStatus(uint32_t base)
Definition: etpwm.h:3164
@ HRPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2021
@ HRPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2004
@ EPWM_TZ_ADV_ACTION_LOW
low voltage state
Definition: etpwm.h:989
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:479
@ EPWM_COUNTER_MODE_UP
Up - count mode.
Definition: etpwm.h:347
@ EPWM_SOC_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1288
static void EPWM_setADCTriggerSource(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, EPWM_ADCStartOfConversionSource socSource, uint16_t mixedSource)
Definition: etpwm.h:6230
static void EPWM_disableSplitXCMP(uint32_t base)
Definition: etpwm.h:10076
static void EPWM_enableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8721
@ EPWM_HSCLOCK_DIVIDER_6
Divide clock by 6.
Definition: etpwm.h:170
@ EPWM_XCMP_1_CMPA
Allocate XCMP1 register to CMPA.
Definition: etpwm.h:2232
static uint16_t EPWM_getTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5461
@ EPWM_REGISTER_GROUP_GLOBAL_LOAD
Global load register group.
Definition: etpwm.h:1708
@ EPWM_GL_LOAD_PULSE_CNTR_PERIOD
load when counter is equal to period
Definition: etpwm.h:1540
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP2
Time base counter equals XCMP2.
Definition: etpwm.h:2206
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2
T2 event on count up and no change in the output pins.
Definition: etpwm.h:687
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG0
Sync-in source is FSI-RX0 RX Trigger 0 signal.
Definition: etpwm.h:280
static uint16_t EPWM_getTimeBasePeriod(uint32_t base)
Definition: etpwm.h:3281
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG2
Sync-in source is FSI-RX0 RX Trigger 2 signal.
Definition: etpwm.h:284
static void EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue)
Definition: etpwm.h:8253
@ EPWM_DC_MODULE_A
Digital Compare Module A.
Definition: etpwm.h:1452
@ EPWM_AQ_OUTPUT_A
ePWMxA output
Definition: etpwm.h:715
EPWM_GlobalLoadTrigger
Definition: etpwm.h:1536
@ EPWM_HSCLOCK_DIVIDER_10
Divide clock by 10.
Definition: etpwm.h:172
@ EPWM_LINK_WITH_EPWM_0
link current ePWM with ePWM0
Definition: etpwm.h:388
@ EPWM_COUNT_MODE_DOWN_AFTER_SYNC
Count down after sync event.
Definition: etpwm.h:137
@ EPWM_DC_WINDOW_START_TBCTR_ZERO
Time base counter equals zero.
Definition: etpwm.h:1392
@ EPWM_AQ_OUTPUT_TOGGLE
Toggle the output pins.
Definition: etpwm.h:587
EPWM_DigitalCompareCBCLatchClearEvent
Definition: etpwm.h:1520
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1
Digital compare event A 1.
Definition: etpwm.h:535
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_TWO
Shadow buffer 2 is in use.
Definition: etpwm.h:2314
static void EPWM_disableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:10930
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T1
T1 event on count down and set output pins to high.
Definition: etpwm.h:683
@ EPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:2092
static bool EPWM_getDigitalCompareCaptureStatus(uint32_t base)
Definition: etpwm.h:7617
@ EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE
Valley capture trigged by software.
Definition: etpwm.h:1601
static void EPWM_setGlobalLoadOneShotLatch(uint32_t base)
Definition: etpwm.h:8569
@ EPWM_AQ_SW_DISABLED
Software forcing disabled.
Definition: etpwm.h:598
@ HRPWM_XCMP3_SHADOW1
XCMP3_SHADOW1.
Definition: etpwm.h:1994
EPWM_ADCStartOfConversionSource
Definition: etpwm.h:1268
@ HRPWM_XCMP5_SHADOW3
XCMP5_SHADOW3.
Definition: etpwm.h:2036
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT23
Trip source is INPUTXBAR out23 signal.
Definition: etpwm.h:2390
static void EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, uint16_t tripInput, EPWM_DigitalCompareType dcType)
Definition: etpwm.h:7719
@ HRPWM_PWMSYNC_SOURCE_COMPD_DOWN
Counter equals COMPD when counting down.
Definition: etpwm.h:1930
EPWM_EmulationMode
Definition: etpwm.h:120
@ EPWM_XMIN_SHADOW3
XMIN_SHADOW3.
Definition: etpwm.h:2192
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2
Trip zone 2.
Definition: etpwm.h:540
@ EPWM_DC_WINDOW_SOURCE_DCBEVT2
DC filter signal source is DCBEVT2.
Definition: etpwm.h:1437
#define EPWM_INT_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1200
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM25
Sync-in source is EPWM25 sync-out signal.
Definition: etpwm.h:238
@ EPWM_DC_EDGEFILT_EDGECNT_2
Digital Compare Edge filter edge count = 3.
Definition: etpwm.h:1686
#define EPWM_INT_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1210
EPWM_XCMP_ALLOC_CMPA
Values that can be passed to EPWM_allocAXCMP() as the alloctype parameter.
Definition: etpwm.h:2228
@ EPWM_XMIN_ACTIVE
XMIN_ACTIVE.
Definition: etpwm.h:2180
@ EPWM_LINK_WITH_EPWM_20
link current ePWM with ePWM20
Definition: etpwm.h:408
@ EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:817
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2
Digital compare event A 2.
Definition: etpwm.h:536
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP6
Time base counter equals XCMP6.
Definition: etpwm.h:2214
@ HRPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2013
static void HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource)
Definition: etpwm.h:9539
static void HRPWM_setHiResTimeBasePeriod(uint32_t base, uint16_t hrPeriodCount)
Definition: etpwm.h:9181
@ EPWM_LINK_WITH_EPWM_30
link current ePWM with ePWM30
Definition: etpwm.h:418
static void EPWM_enableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7249
@ EPWM_DC_TYPE_DCAL
Digital Compare A Low.
Definition: etpwm.h:1309
EPWM_CounterCompareModule
Definition: etpwm.h:453
EPWM_HSClockDivider tbHSClkDiv
Time Base Counter HS Clock Divider.
Definition: etpwm.h:2587
@ EPWM_XTBPRD_SHADOW1
XTBPRD_SHADOW1.
Definition: etpwm.h:2104
@ EPWM_OSHT_SYNC_OUT_TRIG_SYNC
Trigger is OSHT sync.
Definition: etpwm.h:321
HRPWM_CounterCompareModule
Definition: etpwm.h:1940
@ EPWM_TZ_EVENT_DCXL_LOW
Event when DCxL low.
Definition: etpwm.h:925
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D
Digital Compare event A/B 1 while counting down.
Definition: etpwm.h:1006
static void HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount)
Definition: etpwm.h:9116
EPWM_DigitalCompareSyncMode
Definition: etpwm.h:1492
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT15
Trip source is INPUTXBAR out15 signal.
Definition: etpwm.h:2374
static void EPWM_setTimeBaseCounter(uint32_t base, uint16_t count)
Definition: etpwm.h:2606
@ EPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:454
@ EPWM_DC_EDGEFILT_MODE_BOTH
Definition: etpwm.h:1670
@ EPWM_LINK_WITH_EPWM_13
link current ePWM with ePWM13
Definition: etpwm.h:401
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM16
Sync-in source is EPWM16 sync-out signal.
Definition: etpwm.h:220
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB
Time base counter up equals COMPB.
Definition: etpwm.h:563
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP4
Sync-in source is ECAP4 sync-out signal.
Definition: etpwm.h:260
@ EPWM_XCMP1_SHADOW2
XCMP1_SHADOW2.
Definition: etpwm.h:2107
static void EPWM_enableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:5019
@ EPWM_DC_TRIP_TRIPIN13
Trip 13.
Definition: etpwm.h:1335
@ HRPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2040
@ EPWM_DC_EDGEFILT_EDGECNT_7
Definition: etpwm.h:1696
@ HRPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:1992
@ EPWM_AQ_OUTPUT_B
ePWMxB output
Definition: etpwm.h:716
@ EPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR
Trip zone clear group.
Definition: etpwm.h:1710
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD
Time base counter equals period.
Definition: etpwm.h:557
static void EPWM_disableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6752
@ EPWM_SOC_TBCTR_ZERO
Time-base counter equal to zero.
Definition: etpwm.h:1272
@ EPWM_LINK_WITH_EPWM_29
link current ePWM with ePWM29
Definition: etpwm.h:417
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY
Definition: etpwm.h:1651
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT31
Trip source is INPUTXBAR out31 signal.
Definition: etpwm.h:2406
static void EPWM_setCounterCompareValue_opt_cmpC(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3623
@ EPWM_LINK_WITH_EPWM_14
link current ePWM with ePWM14
Definition: etpwm.h:402
static void EPWM_setActionQualifierT1TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3847
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM17
Sync-in source is EPWM17 sync-out signal.
Definition: etpwm.h:222
#define EPWM_MINDB_BLOCK_A
Values that can be passed to.
Definition: etpwm.h:1723
EPWM_ActionQualifierOutputEvent
Definition: etpwm.h:553
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD
load on sync or when counter equals period
Definition: etpwm.h:520
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADMULTIPLE
Load mode is LOADMULTIPLE.
Definition: etpwm.h:2278
@ EPWM_DC_EDGEFILT_EDGECNT_0
Digital Compare Edge filter edge count = 0.
Definition: etpwm.h:1682
@ EPWM_AQ_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:510
@ EPWM_DC_TYPE_DCAH
Digital Compare A High.
Definition: etpwm.h:1308
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1
Sync-in source is EPWM1 sync-out signal.
Definition: etpwm.h:190
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM31
Sync-in source is EPWM31 sync-out signal.
Definition: etpwm.h:250
@ EPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2140
@ HRPWM_OUTPUT_ON_B_INV_A
Definition: etpwm.h:1908
static void EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger)
Definition: etpwm.h:8442
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM3
Sync-in source is EPWM3 sync-out signal.
Definition: etpwm.h:194
@ EPWM_TZ_ACTION_EVENT_TZB
TZ1 - TZ6, DCBEVT2, DCBEVT1.
Definition: etpwm.h:939
static bool EPWM_getEventTriggerInterruptStatus(uint32_t base)
Definition: etpwm.h:5951
static void EPWM_setXCMPActionQualifierAction(uint32_t base, uint32_t shadowset, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_XCMPActionQualifierOutputEvent event)
Definition: etpwm.h:10288
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:481
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP4
Time base counter equals XCMP4.
Definition: etpwm.h:2210
@ EPWM_CLOCK_DIVIDER_64
Divide clock by 64.
Definition: etpwm.h:155
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T1
T1 event on count up and toggle the output pins.
Definition: etpwm.h:677
static void EPWM_selectDiodeEmulationTripSignal(uint32_t base, uint32_t channel, uint32_t signal)
Definition: etpwm.h:10778
static void EPWM_allocAXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPA alloctype)
Definition: etpwm.h:10109
@ EPWM_LINK_WITH_EPWM_3
link current ePWM with ePWM3
Definition: etpwm.h:391
EPWM_TimeBaseCountMode tbCtrMode
Time Base Counter Mode.
Definition: etpwm.h:2585
static void EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount)
Definition: etpwm.h:3232
static void EPWM_enableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:10560
EPWM_DigitalCompareType
Definition: etpwm.h:1307
@ EPWM_COMP_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:483
@ EPWM_REGISTER_GROUP_HR
HRPWM register group.
Definition: etpwm.h:1707
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA
Time base counter down equals COMPA and toggle the output pins.
Definition: etpwm.h:642
@ EPWM_LINK_WITH_EPWM_21
link current ePWM with ePWM21
Definition: etpwm.h:409
static void EPWM_forceEventTriggerInterrupt(uint32_t base)
Definition: etpwm.h:6119
static void EPWM_selectXbarInput(uint32_t base, uint32_t block, uint32_t xbarInput)
Definition: etpwm.h:9041
static void EPWM_setDiodeEmulationMode(uint32_t base, EPWM_DiodeEmulationMode mode)
Definition: etpwm.h:10618
EPWM_DeadBandOutput
Definition: etpwm.h:744
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U
Digital Compare event A/B 2 while counting up.
Definition: etpwm.h:1008
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG1
Sync-in source is FSI-RX0 RX Trigger 1 signal.
Definition: etpwm.h:282
@ EPWM_EMULATION_STOP_AFTER_FULL_CYCLE
Stop when counter completes whole cycle.
Definition: etpwm.h:124
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_D
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down.
Definition: etpwm.h:969
static void EPWM_disableValleyHWDelay(uint32_t base)
Definition: etpwm.h:8230
@ EPWM_SOC_TBCTR_MIXED_EVENT
Time-base counter equal to zero or period.
Definition: etpwm.h:1276
static void EPWM_setXCMPShadowBufPtrLoadOnce(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWBUFPTR ptr)
Definition: etpwm.h:10487
static void EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, EPWM_HSClockDivider highSpeedPrescaler)
Definition: etpwm.h:2677
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB
Time base counter up equals COMPB and toggle the output pins.
Definition: etpwm.h:650
static uint16_t EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base)
Definition: etpwm.h:7111
@ EPWM_AQ_OUTPUT_LOW_UP_CMPB
Time base counter up equals COMPB and set output pins to low.
Definition: etpwm.h:646
@ EPWM_RED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:813
@ EPWM_HSCLOCK_DIVIDER_8
Divide clock by 8.
Definition: etpwm.h:171
@ EPWM_TZ_DC_OUTPUT_A2
Digital Compare output 2 A.
Definition: etpwm.h:909
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT13
Trip source is INPUTXBAR out13 signal.
Definition: etpwm.h:2370
Float32 dutyValB
Desired ePWMxB Signal Duty.
Definition: etpwm.h:2582
static void EPWM_lockRegisters(uint32_t base, EPWM_LockRegisterGroup registerGroup)
Definition: etpwm.h:8696
static void HRPWM_disableAutoConversion(uint32_t base)
Definition: etpwm.h:9421
@ EPWM_DE_TRIP_SRC_CMPSSA2
Trip source is CMPSSA2 signal.
Definition: etpwm.h:2412
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM12
Sync-in source is EPWM12 sync-out signal.
Definition: etpwm.h:212
@ HRPWM_XCMP2_ACTIVE
XCMP2_ACTIVE.
Definition: etpwm.h:1973
#define EPWM_INT_TBCTR_D_CMPC
time-base counter equal to CMPC when the timer is decrementing
Definition: etpwm.h:1204
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2
T2 event on count down and no change in the output pins.
Definition: etpwm.h:695
@ EPWM_AQ_OUTPUT_TOGGLE_UP_T2
T2 event on count up and toggle the output pins.
Definition: etpwm.h:693
@ EPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:2083
static void EPWM_enableXLoad(uint32_t base)
Definition: etpwm.h:10351
@ EPWM_TZ_ACTION_DISABLE
disable action
Definition: etpwm.h:957
@ EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN
ePWM sync
Definition: etpwm.h:542
static void EPWM_forceADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6549
static uint32_t EPWM_getMinDeadBandDelay(uint32_t base, uint32_t block)
Definition: etpwm.h:8915
@ HRPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:1981
@ EPWM_XCMP_NONE_CMPA
Allocate 0 XCMP registers to CMPA.
Definition: etpwm.h:2230
static void EPWM_disableIllegalComboLogic(uint32_t base, uint32_t block)
Definition: etpwm.h:9011
@ EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD
load on sync event or when counter is equal to period or zero
Definition: etpwm.h:1550
static void EPWM_disableActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule)
Definition: etpwm.h:3808
static void EPWM_setADCTriggerEventPrescale(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t preScaleCount)
Definition: etpwm.h:6377
static void EPWM_enableInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:5995
EPWM_DiodeEmulationTripSource
Definition: etpwm.h:2342
static void EPWM_enableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7533
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_ONE
Shadow buffer 1 is in use.
Definition: etpwm.h:2312
@ EPWM_DC_WINDOW_SOURCE_DCAEVT1
DC filter signal source is DCAEVT1.
Definition: etpwm.h:1434
EPWM_DigitalCompareEvent
Definition: etpwm.h:1466
static void HRPWM_enableAutoConversion(uint32_t base)
Definition: etpwm.h:9399
@ EPWM_LINK_COMP_B
link COMPB registers
Definition: etpwm.h:432
@ EPWM_LINK_WITH_EPWM_6
link current ePWM with ePWM6
Definition: etpwm.h:394
static void EPWM_enableDigitalCompareWindowInverseMode(uint32_t base)
Definition: etpwm.h:6774
@ EPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2132
@ EPWM_LINK_WITH_EPWM_15
link current ePWM with ePWM15
Definition: etpwm.h:403
@ HRPWM_MEP_DUTY_PERIOD_CTRL
CMPAHR/CMPBHR or TBPRDHR controls MEP edge.
Definition: etpwm.h:1873
static void EPWM_disableDeadBandControlShadowLoadMode(uint32_t base)
Definition: etpwm.h:4637
@ EPWM_DE_TRIP_SRC_CMPSSA5
Trip source is CMPSSA5 signal.
Definition: etpwm.h:2418
@ EPWM_DB_POLARITY_ACTIVE_LOW
DB polarity is inverted.
Definition: etpwm.h:770
static void EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, EPWM_RisingEdgeDelayLoadMode loadMode)
Definition: etpwm.h:4666
@ EPWM_TZ_ADV_ACTION_DISABLE
disable action
Definition: etpwm.h:991
@ EPWM_CLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:151
@ EPWM_DC_EVENT_INPUT_SYNCED
DC input signal is synced with TBCLK.
Definition: etpwm.h:1494
@ EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD
Time base counter equals period and no change in the output pins.
Definition: etpwm.h:620
@ EPWM_LINK_DBRED
link DBRED registers
Definition: etpwm.h:436
EPWM_ValleyCounterEdge
Definition: etpwm.h:1625
EPWM_LockRegisterGroup
Definition: etpwm.h:1706
@ EPWM_SYNC_IN_PULSE_SRC_DISABLE
Disable Sync-in.
Definition: etpwm.h:186
static void EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4555
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_THREE
Shadow buffer 3 is in use.
Definition: etpwm.h:2316
EPWM_SyncCountMode
Definition: etpwm.h:136
@ EPWM_RED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:819
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG0
Sync-in source is FSI-RX1 RX Trigger 0 signal.
Definition: etpwm.h:288
@ EPWM_HSCLOCK_DIVIDER_12
Divide clock by 12.
Definition: etpwm.h:173
HRPWM_Channel
Definition: etpwm.h:1841
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM21
Sync-in source is EPWM21 sync-out signal.
Definition: etpwm.h:230
static void EPWM_setDeadBandControlShadowLoadMode(uint32_t base, EPWM_DeadBandControlLoadMode loadMode)
Definition: etpwm.h:4612
@ EPWM_DC_TRIP_TRIPIN4
Trip 4.
Definition: etpwm.h:1326
EPWM_HSClockDivider
Definition: etpwm.h:166
@ EPWM_RED_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:815
static void HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap)
Definition: etpwm.h:9343
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPA
Time base counter down equals COMPA and set output pins to low.
Definition: etpwm.h:638
static void EPWM_disableIndependentPulseLogic(uint32_t base)
Definition: etpwm.h:7885
@ HRPWM_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1855
@ EPWM_AQ_OUTPUT_NO_CHANGE_ZERO
Time base counter equals zero and no change in the output pins.
Definition: etpwm.h:612
@ EPWM_DE_TRIP_SRC_CMPSSA1
Trip source is CMPSSA1 signal.
Definition: etpwm.h:2410
static void EPWM_selectCaptureTripInput(uint32_t base, EPWM_DigitalCompareTripInput tripSource, uint8_t dcType)
Definition: etpwm.h:7942
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT19
Trip source is INPUTXBAR out19 signal.
Definition: etpwm.h:2382
@ EPWM_AQ_OUTPUT_LOW
Set output pins to low.
Definition: etpwm.h:585
@ EPWM_XCMP_1_CMPB
Allocate XCMP5 register to CMPB.
Definition: etpwm.h:2258
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT8
Trip source is INPUTXBAR out8 signal.
Definition: etpwm.h:2360
static uint16_t EPWM_getTimeBaseCounterDirection(uint32_t base)
Definition: etpwm.h:3208
HRPWM_LoadMode
Definition: etpwm.h:1886
@ EPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:2069
static void EPWM_selectMinimumDeadBandAndOrLogic(uint32_t base, uint32_t block, uint32_t referenceSignal)
Definition: etpwm.h:8816
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM19
Sync-in source is EPWM19 sync-out signal.
Definition: etpwm.h:226
static uint16_t EPWM_getDigitalCompareCaptureCount(uint32_t base)
Definition: etpwm.h:7640
static void EPWM_setDigitalCompareBlankingEvent(uint32_t base, EPWM_DigitalCompareBlankingPulse blankingPulse, uint16_t mixedSource)
Definition: etpwm.h:6825
#define EPWM_INT_TBCTR_U_CMPD
time-base counter equal to CMPD when the timer is incrementing
Definition: etpwm.h:1208
@ EPWM_XCMP_XLOADCTL_LOADMODE_LOADONCE
Load mode is LOADONCE.
Definition: etpwm.h:2276
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG1
Sync-in source is FSI-RX3 RX Trigger 1 signal.
Definition: etpwm.h:306
@ EPWM_LINK_XLOAD
link XLOAD registers
Definition: etpwm.h:438
@ EPWM_TZ_ADV_ACTION_EVENT_TZB_U
TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up.
Definition: etpwm.h:971
@ EPWM_TZ_EVENT_DC_DISABLED
Event is disabled.
Definition: etpwm.h:922
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_3
SHDW3, SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2297
static uint16_t EPWM_getInterruptEventCount(uint32_t base)
Definition: etpwm.h:6097
@ HRPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2023
static void EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode)
Definition: etpwm.h:7580
Float32 freqInHz
Desired Signal Frequency(in Hz)
Definition: etpwm.h:2580
@ EPWM_ACTION_QUALIFIER_A
Action Qualifier A.
Definition: etpwm.h:497
#define EPWM_DE_TRIPH
Definition: etpwm.h:2492
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM11
Sync-in source is EPWM11 sync-out signal.
Definition: etpwm.h:210
@ EPWM_DE_TRIP_SRC_CMPSSB5
Trip source is CMPSSB5 signal.
Definition: etpwm.h:2438
@ EPWM_DE_TRIP_SRC_CMPSSA4
Trip source is CMPSSA4 signal.
Definition: etpwm.h:2416
#define EPWM_XCMP_SHADOW3
Definition: etpwm.h:2058
EPWM_TripZoneEvent
Definition: etpwm.h:937
@ HRPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2017
@ HRPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:1975
@ EPWM_DC_TRIP_COMBINATION
All Trips (Trip1 - Trip 15) are selected.
Definition: etpwm.h:1338
@ EPWM_GL_LOAD_PULSE_GLOBAL_FORCE
load on global force
Definition: etpwm.h:1560
@ EPWM_DC_TRIP_TRIPIN15
Trip 15.
Definition: etpwm.h:1337
static void EPWM_disableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8522
#define EPWM_INT_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1202
EPWM_DigitalCompareBlankingPulse
Definition: etpwm.h:1388
static uint16_t HRPWM_getHiResCounterCompareValueOnly(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9751
static void EPWM_forceSyncPulse(uint32_t base)
Definition: etpwm.h:2704
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY
Definition: etpwm.h:1648
EPWM_ValleyDelayMode
Definition: etpwm.h:1637
@ EPWM_LINK_WITH_EPWM_11
link current ePWM with ePWM11
Definition: etpwm.h:399
@ EPWM_CLOCK_DIVIDER_1
Divide clock by 1.
Definition: etpwm.h:149
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA
Time base counter up equals COMPA and no change in the output pins.
Definition: etpwm.h:628
@ EPWM_XCMP_3_CMPA
Allocate XCMP1 - XCMP3 registers to CMPA.
Definition: etpwm.h:2236
#define EPWM_CAPTURE_GATE
Capture Gate.
Definition: etpwm.h:2529
static void EPWM_setSyncInPulseSource(uint32_t base, EPWM_SyncInPulseSource source)
Definition: etpwm.h:2744
@ EPWM_DE_TRIP_SRC_CMPSSB8
Trip source is CMPSSB8 signal.
Definition: etpwm.h:2444
@ EPWM_TZ_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:954
static void EPWM_allocBXCMP(uint32_t base, EPWM_XCMP_ALLOC_CMPB alloctype)
Definition: etpwm.h:10136
@ HRPWM_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:1890
static void EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, EPWM_TripZoneAdvancedAction tzAdvDCAction)
Definition: etpwm.h:5296
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT6
Trip source is INPUTXBAR out6 signal.
Definition: etpwm.h:2356
static void EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, EPWM_DigitalCompareEdgeFilterMode edgeMode)
Definition: etpwm.h:6942
@ EPWM_LINK_WITH_EPWM_23
link current ePWM with ePWM23
Definition: etpwm.h:411
@ EPWM_EMULATION_STOP_AFTER_NEXT_TB
Stop after next Time Base counter increment or decrement.
Definition: etpwm.h:122
static void EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount)
Definition: etpwm.h:8469
@ EPWM_SOC_TBCTR_D_CMPA
time-base counter equal to CMPA when the timer is decrementing
Definition: etpwm.h:1282
@ EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL
signal source is unfiltered (DCAEVT1/2)
Definition: etpwm.h:1480
bool invertSignalB
Invert ePWMxB Signal if true.
Definition: etpwm.h:2583
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG2
Sync-in source is FSI-RX1 RX Trigger 2 signal.
Definition: etpwm.h:292
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN
T2 event on count down.
Definition: etpwm.h:573
static void EPWM_setActionQualifierAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output, EPWM_ActionQualifierOutputEvent event)
Definition: etpwm.h:3937
@ EPWM_DB_FED
DB FED (Falling Edge Delay) mode.
Definition: etpwm.h:758
static void EPWM_disableMinimumDeadBand(uint32_t base, uint32_t block)
Definition: etpwm.h:8750
@ EPWM_TZ_DC_OUTPUT_B2
Digital Compare output 2 B.
Definition: etpwm.h:911
static void EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, uint16_t compCount)
Definition: etpwm.h:3542
@ EPWM_TZ_ADV_ACTION_HIGH_Z
high impedance output
Definition: etpwm.h:987
static uint16_t EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base)
Definition: etpwm.h:7091
static void EPWM_invertMinimumDeadBandSignal(uint32_t base, uint32_t block, uint32_t invert)
Definition: etpwm.h:8781
@ EPWM_DE_TRIP_SRC_CMPSSA8
Trip source is CMPSSA8 signal.
Definition: etpwm.h:2424
@ EPWM_DC_TYPE_DCBL
Digital Compare B Low.
Definition: etpwm.h:1311
@ EPWM_CLOCK_DIVIDER_2
Divide clock by 2.
Definition: etpwm.h:150
EPWM_DeadBandDelayMode
Definition: etpwm.h:756
static void EPWM_invertCaptureInputPolarity(uint32_t base, uint8_t polSel)
Definition: etpwm.h:7837
static void EPWM_enableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6893
@ HRPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:1996
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM26
Sync-in source is EPWM26 sync-out signal.
Definition: etpwm.h:240
@ EPWM_DC_EDGEFILT_EDGECNT_3
Digital Compare Edge filter edge count = 4.
Definition: etpwm.h:1688
@ HRPWM_LOAD_ON_CMPB_EQ
load on translater event CMPB-3
Definition: etpwm.h:1894
#define EPWM_INT_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1198
static void EPWM_setCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule, EPWM_CounterCompareLoadMode loadMode)
Definition: etpwm.h:3414
EPWM_OneShotSyncOutTrigger
Definition: etpwm.h:320
static void EPWM_setXCMPRegValue(uint32_t base, EPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:10164
static void EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount)
Definition: etpwm.h:4802
static void EPWM_enableSplitXCMP(uint32_t base)
Definition: etpwm.h:10054
static void EPWM_configCaptureGateInputPolarity(uint32_t base, uint8_t polSel)
Definition: etpwm.h:7809
@ EPWM_TZ_EVENT_DCXH_HIGH
Event when DCxH high.
Definition: etpwm.h:924
@ EPWM_CLOCK_DIVIDER_16
Divide clock by 16.
Definition: etpwm.h:153
@ EPWM_DC_TRIP_TRIPIN12
Trip 12.
Definition: etpwm.h:1334
@ EPWM_XCMP_2_CMPB
Allocate XCMP5 - XCMP6 registers to CMPB.
Definition: etpwm.h:2260
static void EPWM_disableDiodeEmulationMode(uint32_t base)
Definition: etpwm.h:10586
@ EPWM_XCMP5_SHADOW2
XCMP5_SHADOW2.
Definition: etpwm.h:2115
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT5
Trip source is INPUTXBAR out5 signal.
Definition: etpwm.h:2354
@ EPWM_LINK_WITH_EPWM_10
link current ePWM with ePWM10
Definition: etpwm.h:398
static void EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6147
@ EPWM_DC_TRIP_TRIPIN10
Trip 10.
Definition: etpwm.h:1332
@ EPWM_XMIN_SHADOW2
XMIN_SHADOW2.
Definition: etpwm.h:2188
@ HRPWM_XCMP8_SHADOW3
XCMP8_SHADOW3.
Definition: etpwm.h:2042
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP2
Sync-in source is ECAP2 sync-out signal.
Definition: etpwm.h:256
static void EPWM_setADCTriggerEventCountInitValue(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType, uint16_t eventCount)
Definition: etpwm.h:6579
HRPWM_MEPDeadBandEdgeMode
Definition: etpwm.h:1952
@ EPWM_SOC_TBCTR_U_CMPC
time-base counter equal to CMPC when the timer is incrementing
Definition: etpwm.h:1280
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT4
Trip source is INPUTXBAR out4 signal.
Definition: etpwm.h:2352
@ EPWM_VALLEY_COUNT_STOP_EDGE
Valley count stop edge.
Definition: etpwm.h:1627
@ EPWM_COUNTER_MODE_STOP_FREEZE
Stop - Freeze counter.
Definition: etpwm.h:350
static void EPWM_setCounterCompareValue_opt_cmpB(uint32_t base, uint16_t compCount)
Definition: etpwm.h:3604
@ EPWM_LINK_WITH_EPWM_17
link current ePWM with ePWM17
Definition: etpwm.h:405
static void EPWM_setDigitalCompareCBCLatchMode(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchMode latchMode)
Definition: etpwm.h:7382
static void EPWM_forceGlobalLoadOneShotEvent(uint32_t base)
Definition: etpwm.h:8591
static bool EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge)
Definition: etpwm.h:8302
EPWM_ActionQualifierOutput
Definition: etpwm.h:583
@ EPWM_DC_EDGEFILT_MODE_RISING
Digital Compare Edge filter low to high edge mode.
Definition: etpwm.h:1666
@ EPWM_TZ_ACTION_EVENT_DCBEVT2
DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:943
@ EPWM_AQ_OUTPUT_LOW_UP_T1
T1 event on count up and set output pins to low.
Definition: etpwm.h:673
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM14
Sync-in source is EPWM14 sync-out signal.
Definition: etpwm.h:216
@ EPWM_XCMP2_SHADOW1
XCMP2_SHADOW1.
Definition: etpwm.h:2090
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT7
Trip source is INPUTXBAR out7 signal.
Definition: etpwm.h:2358
@ HRPWM_PWMSYNC_SOURCE_COMPC_DOWN
Counter equals COMPC when counting down.
Definition: etpwm.h:1926
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM10
Sync-in source is EPWM10 sync-out signal.
Definition: etpwm.h:208
EPWM_ClockDivider
Definition: etpwm.h:148
#define EPWM_DB_INPUT_DB_RED
Input signal is the output of Rising Edge delay.
Definition: etpwm.h:784
EPWM_LinkComponent
Definition: etpwm.h:429
static void EPWM_disableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2836
static void EPWM_disableADCTriggerEventCountInit(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6520
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_D
load when counter is equal to cmpd and cmpd is decrementing
Definition: etpwm.h:1558
@ EPWM_XMAX_SHADOW1
XMAX_SHADOW1.
Definition: etpwm.h:2182
HRPWM_SyncPulseSource
Definition: etpwm.h:1918
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT17
Trip source is INPUTXBAR out17 signal.
Definition: etpwm.h:2378
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO
Valley capture trigged by when counter is equal to zero.
Definition: etpwm.h:1603
@ EPWM_AQ_OUTPUT_LOW_DOWN_CMPB
Time base counter down equals COMPB and set output pins to low.
Definition: etpwm.h:654
EPWM_DigitalCompareModule
Definition: etpwm.h:1451
static bool EPWM_getADCTriggerFlagStatus(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6432
@ EPWM_FED_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:837
EPWM_DigitalCompareCBCLatchMode
Definition: etpwm.h:1506
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX1_RX_TRIG3
Sync-in source is FSI-RX1 RX Trigger 3 signal.
Definition: etpwm.h:294
@ EPWM_SOC_B
SOC B.
Definition: etpwm.h:1258
@ HRPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:1983
@ EPWM_PERIOD_SHADOW_LOAD
PWM Period register access is through shadow register.
Definition: etpwm.h:334
@ EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D
Digital Compare event A/B 2 while counting down.
Definition: etpwm.h:1010
@ EPWM_DC_EDGEFILT_EDGECNT_1
Digital Compare Edge filter edge count = 2.
Definition: etpwm.h:1684
static void HRPWM_setHiResCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint16_t hrCompCount)
Definition: etpwm.h:9704
@ EPWM_DC_EVENT_SOURCE_FILT_SIGNAL
signal source is filtered (DCEVTFILT)
Definition: etpwm.h:1482
@ EPWM_DE_TRIP_SRC_CMPSSA3
Trip source is CMPSSA3 signal.
Definition: etpwm.h:2414
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM23
Sync-in source is EPWM23 sync-out signal.
Definition: etpwm.h:234
@ EPWM_LINK_WITH_EPWM_8
link current ePWM with ePWM8
Definition: etpwm.h:396
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPB
Time base counter up equals COMPB and set output pins to high.
Definition: etpwm.h:648
static bool EPWM_getTimeBaseCounterOverflowStatus(uint32_t base)
Definition: etpwm.h:3119
@ EPWM_DE_TRIP_SRC_CMPSSA9
Trip source is CMPSSA9 signal.
Definition: etpwm.h:2426
@ EPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:455
@ EPWM_SOC_DCxEVT1
Event is based on DCxEVT1.
Definition: etpwm.h:1270
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1
T1 event on count up and no change in the output pins.
Definition: etpwm.h:671
@ EPWM_DC_CBC_LATCH_ENABLED
DC cycle-by-cycle(CBC) latch is enabled.
Definition: etpwm.h:1510
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1
Trip zone 1.
Definition: etpwm.h:539
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM28
Sync-in source is EPWM28 sync-out signal.
Definition: etpwm.h:244
static void EPWM_setXMINMAXRegValue(uint32_t base, EPWM_XMinMaxReg xminmaxReg, uint16_t xcmpvalue)
Definition: etpwm.h:10234
EPWM_ValleyTriggerSource
Definition: etpwm.h:1599
@ EPWM_DC_TRIP_TRIPIN6
Trip 6.
Definition: etpwm.h:1328
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP5
Sync-in source is ECAP5 sync-out signal.
Definition: etpwm.h:262
@ EPWM_TZ_ADV_ACTION_TOGGLE
toggle the output
Definition: etpwm.h:990
@ EPWM_LINK_COMP_A
link COMPA registers
Definition: etpwm.h:431
static void EPWM_enableGlobalLoad(uint32_t base)
Definition: etpwm.h:8381
static void EPWM_disableValleyCapture(uint32_t base)
Definition: etpwm.h:8096
@ EPWM_TZ_ADV_ACTION_HIGH
high voltage state
Definition: etpwm.h:988
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1
Valley capture trigged by DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:1613
EPWM_AdditionalActionQualifierEventAction
Definition: etpwm.h:669
static void EPWM_configureDiodeEmulationTripSources(uint32_t base, EPWM_DiodeEmulationTripSource source, uint32_t tripLorH)
Definition: etpwm.h:10687
@ EPWM_XCMP7_SHADOW2
XCMP7_SHADOW2.
Definition: etpwm.h:2119
static void EPWM_forceCaptureEventLoad(uint32_t base)
Definition: etpwm.h:7908
static void EPWM_enableChopper(uint32_t base)
Definition: etpwm.h:4857
@ HRPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2025
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO
Time base counter equals zero.
Definition: etpwm.h:555
@ EPWM_DC_TRIP_TRIPIN3
Trip 3.
Definition: etpwm.h:1325
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG1
Sync-in source is FSI-RX2 RX Trigger 1 signal.
Definition: etpwm.h:298
static void EPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2931
static void EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, EPWM_TripZoneDigitalCompareOutput dcType, EPWM_TripZoneDigitalCompareOutputEvent dcEvent)
Definition: etpwm.h:5104
@ EPWM_AQ_SW_IMMEDIATE_LOAD
No shadow load mode. Immediate mode only.
Definition: etpwm.h:734
@ EPWM_DC_WINDOW_SOURCE_DCBEVT1
DC filter signal source is DCBEVT1.
Definition: etpwm.h:1436
static void EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base)
Definition: etpwm.h:3142
EPWM_DeadBandPolarity
Definition: etpwm.h:768
@ EPWM_DC_TRIP_TRIPIN7
Trip 7.
Definition: etpwm.h:1329
@ EPWM_LINK_WITH_EPWM_28
link current ePWM with ePWM28
Definition: etpwm.h:416
HRPWM_MEPEdgeMode
Definition: etpwm.h:1853
static void EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6180
@ EPWM_DB_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:801
static void HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9316
static void EPWM_disableCaptureTripCombinationInput(uint32_t base, uint16_t tripInput, uint8_t dcType)
Definition: etpwm.h:8035
@ EPWM_XCMP7_SHADOW3
XCMP7_SHADOW3.
Definition: etpwm.h:2138
static void EPWM_enableDiodeEmulationMonitorModeControl(uint32_t base)
Definition: etpwm.h:10907
@ EPWM_XCMP_XLOADCTL_SHDWBUFPTR_NULL
No Shadow buffer is in use.
Definition: etpwm.h:2310
static void EPWM_enableDigitalCompareBlankingWindow(uint32_t base)
Definition: etpwm.h:6731
@ EPWM_DC_WINDOW_START_TBCTR_PERIOD
Time base counter equals period.
Definition: etpwm.h:1390
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT11
Trip source is INPUTXBAR out11 signal.
Definition: etpwm.h:2366
EPWM_TripZoneAdvancedAction
Definition: etpwm.h:986
@ EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY
Definition: etpwm.h:1642
@ EPWM_CMPC_SHADOW2
CMPC_SHADOW2.
Definition: etpwm.h:2159
@ HRPWM_MEP_CTRL_RISING_EDGE
MEP controls rising edge.
Definition: etpwm.h:1857
@ EPWM_DC_TRIP_TRIPIN14
Trip 14.
Definition: etpwm.h:1336
#define EPWM_DE_CHANNEL_A
< Diode emulation channel A
Definition: etpwm.h:2468
static void HRPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:9506
static void EPWM_disableTripZoneOutput(uint32_t base, uint16_t tzOutput)
Definition: etpwm.h:5758
@ EPWM_XCMP_8_CMPA
Allocate XCMP1 - XCMP8 registers to CMPA.
Definition: etpwm.h:2246
@ EPWM_XCMP6_SHADOW3
XCMP6_SHADOW3.
Definition: etpwm.h:2136
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT26
Trip source is INPUTXBAR out26 signal.
Definition: etpwm.h:2396
@ EPWM_AQ_OUTPUT_TOGGLE_PERIOD
Time base counter equals period and toggle the output pins.
Definition: etpwm.h:626
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD
Valley capture trigged when counter is equal to zero or period.
Definition: etpwm.h:1607
static void EPWM_setActionQualifierSWAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierOutput output)
Definition: etpwm.h:4302
static void EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8667
@ EPWM_COUNTER_MODE_UP_DOWN
Up - down - count mode.
Definition: etpwm.h:349
@ EPWM_DC_TRIP_TRIPIN11
Trip 11.
Definition: etpwm.h:1333
static void EPWM_enableOneShotSync(uint32_t base)
Definition: etpwm.h:3033
static void EPWM_enableSyncOutPulseSource(uint32_t base, uint16_t source)
Definition: etpwm.h:2791
static void EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_AdditionalActionQualifierEventAction action)
Definition: etpwm.h:4140
EPWM_TripZoneAction
Definition: etpwm.h:953
@ HRPWM_DB_MEP_CTRL_RED_FED
MEP controls both Falling and Rising edge delay.
Definition: etpwm.h:1960
@ EPWM_XCMP6_ACTIVE
XCMP6_ACTIVE.
Definition: etpwm.h:2079
#define EPWM_LOCK_KEY
Definition: etpwm.h:2570
@ HRPWM_MEP_CTRL_FALLING_EDGE
MEP controls falling edge.
Definition: etpwm.h:1859
@ EPWM_DE_TRIP_SRC_CMPSSB3
Trip source is CMPSSB3 signal.
Definition: etpwm.h:2434
@ EPWM_DE_TRIP_SRC_CMPSSB6
Trip source is CMPSSB6 signal.
Definition: etpwm.h:2440
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP8
Sync-in source is ECAP8 sync-out signal.
Definition: etpwm.h:268
@ EPWM_DC_CBC_LATCH_DISABLED
DC cycle-by-cycle(CBC) latch is disabled.
Definition: etpwm.h:1508
@ EPWM_LINK_GLDCTL2
link GLDCTL2 registers
Definition: etpwm.h:435
@ EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD
Valley capture trigged by when counter is equal period.
Definition: etpwm.h:1605
EPWM_TripZoneAdvDigitalCompareEvent
Definition: etpwm.h:1002
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT9
Trip source is INPUTXBAR out9 signal.
Definition: etpwm.h:2362
static void EPWM_selectMinimumDeadBandBlockingSignal(uint32_t base, uint32_t block, uint32_t blockingSignal)
Definition: etpwm.h:8850
EPWM_DigitalCompareEventSource
Definition: etpwm.h:1478
@ EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC
Definition: etpwm.h:365
static void EPWM_setDiodeEmulationMonitorCounterThreshold(uint32_t base, uint16_t threshold)
Definition: etpwm.h:10994
static void EPWM_enableCaptureTripCombinationInput(uint32_t base, uint16_t tripInput, uint8_t dcType)
Definition: etpwm.h:7986
EPWM_XCMP_ALLOC_CMPB
Values that can be passed to EPWM_allocBXCMP() as the alloctype parameter.
Definition: etpwm.h:2256
@ EPWM_AQ_OUTPUT_ON_T2_COUNT_UP
T2 event on count up.
Definition: etpwm.h:571
static void EPWM_enableIndependentPulseLogic(uint32_t base)
Definition: etpwm.h:7861
static uint16_t EPWM_getOneShotTripZoneFlagStatus(uint32_t base)
Definition: etpwm.h:5523
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB
Time base counter down equals COMPB and toggle the output pins.
Definition: etpwm.h:658
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP7
Time base counter equals XCMP7.
Definition: etpwm.h:2216
@ HRPWM_OUTPUT_ON_B_NORMAL
ePWMxB output is normal.
Definition: etpwm.h:1906
static void EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, EPWM_TripZoneAction tzAction)
Definition: etpwm.h:5194
@ EPWM_FED_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:831
EPWM_DigitalCompareEdgeFilterMode
Definition: etpwm.h:1664
static void EPWM_disableCaptureInEvent(uint32_t base)
Definition: etpwm.h:7780
@ HRPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2019
@ EPWM_LINK_WITH_EPWM_7
link current ePWM with ePWM7
Definition: etpwm.h:395
@ EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB
Time base counter up equals COMPB and no change in the output pins.
Definition: etpwm.h:644
static void EPWM_setDigitalCompareFilterInput(uint32_t base, EPWM_DigitalCompareFilterInput filterInput)
Definition: etpwm.h:6866
@ HRPWM_XCMP1_ACTIVE
XCMP1_ACTIVE.
Definition: etpwm.h:1971
@ EPWM_AQ_OUTPUT_LOW_DOWN_T1
T1 event on count down and set output pins to low.
Definition: etpwm.h:681
#define EPWM_INT_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1206
@ EPWM_DC_EDGEFILT_EDGECNT_5
Digital Compare Edge filter edge count = 6.
Definition: etpwm.h:1692
@ EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:835
@ EPWM_TZ_EVENT_DCXL_HIGH
Event when DCxL high.
Definition: etpwm.h:926
@ EPWM_TZ_ACTION_EVENT_DCAEVT1
DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:940
@ EPWM_TZ_EVENT_DCXH_LOW
Event when DCxH low.
Definition: etpwm.h:923
@ EPWM_AQ_OUTPUT_HIGH_UP_CMPA
Time base counter up equals COMPA and set output pins to high.
Definition: etpwm.h:632
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX0_RX_TRIG3
Sync-in source is FSI-RX0 RX Trigger 3 signal.
Definition: etpwm.h:286
static void EPWM_forceInterruptEventCountInit(uint32_t base)
Definition: etpwm.h:6044
static uint16_t EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base)
Definition: etpwm.h:7001
@ EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:477
@ EPWM_AQ_OUTPUT_HIGH
Set output pins to High.
Definition: etpwm.h:586
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD
load when counter is equal to zero or period
Definition: etpwm.h:1542
@ HRPWM_DB_MEP_CTRL_DISABLE
HRPWM is disabled.
Definition: etpwm.h:1954
@ EPWM_DC_TRIP_TRIPIN9
Trip 9.
Definition: etpwm.h:1331
@ EPWM_XCMP3_ACTIVE
XCMP3_ACTIVE.
Definition: etpwm.h:2073
static void EPWM_enableGlobalLoadOneShotMode(uint32_t base)
Definition: etpwm.h:8546
EPWM_RisingEdgeDelayLoadMode
Definition: etpwm.h:811
@ EPWM_SOC_TBCTR_D_CMPB
time-base counter equal to CMPB when the timer is decrementing
Definition: etpwm.h:1290
EPWM_CycleByCycleTripZoneClearMode
Definition: etpwm.h:1122
#define EPWM_DE_COUNT_UP
Values that can be passed to EPWM_setDiodeEmulationMonitorModeStep()
Definition: etpwm.h:2479
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD
shadow mode load when counter equals period
Definition: etpwm.h:730
@ EPWM_VALLEY_COUNT_START_EDGE
Valley count start edge.
Definition: etpwm.h:1626
EPWM_XCMPActionQualifierOutputEvent
Values that can be passed to EPWM_setXCMPActionQualifierAction() as the event parameter.
Definition: etpwm.h:2202
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT2
Trip source is INPUTXBAR out2 signal.
Definition: etpwm.h:2348
@ EPWM_DE_TRIP_SRC_CMPSSA7
Trip source is CMPSSA7 signal.
Definition: etpwm.h:2422
@ EPWM_LINK_WITH_EPWM_27
link current ePWM with ePWM27
Definition: etpwm.h:415
@ EPWM_DC_EDGEFILT_MODE_FALLING
Digital Compare Edge filter both edges mode.
Definition: etpwm.h:1668
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD
shadow mode load when counter equals zero or period
Definition: etpwm.h:732
@ EPWM_XCMP8_SHADOW2
XCMP8_SHADOW2.
Definition: etpwm.h:2121
static void HRPWM_setHiResPhaseShift(uint32_t base, uint16_t hrPhaseCount)
Definition: etpwm.h:9146
@ EPWM_XCMP3_SHADOW2
XCMP3_SHADOW2.
Definition: etpwm.h:2111
@ EPWM_DC_EVENT_2
Digital Compare Event number 2.
Definition: etpwm.h:1468
@ HRPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2011
@ EPWM_COUNTER_COMPARE_C
counter compare C
Definition: etpwm.h:456
static void EPWM_disableDigitalCompareCounterCapture(uint32_t base)
Definition: etpwm.h:7554
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP6
Sync-in source is ECAP6 sync-out signal.
Definition: etpwm.h:264
static void EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5387
static void EPWM_setLutDecX(uint32_t base, uint32_t block, uint32_t decx, uint32_t force)
Definition: etpwm.h:9075
@ EPWM_LINK_WITH_EPWM_19
link current ePWM with ePWM19
Definition: etpwm.h:407
@ EPWM_AQ_OUTPUT_LOW_PERIOD
Time base counter equals period and set output pins to low.
Definition: etpwm.h:622
EPWM_DiodeEmulationMode
Definition: etpwm.h:2328
@ EPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2126
@ EPWM_XCMP4_SHADOW1
XCMP4_SHADOW1.
Definition: etpwm.h:2094
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP7
Sync-in source is ECAP7 sync-out signal.
Definition: etpwm.h:266
static void EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount)
Definition: etpwm.h:7071
static void EPWM_setDiodeEmulationReentryDelay(uint32_t base, uint8_t delay)
Definition: etpwm.h:10654
@ EPWM_CMPC_SHADOW1
CMPC_SHADOW1.
Definition: etpwm.h:2155
static void EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base)
Definition: etpwm.h:4692
@ EPWM_DB_COUNTER_CLOCK_HALF_CYCLE
Dead band counter runs at 2*TBCLK rate.
Definition: etpwm.h:851
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM5
Sync-in source is EPWM5 sync-out signal.
Definition: etpwm.h:198
@ EPWM_DC_TRIP_TRIPIN2
Trip 2.
Definition: etpwm.h:1324
@ EPWM_XCMP_4_CMPB
Allocate XCMP5 - XCMP8 registers to CMPB.
Definition: etpwm.h:2264
static void EPWM_forceXLoad(uint32_t base)
Definition: etpwm.h:10391
static bool EPWM_getCounterCompareShadowStatus(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3715
@ EPWM_CMPD_SHADOW2
CMPD_SHADOW2.
Definition: etpwm.h:2161
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP3
Time base counter equals XCMP3.
Definition: etpwm.h:2208
static void EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode)
Definition: etpwm.h:2898
@ EPWM_AQ_OUTPUT_HIGH_DOWN_T2
T2 event on count down and set output pins to high.
Definition: etpwm.h:699
static void EPWM_setActionQualifierShadowLoadMode(uint32_t base, EPWM_ActionQualifierModule aqModule, EPWM_ActionQualifierLoadMode loadMode)
Definition: etpwm.h:3767
static void EPWM_setActionQualifierContSWForceAction(uint32_t base, EPWM_ActionQualifierOutputModule epwmOutput, EPWM_ActionQualifierSWOutput output)
Definition: etpwm.h:4216
@ HRPWM_XCMP1_SHADOW1
XCMP1_SHADOW1.
Definition: etpwm.h:1990
@ EPWM_SOC_TBCTR_U_CMPB
time-base counter equal to CMPB when the timer is incrementing
Definition: etpwm.h:1286
static void EPWM_selectDiodeEmulationPWMsignal(uint32_t base, uint32_t channel, EPWM_DiodeEmulationSignal signal)
Definition: etpwm.h:10734
@ HRPWM_XCMP1_SHADOW3
XCMP1_SHADOW3.
Definition: etpwm.h:2028
EPWM_FallingEdgeDelayLoadMode
Definition: etpwm.h:829
static void EPWM_disablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:2952
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB
Time base counter down equals COMPB.
Definition: etpwm.h:565
@ EPWM_DE_LOW
a constant low signal
Definition: etpwm.h:2457
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT0
Trip source is INPUTXBAR out0 signal.
Definition: etpwm.h:2344
static void EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags)
Definition: etpwm.h:5664
@ EPWM_DB_OUTPUT_B
DB output is ePWMB.
Definition: etpwm.h:746
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT20
Trip source is INPUTXBAR out20 signal.
Definition: etpwm.h:2384
@ EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO
Clear CBC pulse when counter equals zero.
Definition: etpwm.h:1124
@ EPWM_GL_LOAD_PULSE_CNTR_CMPD_U
load when counter is equal to cmpd and cmpd is incrementing
Definition: etpwm.h:1556
static void EPWM_setXCMPShadowLevel(uint32_t base, EPWM_XCMP_XLOADCTL_SHDWLEVEL level)
Definition: etpwm.h:10456
@ HRPWM_COUNTER_COMPARE_A
counter compare A
Definition: etpwm.h:1941
@ EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO
shadow mode load when counter equals zero
Definition: etpwm.h:728
@ EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1
T1 event on count down and toggle the output pins.
Definition: etpwm.h:685
@ EPWM_AQ_LOAD_ON_SYNC_ONLY
load on sync only
Definition: etpwm.h:524
@ HRPWM_XCMP4_SHADOW3
XCMP4_SHADOW3.
Definition: etpwm.h:2034
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM13
Sync-in source is EPWM13 sync-out signal.
Definition: etpwm.h:214
@ EPWM_LINK_COMP_D
link COMPD registers
Definition: etpwm.h:434
@ EPWM_COUNT_MODE_UP_AFTER_SYNC
Count up after sync event.
Definition: etpwm.h:138
@ EPWM_DC_EDGEFILT_EDGECNT_4
Digital Compare Edge filter edge count = 5.
Definition: etpwm.h:1690
static void EPWM_enableValleyCapture(uint32_t base)
Definition: etpwm.h:8075
static void EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, bool enableDelayMode)
Definition: etpwm.h:4436
@ EPWM_DE_TRIP_SRC_CMPSSB7
Trip source is CMPSSB7 signal.
Definition: etpwm.h:2442
@ EPWM_CMPC_SHADOW3
CMPC_SHADOW3.
Definition: etpwm.h:2163
@ EPWM_AQ_OUTPUT_HIGH_UP_T2
T2 event on count up and set output pins to high.
Definition: etpwm.h:691
@ EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB
Time base counter down equals COMPB and no change in the output pins.
Definition: etpwm.h:652
static void EPWM_setActionQualifierT2TriggerSource(uint32_t base, EPWM_ActionQualifierTriggerSource trigger)
Definition: etpwm.h:3882
static void EPWM_disableTripZoneSignals(uint32_t base, uint32_t tzSignal)
Definition: etpwm.h:5062
@ EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA
Time base counter up equals COMPA and toggle the output pins.
Definition: etpwm.h:634
static void HRPWM_setXCMPRegValue(uint32_t base, HRPWM_XCMPReg xcmpReg, uint16_t xcmpvalue)
Definition: etpwm.h:9981
@ EPWM_DC_TRIP_TRIPIN8
Trip 8.
Definition: etpwm.h:1330
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM30
Sync-in source is EPWM30 sync-out signal.
Definition: etpwm.h:248
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG2
Sync-in source is FSI-RX3 RX Trigger 2 signal.
Definition: etpwm.h:308
@ EPWM_XCMP8_SHADOW1
XCMP8_SHADOW1.
Definition: etpwm.h:2102
#define EPWM_DB_INPUT_EPWMB
Input signal is ePWMB.
Definition: etpwm.h:782
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_XCMP5
Time base counter equals XCMP5.
Definition: etpwm.h:2212
@ EPWM_SOC_TBCTR_U_CMPA
time-base counter equal to CMPA when the timer is incrementing
Definition: etpwm.h:1278
@ EPWM_LINK_WITH_EPWM_26
link current ePWM with ePWM26
Definition: etpwm.h:414
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT1
Trip source is INPUTXBAR out1 signal.
Definition: etpwm.h:2346
@ EPWM_DE_TRIP_SRC_CMPSSA6
Trip source is CMPSSA6 signal.
Definition: etpwm.h:2420
@ EPWM_XCMP_5_CMPA
Allocate XCMP1 - XCMP5 registers to CMPA.
Definition: etpwm.h:2240
static void EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags)
Definition: etpwm.h:5627
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT24
Trip source is INPUTXBAR out24 signal.
Definition: etpwm.h:2392
@ EPWM_ACTION_QUALIFIER_B
Action Qualifier B.
Definition: etpwm.h:498
@ HRPWM_XCMP8_ACTIVE
XCMP8_ACTIVE.
Definition: etpwm.h:1985
@ EPWM_DC_MODULE_B
Digital Compare Module B.
Definition: etpwm.h:1453
@ EPWM_DB_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:797
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1
Valley capture trigged by DCAEVT1 (Digital Compare A event 1)
Definition: etpwm.h:1609
@ EPWM_PERIOD_DIRECT_LOAD
PWM Period register access is directly.
Definition: etpwm.h:336
#define EPWM_DCxCTL_STEP
Defines to be used by the driver.
Definition: etpwm.h:2564
EPWM_XCMPReg
Definition: etpwm.h:2067
@ EPWM_LINK_DBFED
link DBFED registers
Definition: etpwm.h:437
@ EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN
T1 event on count down.
Definition: etpwm.h:569
@ HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE
MEP controls both rising and falling edge.
Definition: etpwm.h:1861
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP1
Sync-in source is ECAP1 sync-out signal.
Definition: etpwm.h:254
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:177
EPWM_ActionQualifierModule
Definition: etpwm.h:496
EPWM_ActionQualifierOutputModule
Definition: etpwm.h:714
@ EPWM_LINK_WITH_EPWM_25
link current ePWM with ePWM25
Definition: etpwm.h:413
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT30
Trip source is INPUTXBAR out30 signal.
Definition: etpwm.h:2404
static void EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType)
Definition: etpwm.h:6663
@ EPWM_DC_EVENT_INPUT_NOT_SYNCED
DC input signal is not synced with TBCLK.
Definition: etpwm.h:1496
static void EPWM_setDiodeEmulationMonitorModeStep(uint32_t base, uint32_t direction, uint8_t stepsize)
Definition: etpwm.h:10959
@ EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2
Digital compare event B 2.
Definition: etpwm.h:538
@ HRPWM_XCMP2_SHADOW3
XCMP2_SHADOW3.
Definition: etpwm.h:2030
EPWM_DigitalCompareFilterInput
Definition: etpwm.h:1433
static void EPWM_setXCMPLoadMode(uint32_t base, EPWM_XCMPXloadCtlLoadMode mode)
Definition: etpwm.h:10418
@ EPWM_TZ_DC_OUTPUT_B1
Digital Compare output 1 B.
Definition: etpwm.h:910
@ EPWM_AQ_OUTPUT_LOW_UP_CMPA
Time base counter up equals COMPA and set output pins to low.
Definition: etpwm.h:630
@ EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD
load on sync or when counter equals zero or period
Definition: etpwm.h:522
@ EPWM_LINK_WITH_EPWM_1
link current ePWM with ePWM1
Definition: etpwm.h:389
@ EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2
Valley capture trigged by DCBEVT2 (Digital Compare B event 2)
Definition: etpwm.h:1615
@ EPWM_LINK_WITH_EPWM_4
link current ePWM with ePWM4
Definition: etpwm.h:392
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG0
Sync-in source is FSI-RX2 RX Trigger 0 signal.
Definition: etpwm.h:296
@ EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD
load when counter equals zero or period
Definition: etpwm.h:799
static void EPWM_disableXLoad(uint32_t base)
Definition: etpwm.h:10371
@ EPWM_AQ_OUTPUT_LOW_UP_T2
T2 event on count up and set output pins to low.
Definition: etpwm.h:689
static uint16_t EPWM_getValleyCount(uint32_t base)
Definition: etpwm.h:8339
@ EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3
Trip zone 3.
Definition: etpwm.h:541
static void EPWM_disableDigitalCompareEdgeFilter(uint32_t base)
Definition: etpwm.h:6915
@ EPWM_COUNTER_MODE_DOWN
Down - count mode.
Definition: etpwm.h:348
static void HRPWM_enablePhaseShiftLoad(uint32_t base)
Definition: etpwm.h:9485
@ EPWM_XMAX_SHADOW2
XMAX_SHADOW2.
Definition: etpwm.h:2186
@ EPWM_DE_TRIP_SRC_CMPSSB9
Trip source is CMPSSB9 signal.
Definition: etpwm.h:2446
@ EPWM_SOC_TBCTR_D_CMPD
time-base counter equal to CMPD when the timer is decrementing
Definition: etpwm.h:1292
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM20
Sync-in source is EPWM20 sync-out signal.
Definition: etpwm.h:228
static void EPWM_enableXCMPMode(uint32_t base)
Definition: etpwm.h:10012
static void EPWM_enableCaptureInEvent(uint32_t base)
Definition: etpwm.h:7755
@ EPWM_DIODE_EMULATION_OST
Diode Emulation mode is One Shot.
Definition: etpwm.h:2332
@ HRPWM_CHANNEL_B
HRPWM B.
Definition: etpwm.h:1843
static void EPWM_disableCounterCompareShadowLoadMode(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3484
static void HRPWM_enablePeriodControl(uint32_t base)
Definition: etpwm.h:9442
@ EPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2113
@ EPWM_DE_SYNC_TRIPHorL
synchronized version of TRIPH or TRIPL signal
Definition: etpwm.h:2453
@ EPWM_TZ_ACTION_EVENT_DCBEVT1
DCBEVT1 (Digital Compare B event 1)
Definition: etpwm.h:942
@ EPWM_DC_CBC_LATCH_CLR_ON_CNTR_PERIOD
Clear CBC latch when counter equals period.
Definition: etpwm.h:1524
@ EPWM_GL_LOAD_PULSE_CNTR_ZERO
load when counter is equal to zero
Definition: etpwm.h:1538
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM9
Sync-in source is EPWM9 sync-out signal.
Definition: etpwm.h:206
@ EPWM_DIODE_EMULATION_CBC
Diode Emulation mode is Cycle by Cycle.
Definition: etpwm.h:2330
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT21
Trip source is INPUTXBAR out21 signal.
Definition: etpwm.h:2386
static void EPWM_disableInterrupt(uint32_t base)
Definition: etpwm.h:5803
static void EPWM_disableGlobalLoad(uint32_t base)
Definition: etpwm.h:8403
static void EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input)
Definition: etpwm.h:4517
@ EPWM_XMAX_ACTIVE
XMAX_ACTIVE.
Definition: etpwm.h:2178
#define EPWM_XCMP_SHADOW2
XCMP set = Shadow 3.
Definition: etpwm.h:2056
static void EPWM_selectDigitalCompareCBCLatchClearEvent(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareCBCLatchClearEvent clearEvent)
Definition: etpwm.h:7440
@ HRPWM_COUNTER_COMPARE_B
counter compare B
Definition: etpwm.h:1942
static void HRPWM_setCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule, uint32_t compCount)
Definition: etpwm.h:9612
static void EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, uint16_t stopCount)
Definition: etpwm.h:8179
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT4
Sync-in source is Input XBAR out4 signal.
Definition: etpwm.h:272
@ EPWM_XCMP6_SHADOW2
XCMP6_SHADOW2.
Definition: etpwm.h:2117
static void EPWM_disableChopper(uint32_t base)
Definition: etpwm.h:4878
static void EPWM_setActionQualifierContSWForceAction_opt_outputs(uint32_t base, uint8_t outputAB)
Definition: etpwm.h:4272
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX2_RX_TRIG3
Sync-in source is FSI-RX2 RX Trigger 3 signal.
Definition: etpwm.h:302
static void EPWM_disableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7342
@ EPWM_LINK_COMP_C
link COMPC registers
Definition: etpwm.h:433
static void EPWM_disableDigitalCompareADCTrigger(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7280
@ HRPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2002
@ EPWM_COMP_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:471
@ EPWM_HSCLOCK_DIVIDER_4
Divide clock by 4.
Definition: etpwm.h:169
@ EPWM_XCMP_3_CMPB
Allocate XCMP5 - XCMP7 registers to CMPB.
Definition: etpwm.h:2262
@ HRPWM_DB_MEP_CTRL_FED
MEP controls Falling Edge Delay.
Definition: etpwm.h:1958
static uint16_t EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule)
Definition: etpwm.h:3665
static void EPWM_bypassDiodeEmulationLogic(uint32_t base)
Definition: etpwm.h:10837
static void EPWM_startOneShotSync(uint32_t base)
Definition: etpwm.h:3077
@ EPWM_AQ_OUTPUT_LOW_ZERO
Time base counter equals zero and set output pins to low.
Definition: etpwm.h:614
#define EPWM_MINDB_BLOCK_B
Definition: etpwm.h:1725
static void HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal)
Definition: etpwm.h:9577
@ HRPWM_XCMP4_SHADOW2
XCMP4_SHADOW2.
Definition: etpwm.h:2015
@ EPWM_XTBPRD_ACTIVE
XTBPRD_ACTIVE.
Definition: etpwm.h:2085
EPWM_PeriodShadowLoadMode
Definition: etpwm.h:360
#define EPWM_DE_TRIPL
Values that can be passed to EPWM_configureDiodeEmulationTripSources()
Definition: etpwm.h:2490
static void EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister)
Definition: etpwm.h:8626
@ EPWM_AQ_OUTPUT_HIGH_PERIOD
Time base counter equals period and set output pins to high.
Definition: etpwm.h:624
@ EPWM_CLOCK_DIVIDER_128
Divide clock by 128.
Definition: etpwm.h:156
EPWM_CounterCompareLoadMode
Definition: etpwm.h:467
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM6
Sync-in source is EPWM6 sync-out signal.
Definition: etpwm.h:200
@ EPWM_TZ_ACTION_EVENT_TZA
TZ1 - TZ6, DCAEVT2, DCAEVT1.
Definition: etpwm.h:938
static void HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent)
Definition: etpwm.h:9923
static void EPWM_setDigitalCompareEventSource(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent, EPWM_DigitalCompareEventSource dcEventSource)
Definition: etpwm.h:7149
@ HRPWM_XTBPRD_SHADOW3
XTBPRD_SHADOW3.
Definition: etpwm.h:2044
@ EPWM_XCMP6_SHADOW1
XCMP6_SHADOW1.
Definition: etpwm.h:2098
@ EPWM_AQ_LOAD_ON_CNTR_PERIOD
load when counter equals period
Definition: etpwm.h:512
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM7
Sync-in source is EPWM7 sync-out signal.
Definition: etpwm.h:202
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_ECAP3
Sync-in source is ECAP3 sync-out signal.
Definition: etpwm.h:258
static void EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt)
Definition: etpwm.h:5425
@ EPWM_DC_WINDOW_START_TBCTR_BLANK_PULSE_MIX
Time base counter blank pulse mix.
Definition: etpwm.h:1396
EPWM_DeadBandClockMode
Definition: etpwm.h:847
@ EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2
Valley capture trigged by DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:1611
EPWM_XCMPXloadCtlLoadMode
Definition: etpwm.h:2274
@ EPWM_XCMP4_ACTIVE
XCMP4_ACTIVE.
Definition: etpwm.h:2075
static void EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent)
Definition: etpwm.h:5699
static void EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount)
Definition: etpwm.h:6069
@ HRPWM_PWMSYNC_SOURCE_PERIOD
Counter equals Period.
Definition: etpwm.h:1920
@ EPWM_SYNC_IN_PULSE_SRC_FSIRX3_RX_TRIG3
Sync-in source is FSI-RX3 RX Trigger 3 signal.
Definition: etpwm.h:310
static uint16_t HRPWM_getHiResTimeBasePeriod(uint32_t base)
Definition: etpwm.h:9206
@ EPWM_GL_LOAD_PULSE_CNTR_CMPC_D
load when counter is equal to cmpc and cmpc is decrementing
Definition: etpwm.h:1554
#define EPWM_DE_COUNT_DOWN
Definition: etpwm.h:2481
@ EPWM_XMAX_SHADOW3
XMAX_SHADOW3.
Definition: etpwm.h:2190
@ EPWM_TZ_ACTION_EVENT_DCAEVT2
DCAEVT2 (Digital Compare A event 2)
Definition: etpwm.h:941
static void EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource, uint16_t mixedSource)
Definition: etpwm.h:5839
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM2
Sync-in source is EPWM2 sync-out signal.
Definition: etpwm.h:192
@ EPWM_DC_TYPE_DCBH
Digital Compare B High.
Definition: etpwm.h:1310
static void EPWM_enableDigitalCompareSyncEvent(uint32_t base, EPWM_DigitalCompareModule dcModule)
Definition: etpwm.h:7311
static void EPWM_clearSyncEvent(uint32_t base)
Definition: etpwm.h:3185
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_2
SHDW2, SHDW1 and Active registers are available.
Definition: etpwm.h:2295
@ EPWM_EMULATION_FREE_RUN
Free run.
Definition: etpwm.h:126
static bool EPWM_getDigitalCompareCBCLatchStatus(uint32_t base, EPWM_DigitalCompareModule dcModule, EPWM_DigitalCompareEvent dcEvent)
Definition: etpwm.h:7492
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM22
Sync-in source is EPWM22 sync-out signal.
Definition: etpwm.h:232
static void EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, EPWM_DigitalCompareEdgeFilterEdgeCount edgeCount)
Definition: etpwm.h:6976
@ EPWM_XCMP_XLOADCTL_SHDWLEVEL_1
SHDW1 and Active registers are available.
Definition: etpwm.h:2293
@ EPWM_AQ_LOAD_FREEZE
Freeze shadow to active load.
Definition: etpwm.h:516
@ EPWM_XCMP7_ACTIVE
XCMP7_ACTIVE.
Definition: etpwm.h:2081
@ EPWM_DC_TRIP_TRIPIN5
Trip 5.
Definition: etpwm.h:1327
@ HRPWM_PWMSYNC_SOURCE_COMPC_UP
Counter equals COMPC when counting up.
Definition: etpwm.h:1924
@ EPWM_VALLEY_DELAY_MODE_SW_DELAY
Delay value equals the offset value defines by software.
Definition: etpwm.h:1639
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT10
Trip source is INPUTXBAR out10 signal.
Definition: etpwm.h:2364
@ EPWM_XTBPRD_SHADOW2
XTBPRD_SHADOW2.
Definition: etpwm.h:2123
@ EPWM_XCMP2_SHADOW2
XCMP2_SHADOW2.
Definition: etpwm.h:2109
@ EPWM_DE_TRIP_SRC_INPUTXBAR_OUT27
Trip source is INPUTXBAR out27 signal.
Definition: etpwm.h:2398
@ EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA
Time base counter up equals COMPA.
Definition: etpwm.h:559
@ EPWM_XCMP7_SHADOW1
XCMP7_SHADOW1.
Definition: etpwm.h:2100
@ EPWM_XCMP5_ACTIVE
XCMP5_ACTIVE.
Definition: etpwm.h:2077
static void EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount)
Definition: etpwm.h:3261
@ HRPWM_CHANNEL_A
HRPWM A.
Definition: etpwm.h:1842
@ EPWM_DB_COUNTER_CLOCK_FULL_CYCLE
Dead band counter runs at TBCLK rate.
Definition: etpwm.h:849
@ EPWM_SYNC_IN_PULSE_SRC_INPUTXBAR_OUT20
Sync-in source is Input XBAR out20 signal.
Definition: etpwm.h:274
@ EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM29
Sync-in source is EPWM29 sync-out signal.
Definition: etpwm.h:246
EPWM_XCMP_XLOADCTL_SHDWBUFPTR
Definition: etpwm.h:2308
@ EPWM_DC_WINDOW_SOURCE_DCAEVT2
DC filter signal source is DCAEVT2.
Definition: etpwm.h:1435
@ EPWM_LINK_WITH_EPWM_31
link current ePWM with ePWM31
Definition: etpwm.h:419
static uint32_t HRPWM_getCounterCompareValue(uint32_t base, HRPWM_CounterCompareModule compModule)
Definition: etpwm.h:9658
@ EPWM_DC_TRIP_TRIPIN1
Trip 1.
Definition: etpwm.h:1323
@ EPWM_DB_LOAD_ON_CNTR_ZERO
load when counter equals zero
Definition: etpwm.h:795
@ EPWM_TZ_DC_OUTPUT_A1
Digital Compare output 1 A.
Definition: etpwm.h:908
@ EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB
Time base counter down equals COMPB and set output pins to high.
Definition: etpwm.h:656