gpmc.h

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/*
 *  Copyright (C) 2023 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef _GPMC__H_
#define _GPMC__H_
 
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <kernel/dpl/SystemP.h>
#include <kernel/dpl/SemaphoreP.h>
#include <kernel/dpl/HwiP.h>
#include <drivers/hw_include/csl_types.h>
#include <drivers/hw_include/cslr_gpmc.h>
#include <kernel/dpl/CacheP.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
#define GPMC_CHIP_SELECT_CS0                            (0U)
#define GPMC_CHIP_SELECT_CS1                            (1U)
#define GPMC_CHIP_SELECT_CS2                            (2U)
#define GPMC_CHIP_SELECT_CS3                            (3U)
 
#define GPMC_FIFOEVENT_STATUS                         (0U)
#define GPMC_TERMINALCOUNT_STATUS                     (1U)
#define GPMC_WAIT0EDGEDETECTION_STATUS                (2U)
#define GPMC_WAIT1EDGEDETECTION_STATUS                (3U)
 
#define GPMC_FIFOEVENT_INT                            (0U)
#define GPMC_TERMINALCOUNT_INT                        (1U)
#define GPMC_WAIT0EDGEDETECTION_INT                   (2U)
#define GPMC_WAIT1EDGEDETECTION_INT                   (3U)
 
#define GPMC_PREFETCH_ACCESSMODE_READ                 (0U)
#define GPMC_PREFETCH_ACCESSMODE_WRITE                (1U)
 
#define GPMC_ECC_ALGORITHM_HAMMINGCODE                (0U)
#define GPMC_ECC_ALGORITHM_BCH                        (1U)
 
#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_4BITS            (0U)
#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_8BITS            (1U)
#define GPMC_ECC_BCH_ERRCORRCAP_UPTO_16BITS           (2U)
 
#define GPMC_ECCPOINTER_RESULT_1                      (1U)
#define GPMC_ECCPOINTER_RESULT_2                      (2U)
#define GPMC_ECCPOINTER_RESULT_3                      (3U)
#define GPMC_ECCPOINTER_RESULT_4                      (4U)
#define GPMC_ECCPOINTER_RESULT_5                      (5U)
#define GPMC_ECCPOINTER_RESULT_6                      (6U)
#define GPMC_ECCPOINTER_RESULT_7                      (7U)
#define GPMC_ECCPOINTER_RESULT_8                      (8U)
#define GPMC_ECCPOINTER_RESULT_9                      (9U)
 
#define GPMC_ECC_SIZE_0                               (0U)
#define GPMC_ECC_SIZE_1                               (1U)
 
#define GPMC_ECC_RESULT_1                             (1U)
#define GPMC_ECC_RESULT_2                             (2U)
#define GPMC_ECC_RESULT_3                             (3U)
#define GPMC_ECC_RESULT_4                             (4U)
#define GPMC_ECC_RESULT_5                             (5U)
#define GPMC_ECC_RESULT_6                             (6U)
#define GPMC_ECC_RESULT_7                             (7U)
#define GPMC_ECC_RESULT_8                             (8U)
#define GPMC_ECC_RESULT_9                             (9U)
 
#define GPMC_BCH_RESULT0                             (0U)
#define GPMC_BCH_RESULT1                             (1U)
#define GPMC_BCH_RESULT2                             (2U)
#define GPMC_BCH_RESULT3                             (3U)
#define GPMC_BCH_RESULT4                             (4U)
#define GPMC_BCH_RESULT5                             (5U)
#define GPMC_BCH_RESULT6                             (6U)
 
#define GPMC_CS_MASK_ADDR_SIZE_256MB                            (0x00U)
#define GPMC_CS_MASK_ADDR_SIZE_128MB                            (0x08U)
#define GPMC_CS_MASK_ADDR_SIZE_64MB                             (0x0cU)
#define GPMC_CS_MASK_ADDR_SIZE_32MB                             (0x0eU)
#define GPMC_CS_MASK_ADDR_SIZE_16MB                             (0x0fU)
 
#define GPMC_CS_TIMING_CONFIG(CSWrOffTime, CSRdOffTime, CSExtDelayFlag, \
                              CSOnTime)                                 \
    ((uint32_t) (((CSWrOffTime) << CSL_GPMC_CONFIG2_CSWROFFTIME_SHIFT)    \
                 & CSL_GPMC_CONFIG2_CSWROFFTIME_MASK) |                   \
     (((CSRdOffTime) << CSL_GPMC_CONFIG2_CSRDOFFTIME_SHIFT)               \
      & CSL_GPMC_CONFIG2_CSRDOFFTIME_MASK) |                              \
     (((CSExtDelayFlag) << CSL_GPMC_CONFIG2_CSEXTRADELAY_SHIFT)           \
      & CSL_GPMC_CONFIG2_CSEXTRADELAY_MASK) |                             \
     (((CSOnTime) << CSL_GPMC_CONFIG2_CSONTIME_SHIFT)                     \
      & CSL_GPMC_CONFIG2_CSONTIME_MASK))
 
 
#define GPMC_ADV_TIMING_CONFIG(ADVAADMuxWrOffTime, ADVAADMuxRdOffTime,      \
                               ADVWrOffTime, ADVRdOffTime, ADVExtDelayFlag, \
                               ADVAADMuxOnTime,                             \
                               ADVOnTime)                                   \
    ((uint32_t) (((ADVAADMuxWrOffTime) <<                                   \
                  CSL_GPMC_CONFIG3_ADVAADMUXWROFFTIME_SHIFT) &                \
                 CSL_GPMC_CONFIG3_ADVAADMUXWROFFTIME_MASK) |                  \
     (((ADVAADMuxRdOffTime) << CSL_GPMC_CONFIG3_ADVAADMUXRDOFFTIME_SHIFT) &   \
      CSL_GPMC_CONFIG3_ADVAADMUXRDOFFTIME_MASK) |                             \
     (((ADVWrOffTime) << CSL_GPMC_CONFIG3_ADVWROFFTIME_SHIFT) &               \
      CSL_GPMC_CONFIG3_ADVWROFFTIME_MASK) |                                   \
     (((ADVRdOffTime) << CSL_GPMC_CONFIG3_ADVRDOFFTIME_SHIFT) &               \
      CSL_GPMC_CONFIG3_ADVRDOFFTIME_MASK) |                                   \
     (((ADVExtDelayFlag) << CSL_GPMC_CONFIG3_ADVEXTRADELAY_SHIFT) &           \
      CSL_GPMC_CONFIG3_ADVEXTRADELAY_MASK) |                                  \
     (((ADVAADMuxOnTime) << CSL_GPMC_CONFIG3_ADVAADMUXONTIME_SHIFT) &         \
      CSL_GPMC_CONFIG3_ADVAADMUXONTIME_MASK) |                                \
     (((ADVOnTime) << CSL_GPMC_CONFIG3_ADVONTIME_SHIFT) &                     \
      CSL_GPMC_CONFIG3_ADVONTIME_MASK))
 
 
#define GPMC_WE_OE_TIMING_CONFIG(WEOffTime, WEExtDelayFlag, WEOnTime,           \
                                 OEAADMuxOffTime, OEOffTime, OEExtDelayFlag,    \
                                 OEAADMuxOnTime, OEOnTime)                      \
    ((uint32_t) (((WEOffTime) <<                                                \
                  CSL_GPMC_CONFIG4_WEOFFTIME_SHIFT) &                             \
                 CSL_GPMC_CONFIG4_WEOFFTIME_MASK) |                               \
     (((WEExtDelayFlag) <<                                                      \
       CSL_GPMC_CONFIG4_WEEXTRADELAY_SHIFT) & CSL_GPMC_CONFIG4_WEEXTRADELAY_MASK) | \
     (((WEOnTime) <<                                                            \
       CSL_GPMC_CONFIG4_WEONTIME_SHIFT) & CSL_GPMC_CONFIG4_WEONTIME_MASK) |         \
     (((OEAADMuxOffTime) <<                                                     \
       CSL_GPMC_CONFIG4_OEAADMUXOFFTIME_SHIFT) &                                  \
      CSL_GPMC_CONFIG4_OEAADMUXOFFTIME_MASK) |                                    \
     (((OEOffTime) <<                                                           \
       CSL_GPMC_CONFIG4_OEOFFTIME_SHIFT) & CSL_GPMC_CONFIG4_OEOFFTIME_MASK) |       \
     (((OEExtDelayFlag) <<                                                      \
       CSL_GPMC_CONFIG4_OEEXTRADELAY_SHIFT) & CSL_GPMC_CONFIG4_OEEXTRADELAY_MASK) | \
     (((OEAADMuxOnTime) <<                                                      \
       CSL_GPMC_CONFIG4_OEAADMUXONTIME_SHIFT) &                                   \
      CSL_GPMC_CONFIG4_OEAADMUXONTIME_MASK) |                                     \
     (((OEOnTime) <<                                                            \
       CSL_GPMC_CONFIG4_OEONTIME_SHIFT) & CSL_GPMC_CONFIG4_OEONTIME_MASK))
 
 
 
#define GPMC_RDACCESS_CYCLETIME_TIMING_CONFIG(rdCycleTime, wrCycleTime,         \
                                              rdAccessTime,                     \
                                              pageBurstAccessTime)              \
    ((uint32_t) (((rdCycleTime) <<                                              \
                  CSL_GPMC_CONFIG5_RDCYCLETIME_SHIFT) &                           \
                 CSL_GPMC_CONFIG5_RDCYCLETIME_MASK) |                             \
     (((wrCycleTime) <<                                                         \
       CSL_GPMC_CONFIG5_WRCYCLETIME_SHIFT) & CSL_GPMC_CONFIG5_WRCYCLETIME_MASK) |   \
     (((rdAccessTime) <<                                                        \
       CSL_GPMC_CONFIG5_RDACCESSTIME_SHIFT) & CSL_GPMC_CONFIG5_RDACCESSTIME_MASK) | \
     (((pageBurstAccessTime) <<                                                 \
       CSL_GPMC_CONFIG5_PAGEBURSTACCESSTIME_SHIFT) &                              \
      CSL_GPMC_CONFIG5_PAGEBURSTACCESSTIME_MASK))
 
 
 
#define GPMC_CYCLE2CYCLE_BUSTURNAROUND_TIMING_CONFIG(cycle2CycleDelay,          \
                                                     cycle2CycleDelaySameCSCfg, \
                                                     cycle2CycleDelayDiffCSCfg, \
                                                     busTAtime)                 \
    ((uint32_t) (((cycle2CycleDelay) <<                                         \
                  CSL_GPMC_CONFIG6_CYCLE2CYCLEDELAY_SHIFT) &                      \
                 CSL_GPMC_CONFIG6_CYCLE2CYCLEDELAY_MASK) |                        \
     (((cycle2CycleDelaySameCSCfg) <<                                           \
       CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_SHIFT) &                              \
      CSL_GPMC_CONFIG6_CYCLE2CYCLESAMECSEN_MASK) |                                \
     (((cycle2CycleDelayDiffCSCfg) <<                                           \
       CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_SHIFT) &                              \
      CSL_GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN_MASK) |                                \
     (((busTAtime) <<                                                           \
       CSL_GPMC_CONFIG6_BUSTURNAROUND_SHIFT) & CSL_GPMC_CONFIG6_BUSTURNAROUND_MASK))
 
 
 
#define GPMC_NAND_CS_ON_TIME                0U
 
#define GPMC_NAND_WE_ON_TIME                0U
 
#define GPMC_NAND_ADV_ON_TIME               0U
 
#define GPMC_NAND_CS_WR_OFF_TIME            6U
 
#define GPMC_NAND_WR_CYCLE_TIME             6U
 
#define GPMC_NAND_ADV_WR_OFF_TIME           4U
 
#define GPMC_NAND_CS_RD_OFF_TIME            6U
 
#define GPMC_NAND_RD_CYCLE_TIME             6U
 
#define GPMC_NAND_ADV_AADMUX_ON_TIME        0U
 
#define GPMC_NAND_ADV_AADMUX_RD_OFF_TIME    0U
 
#define GPMC_NAND_ADV_AADMUX_WR_OFF_TIME    0U
 
#define GPMC_NAND_PAGEBURST_ACCESS_TIME     0U
 
#define GPMC_NAND_OE_ON_TIME                1U
 
#define GPMC_NAND_OE_OFF_TIME               4U
 
#define GPMC_NAND_OE_AADMUX_ON_TIME         0U
 
#define GPMC_NAND_OE_AADMUX_OFF_TIME        0U
 
#define GPMC_NAND_ADV_RD_OFF_TIME           4U
 
#define GPMC_NAND_WE_OFF_TIME               3U
 
#define GPMC_NAND_RD_ACCESS_TIME            4U
 
#define GPMC_NAND_C2C_DELAY                 0U
 
#define GPMC_NAND_ADMUX_DATA_VALID          0U
 
#define GPMC_NAND_WR_ACCESS_TIME            6U
 
#define GPMC_NAND_BRST_TAROUND_TIME         0U
 
#define GPMC_PSRAM_CS_ON_TIME                3U
 
#define GPMC_PSRAM_WE_ON_TIME                10U
 
#define GPMC_PSRAM_ADV_ON_TIME               1U
 
#define GPMC_PSRAM_CS_WR_OFF_TIME            21U
 
#define GPMC_PSRAM_WR_CYCLE_TIME             23U
 
#define GPMC_PSRAM_ADV_WR_OFF_TIME           3U
 
#define GPMC_PSRAM_CS_RD_OFF_TIME            21U
 
#define GPMC_PSRAM_RD_CYCLE_TIME             23U
 
#define GPMC_PSRAM_ADV_AADMUX_ON_TIME        1U
 
#define GPMC_PSRAM_ADV_AADMUX_RD_OFF_TIME    2U
 
#define GPMC_PSRAM_ADV_AADMUX_WR_OFF_TIME    2U
 
#define GPMC_PSRAM_PAGEBURST_ACCESS_TIME     3U
 
#define GPMC_PSRAM_OE_ON_TIME                10U
 
#define GPMC_PSRAM_OE_OFF_TIME               1U
 
#define GPMC_PSRAM_OE_AADMUX_ON_TIME         1U
 
#define GPMC_PSRAM_OE_AADMUX_OFF_TIME        15U
 
#define GPMC_PSRAM_ADV_RD_OFF_TIME           3U
 
#define GPMC_PSRAM_WE_OFF_TIME               16U
 
#define GPMC_PSRAM_RD_ACCESS_TIME            16U
 
#define GPMC_PSRAM_C2C_DELAY                 0U
 
#define GPMC_PSRAM_ADMUX_DATA_VALID          0U
 
#define GPMC_PSRAM_WR_ACCESS_TIME            8U
 
#define GPMC_PSRAM_BRST_TAROUND_TIME         1U
 
#define GPMC_DMA_COPY_LOWER_LIMIT                   (512U)
 
#define GPMC_CS_BASE_ADDR_SHIFT                      (24U)
 
#define GPMC_ECC_WRAP_MODE1                          (1)
 
#define GPMC_CMD_INVALID                             (0xFFFFFFFFU)
 
#define GPMC_MEM_TYPE_NAND                           (0)
#define GPMC_MEM_TYPE_PSRAM                          (1)
 
typedef void* GPMC_Handle;
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
typedef enum GPMC_v1_nandEccAlgo_s
{
    GPMC_NAND_ECC_ALGO_NONE  = 0x00U,
    GPMC_NAND_ECC_ALGO_HAMMING_1BIT,
    GPMC_NAND_ECC_ALGO_BCH_4BIT,
    GPMC_NAND_ECC_ALGO_BCH_8BIT,
    GPMC_NAND_ECC_ALGO_BCH_16BIT
 
} GPMC_nandEccAlgo;
 
typedef enum GPMC_OperatingMode_s {
 
    GPMC_OPERATING_MODE_BLOCKING = 0,
    GPMC_OPERATING_MODE_CALLBACK,
    GPMC_OPERATING_MODE_POLLING
} GPMC_OperatingMode;
 
typedef enum GPMC_TransferMode_s {
 
    GPMC_TRANSFER_MODE_BLOCKING = 0,
    GPMC_TRANSFER_MODE_CALLBACK,
} GPMC_TransferMode;
 
typedef enum GPMC_TransactionType_e {
    GPMC_TRANSACTION_TYPE_READ = 0,
    GPMC_TRANSACTION_TYPE_WRITE,
    GPMC_TRANSACTION_TYPE_READ_CMDREG,
    GPMC_TRANSACTION_TYPE_WRITE_CMDREG
} GPMC_TransactionType;
 
typedef enum GPMC_TransactionStatus_s {
    GPMC_TRANSFER_COMPLETED = 0,
    GPMC_TRANSFER_STARTED,
    GPMC_TRANSFER_CANCELED,
    GPMC_TRANSFER_FAILED,
    GPMC_TRANSFER_CSN_DEASSERT,
    GPMC_TRANSFER_TIMEOUT,
} GPMC_TransactionStatus;
 
 
typedef struct
{
    uint32_t cmdCycle1;
    uint32_t cmdCycle2;
    uint32_t rowAddress;
    uint32_t numRowAddrCycles;
    uint32_t colAddress;
    uint32_t numColAddrCycles;
    uint32_t waitTimeout;
    uint32_t checkReadypin;
} GPMC_nandCmdParams;
 
 
typedef struct GPMC_Transaction_s {
 
    GPMC_TransactionType    transType;
    uint32_t                count;
    void                    *Buf;
    void                    *arg;
    uint32_t                transferTimeout;
    GPMC_TransactionStatus status;
} GPMC_Transaction;
 
typedef void (*GPMC_CallbackFxn)(GPMC_Handle handle,
                                 GPMC_Transaction * transaction);
 
 
typedef struct GPMC_Params_s
{
    int32_t                 gpmcDmaChIndex;
    uint32_t                devType;
    uint32_t                devSize;
    uint32_t                chipSel;
    uint32_t                intrEnable;
 
    uint32_t                dmaEnable;
    GPMC_TransferMode       transferMode;
    GPMC_CallbackFxn        transferCallBckFunc;
    uint32_t                memDevice;
} GPMC_Params;
 
typedef struct
{
    uint32_t regionStartAddr;
    uint32_t regionSize;
} GPMC_AddrRegion;
 
typedef struct GPMC_Object_s {
 
    GPMC_Handle                     handle;
    GPMC_CallbackFxn                transferCallbackFxn;
    GPMC_Params                     params;
    GPMC_OperatingMode              operMode;
    /*
     * State variables
     */
    uint32_t                        isOpen;
    HwiP_Object                     hwi;
    SemaphoreP_Object               mutex;
    SemaphoreP_Object               transferComplete;
    GPMC_Transaction                *transaction;
    void* gpmcDmaHandle;
} GPMC_Object;
 
typedef struct GPMC_timingParams_s
{
    uint32_t    csOnTime;
    /* Chip Select assertion time. */
    uint32_t    csRdOffTime;
    uint32_t    csWrOffTime;
    uint32_t    advOnTime;
    uint32_t    advRdOffTime;
    uint32_t    advWrOffTime;
    uint32_t    advAadMuxOnTime;
    uint32_t    advAadMuxRdOffTime;
    uint32_t    advAadMuxWrOffTime;
    uint32_t    weOnTtime;
    uint32_t    weOffTime;
    uint32_t    oeOnTime;
    uint32_t    oeOffTime;
    uint32_t    oeAadMuxOnTime;
    uint32_t    oeAadMuxOffTime;
    uint32_t    pageBurstAccess;
    uint32_t    rdAccessTime;
    uint32_t    wrAcessTime;
    uint32_t    rdCycleTime;
    uint32_t    wrCycleTime;
    uint32_t    wrDataOnMuxBusTime;
    uint32_t    cycle2CycleDelay;
    uint32_t    cycleDelaySameChipSel;
    uint32_t    cycleDelayDiffChipSel;
    uint32_t    busTurnAroundTime;
} GPMC_timingParams;
 
typedef struct GPMC_HwAttrs_s
{
 
    uint32_t                gpmcBaseAddr;
    uint32_t                dataBaseAddr;
    uint32_t                elmBaseAddr;
    uint32_t                inputClkFreq;
    uint32_t                intrNum;
    uint32_t                intrPriority;
    uint32_t                clkDivider;
    uint32_t                addrDataMux;
    uint32_t                timeLatency;
    uint32_t                chipSelBaseAddr;
    uint32_t                chipSelAddrSize;
    uint32_t                waitPinNum;
    uint32_t                waitPinPol;
    GPMC_timingParams       timingParams;
    GPMC_nandEccAlgo        eccAlgo;
    uint32_t                readType;
    uint32_t                writeType;
    uint32_t                csExDelay;
    uint32_t                accessType;
    const GPMC_AddrRegion   *dmaRestrictedRegions;
} GPMC_HwAttrs;
 
typedef struct GPMC_Config_s {
 
    const GPMC_HwAttrs * attrs;
    GPMC_Object *object;
} GPMC_Config;
 
 
extern GPMC_Config gGpmcConfig[];
extern uint32_t gGpmcConfigNum;
 
/* ========================================================================== */
/*                       Function Declarations                                */
/* ========================================================================== */
static inline void GPMC_Params_init(GPMC_Params *params);
 
void GPMC_init(void);
void GPMC_deinit(void);
 
GPMC_Handle GPMC_open(uint32_t index, const GPMC_Params *prms);
 
void GPMC_close(GPMC_Handle handle);
 
uint32_t GPMC_getInputClk(GPMC_Handle handle);
 
GPMC_Handle GPMC_getHandle(uint32_t driverInstanceIndex);
 
void GPMC_writeNandCommandParamsInit(GPMC_nandCmdParams *cmdParams);
 
int32_t GPMC_writeNandCommand(GPMC_Handle handle, GPMC_nandCmdParams *cmdParams);
 
void GPMC_transactionInit(GPMC_Transaction *trans);
 
int32_t GPMC_nandReadData(GPMC_Handle handle, GPMC_Transaction *trans);
 
int32_t GPMC_nandWriteData(GPMC_Handle handle, GPMC_Transaction *trans);
 
int32_t GPMC_setDeviceSize(GPMC_Handle handle);
 
int32_t GPMC_setDeviceType(GPMC_Handle handle);
 
int32_t GPMC_configureTimingParameters(GPMC_Handle handle);
 
int32_t GPMC_configureTimingParametersPsram(GPMC_Handle handle);
 
int32_t GPMC_eccValueSizeSet(GPMC_Handle handle, uint32_t eccSize, uint32_t eccSizeVal);
 
int32_t GPMC_eccBchConfigureElm(GPMC_Handle handle, uint8_t numSectors);
 
int32_t GPMC_eccEngineBCHConfig (GPMC_Handle handle, uint32_t eccSteps);
 
int32_t GPMC_eccEngineEnable(GPMC_Handle handle);
 
void GPMC_eccResultRegisterClear(GPMC_Handle handle);
 
int32_t GPMC_eccBchFillSyndromeValue(GPMC_Handle handle, uint32_t sector, uint32_t *bchData);
 
int32_t GPMC_eccBchStartErrorProcessing(GPMC_Handle handle, uint8_t sector);
 
int32_t GPMC_eccBchCheckErrorProcessingStatus(GPMC_Handle handle, uint32_t sector);
 
int32_t GPMC_eccBchSectorGetError(GPMC_Handle handle, uint32_t sector, uint32_t *errCount, uint32_t *errLoc);
 
int32_t GPMC_eccCalculateBchSyndromePolynomial(GPMC_Handle handle, uint8_t *pEccdata, uint32_t sector);
 
int32_t GPMC_eccGetBchSyndromePolynomial(GPMC_Handle handle, uint32_t sector, uint32_t *bchData);
 
int32_t GPMC_configurePrefetchPostWriteEngine(GPMC_Handle handle);
 
int32_t GPMC_disableFlashWriteProtect(GPMC_Handle handle);
 
int32_t GPMC_enableFlashWriteProtect(GPMC_Handle handle);
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
static inline void GPMC_Params_init(GPMC_Params *params)
{
    if (params != NULL)
    {
        params->dmaEnable = FALSE;
        params->intrEnable = FALSE;
        params->chipSel = 0;
        params->devType = CSL_GPMC_CONFIG1_DEVICETYPE_NANDLIKE;
        params->devType = CSL_GPMC_CONFIG1_DEVICESIZE_EIGHTBITS;
        params->gpmcDmaChIndex = -1;
        params->transferMode = GPMC_TRANSFER_MODE_BLOCKING;
        params->transferCallBckFunc = NULL;
    }
}
 
#ifdef __cplusplus
}
#endif
 
#endif  /* _GPMC__H_ */