PRU ICSS EtherCAT Release Notes¶
Updated : April 2020
Overview¶
The PRU-ICSS EtherCAT package provides the foundation that facilitate application software development for EtherCAT Slave on TI Sitara Embedded Processors with PRU-ICSS HW IP
Licensing¶
Please refer to the software manifest, which outlines the licensing status for all packages included in this release. The manifest can be found on the SDK download page or in the installed directory as indicated below.
Standard Compliance¶
Compliant to ETG.1000 V1.0.2 Spec
Documentation¶
- Software Developer Guide: Provides information on features, functions, delivery package and, compile tools for the release. This also provides detailed information regarding software elements and software infrastructure to allow developers to start creating applications.
- Getting Started Guide: provides information on getting the software and running basic examples/demonstrations bundled in the package.
- User Guide: Provides basic information on the applications
- **Software Manifest**: Provides license information on software included in the package. This document is in the release at the root directory of the package
- EVM Quick Start Guide: Provides information on hardware setup and running the demonstration application that is loaded on flash. This document is provided as part of the EVM kit.
Release 01.00.08¶
Released April 2020
System Requirements¶
What’s New¶
- PRU-ICSS EtherCAT Slave Software (100M MII) support on R5F for AM654x SoC
- Baremetal Support for AM335x and AMIC110
- Bug Fixes
Features Supported¶
- EtherCAT Slave Controller
- All EtherCAT Commands (NOP, APRD, APWR, APRW, FPRD, FPWR, FPRW, BRD, BWR, BRW, LRD, LWR, LRW, ARMW and FRMW)
- 8 FMMU support
- 8 SM support
- 8KB (AM335x, AMIC11x) / 28KB (AM437x, AMIC12x, AM57xx) / 59KB (AM654x) of Process Data RAM
- Distributed clocks
- 64-bit DC
- SYNC0 out generation single shot and cyclic mode support
- SYNC1 out generation - SYNC1 cycle time multiple of SYNC0 cycle time
- Latch0 and Latch1 inputs
- System Time PDI control
- DL Loop Control
- Using MII_RX_LINK (fast - depending on PHY link loss detection latency) – mandatory for cable redundancy support
- Using PRU-ICSS MDIO state machine – not recommended for cable redundancy support
- Interrupts – AL/ECAT events
- SYNC0, SYNC1 and PDI interrupt events on external SOC pins
- Watchdog – PDI and SM
- Error Counters
- RX Invalid Frame Counter Port 0/1
- RX ERR Counter Port 0/1
- Forwarded Error Counter Port 0/1
- ECAT Processing Unit Error Counter
- LED – Run, Error and Port0/1 activity based on firmware feedback
- Controlled via GPIO from Host CPU or PHY directly
- EEPROM Emulation
- QSPI flash non-volatile storage support
- Management Interface for PHY over EtherCAT
- PHY address configuration and host side PRU-ICSS MDIO API for PHY programming
- Cable redundancy support
- Beckhoff EtherCAT Slave Stack Code (SSC) Version 5.12 based evaluation library and example
- PRU-ICSS EtherCAT TI-ESC SPI Slave mode on AMIC11x and AMIC12x SoC with on chip memory execution support(without DDR)
What is not supported¶
- In general, peripherals or features not mentioned as part of “Features Supported” section are not supported in this release.
- EtherCAT Slave Controller
- ECAT side register protection when using LRD command
- APRW/FPRW/BRW for SM mapped area
- EtherCAT G
PRU-ICSS Firmware Revision¶
| Platform | Build | Firmware Header location |
|---|---|---|
| AM335x, AMIC11x | 1.4.239 | protocols\ethercat_slave\firmware\v1.0 |
| AM437x | 2.4.239 | protocols\ethercat_slave\firmware\v2.0 |
| AM57xx | 3.4.239 | protocols\ethercat_slave\firmware\v2.1 |
| AM654x | 5.4.239 | protocols\ethercat_slave\firmware\g_v1.0 |
Fixed Issues¶
| Record ID | Platform | Details |
|---|---|---|
| PINDSW-2734 | AM65x AM4x, AM5x | One byte read/write to 0xFFFF fails on AM65x. Fix ESC register corruption on AM4 and AM5 when LWR access made to end of Process Data memory |
| PINDSW-3048 | AM572x | Incorrect usage of pinmux config of AM571x IDK board on AM572x IDK. This issue is fixed. |
| PINDSW-4113 | AMIC11x | ET1100 emulation failure if the read and write PDO size are not equal. |
| PINDSW-3898 | AM335x | 2.5x more DC Sync Jitter seen with Acontis Master and with TwinCAT in DC slave mode. |
| PINDSW-3650 | Sitara | TF-2301_1.3.0 Sync Manager Communication Type Object (0x1C00) Conformance Test Failures |
Known Issues¶
This section contains the list of Known Issues at the time of making the release.
| Record ID | Platform | Details | Workaround |
|---|---|---|---|
| PINDSW-47 | Sitara | Multiple FMMU access in a single datagram to a slave for process data using LRD/LWR commands | Use LRW instead of LRD/LWR |
| PINDSW-72 | Sitara | PDI/PD watchdog counter incremented by 1 whenever PDI/PD watchdog is disabled | None |
| PINDSW-74 | Sitara | LRD access on unused registers increment WKC - no register protection while using LRD | None |
| PINDSW-141 | Sitara | LRW access to non-interleaved input and output process data of multiple slaves does not work. SOEM accesses slaves in LRW mode this way | Use LRD/LWR for process data access or use more optimal interleaved access for process data access from Master (TwinCAT way) |
| PINDSW-1005 | AM335x | ESC test tool - Errors: some registers which are “Mandatory” read-only are actually writable | None |
| PINDSW-2204 | Sitara | Frames with no SFD not counted as errors if received on reverse path | None |
| PINDSW-2360 | Sitara | System time of next Sync0 pulse register (0x990:0x993) is not instantaneous, resulting in read of incorrect value if read immediately after sync pulse | None |
| PINDSW-3120 | Sitara | Lost Link Counter register (0x310) increments with “2” on every link down instead of “1” | Revert back the MDIO Link interrupt to Edge in tiesc_pruss_intc_mapping.h file. Customers need to make sure that above mentioned link stability issue is not seen in their setup before making this change. |
| PINDSW-3138 | AM437x | While setting the AM437x IDK single chip motor control demo in csv mode, the motor either spins too fast or too slow or completely stop, and position is random and often quite large. | None |
| PINDSW-4268 | AM335x | EtherCAT application takes 3 seconds to comeup on AM335x baremetal example. | Comment OLED related code in tiesc_soc.c file. |
| PINDSW-4269 | AM335x | LED Control and Rotary Switch inputs do not work in AM335x baremetal example | None |
| PINDSW-4298 | AM65x | IDK does not detected by TwinCAT when NIC’s Link Speed Duplex is in 100Mbps Full Duplex Mode | None |
| PINDSW-4308 | AM65x | projectCreate.bat does not generate postbuild images. | Append following arguments for the post build script in CCS. am65xx mcu |
| PINDSW-4310 | Sitara | EtherCAT Slave in DC slave mode takes longer to recover from reference clock shifts | None |
EtherCAT errata for AM57x, AM437x is the same as AM335x. Please find the details here
