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AM263x MCU+ SDK
09.01.00
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33 #ifndef SOC_RCM_AM263X_H_
34 #define SOC_RCM_AM263X_H_
54 #define SOC_RCM_FREQ_MHZ2HZ(x) ((x) * 1000 * 1000)
55 #define SOC_RCM_FREQ_HZ2MHZ(x) ((x) / (1000 * 1000))
62 typedef enum SOC_WarmResetCause_e
118 typedef enum SOC_RcmWarm_ResetTime123_e
193 typedef enum SOC_RcmResetCause_e
252 typedef enum SOC_Rcmr5fssNum_e
270 typedef enum SOC_RcmPeripheralId_e
400 typedef enum SOC_RcmPeripheralClockSource_e
458 typedef enum SOC_RcmPllFoutFreqId_e
476 typedef enum SOC_RcmXtalFreqId_e
484 typedef enum SOC_RcmPllId_e
501 typedef enum SOC_RcmPllHSDIVOutId_e
522 typedef struct SOC_RcmClkSrcInfo_s
528 typedef struct SOC_RcmXTALInfo_s
534 typedef struct SOC_RcmADPLLJConfig_s
544 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)
545 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)
546 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)
547 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)
548 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL (RCM_PLL_HSDIV_OUTPUT_ENABLE_0 | \
549 RCM_PLL_HSDIV_OUTPUT_ENABLE_1 | \
550 RCM_PLL_HSDIV_OUTPUT_ENABLE_2 | \
551 RCM_PLL_HSDIV_OUTPUT_ENABLE_3)
553 #define RCM_PLL_HSDIV_OUTPUT_IDX0 (0)
554 #define RCM_PLL_HSDIV_OUTPUT_IDX1 (1)
555 #define RCM_PLL_HSDIV_OUTPUT_IDX2 (2)
556 #define RCM_PLL_HSDIV_OUTPUT_IDX3 (3)
557 #define RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)
559 typedef struct SOC_RcmPllHsDivOutConfig_s
SOC_Rcmr5fssNum
Definition: soc_rcm.h:253
@ RCM_PLLHSDIV_OUT_NONE
Value specifying invalid/no HSDIVIDER ID.
Definition: soc_rcm.h:518
@ SOC_RcmPeripheralId_LIN0_UART0
Value specifying LIN0_UART0.
Definition: soc_rcm.h:371
void SOC_rcmR5SS1PowerOnReset(void)
Reset R5SS1 Core.
@ RCM_PLLHSDIV_OUT_1
Value specifying HSDIVIDER 1.
Definition: soc_rcm.h:510
@ SOC_RcmResetCause_MMR_CPU0_VIM0_RESET
Value specifying R5 Core A Subsytem Reset.
Definition: soc_rcm.h:210
@ SOC_WARM_RESET_PAD_TIME_1024US
Delay Value specifying in time 1024us.
Definition: soc_rcm.h:167
@ SOC_RcmPeripheralId_WDT2
Value specifying WDT2.
Definition: soc_rcm.h:319
void SOC_configureWarmResetInputFallDelay(uint16_t inpFallDelayValue)
Program output delay on warm reset Pad 3.
@ RCM_PLLID_CORE
Definition: soc_rcm.h:486
@ SOC_RcmResetCause_MMR_CPU0_RESET
Value specifying R5 Core A (core only) Reset.
Definition: soc_rcm.h:218
void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure CORE PLL HSDIVIDERS.
@ RCM_PLLID_PER
Definition: soc_rcm.h:487
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enable)
Enable/disable module clock (IP clock configuration)
void SOC_rcmCoreR5FUnhalt(uint32_t cpuId)
Unhalt R5 cores.
uint32_t SOC_rcmCoreApllRelockPreRequisite(void)
Pre-requisite sequence to Re-configure CORE PLL.
@ r5fss1
Value specifying Warm Reset.
Definition: soc_rcm.h:261
@ SOC_RcmPeripheralId_RTI1
Value specifying RTI1.
Definition: soc_rcm.h:299
Definition: soc_rcm.h:535
@ SOC_RcmPeripheralId_MCSPI2
Value specifying MCSPI2.
Definition: soc_rcm.h:335
SOC_RcmPeripheralClockSource
Definition: soc_rcm.h:401
uint32_t FracM
Definition: soc_rcm.h:539
@ SOC_WARM_RESET_PAD_TIME_128US
Delay Value specifying in time 128us.
Definition: soc_rcm.h:155
void SOC_rcmsetTraceClock(uint32_t traceFreqHz)
Set Trace clock frequency.
@ SOC_RcmPeripheralId_MCSPI0
Value specifying MCSPI0.
Definition: soc_rcm.h:327
void SOC_rcmStartMemInitTCMA(uint32_t cpuId)
Start memory initialization for R5 TCMA.
@ SOC_WARM_RESET_PAD_TIME_512US
Delay Value specifying in time 512us.
Definition: soc_rcm.h:163
uint32_t M
Definition: soc_rcm.h:538
@ SOC_WARM_RESET_PAD_TIME_4US
Delay Value specifying in time 4us.
Definition: soc_rcm.h:135
void SOC_configureWarmResetInputRiseDelay(uint16_t inpRiseDelayValue)
Program input rise delay on warm reset Pad 2.
@ SOC_WARM_RESET_PAD_TIME_2048US
Delay Value specifying in time 2048us.
Definition: soc_rcm.h:171
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0
Value specifying PLL Core Clock Out 0 (400 Mhz)
Definition: soc_rcm.h:433
uint32_t Fout
Definition: soc_rcm.h:540
@ SOC_WARM_RESET_PAD_TIME_2US
Delay Value specifying in time 2us.
Definition: soc_rcm.h:131
@ SOC_WarmResetCause_MSS_WDT0
Value specifying MSS WDT0.
Definition: soc_rcm.h:71
void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc)
Set R5 clock source.
@ SOC_WarmResetCause_EXT_PAD_RESET
Value specifying External Pad Reset.
Definition: soc_rcm.h:91
@ SOC_WarmResetCause_MSS_WDT3
Value specifying MSS WDT3.
Definition: soc_rcm.h:83
@ SOC_RcmPeripheralId_LIN4_UART4
Value specifying LIN4_UART4.
Definition: soc_rcm.h:387
@ SOC_RcmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:198
void SOC_rcmWaitMemInitTCMB(uint32_t cpuId)
Wait memory initialization to complete for R5 TCMB.
SOC_RcmPeripheralId
Definition: soc_rcm.h:271
@ SOC_RcmPeripheralClockSource_XTALCLK
Value specifying Crystal Clock.
Definition: soc_rcm.h:405
void SOC_rcmStartMemInitTCMB(uint32_t cpuId)
Start memory initialization for R5 TCMB.
@ SOC_WARM_RESET_PAD_TIME_8US
Delay Value specifying in time 8us.
Definition: soc_rcm.h:139
@ SOC_RcmResetCause_RST_CAUSE_UNKNOWN
Value specifying R5 Reset due to Unknown reason.
Definition: soc_rcm.h:242
void SOC_rcmsetClkoutClock(uint32_t clkout0FreqHz, uint32_t clkout1FreqHz)
Set CLKOUT clock frequency.
@ SOC_RcmPeripheralId_WDT1
Value specifying WDT1.
Definition: soc_rcm.h:315
@ SOC_WARM_RESET_PAD_TIME_32US
Delay Value specifying in time 32us.
Definition: soc_rcm.h:147
@ SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ
Value specifying Software Warm Reset.
Definition: soc_rcm.h:87
@ SOC_RcmPeripheralId_GPMC
Value specifying GPMC.
Definition: soc_rcm.h:359
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0
Value specifying PLL Core Clock Out 0 (160 Mhz)
Definition: soc_rcm.h:445
void SOC_configureWarmResetOutputDelay(uint16_t opDelayValue)
Program output delay on warm reset Pad 1.
@ SOC_RcmPeripheralClockSource_SYS_CLK
Value specifying System Clock (200Mhz)
Definition: soc_rcm.h:409
@ SOC_WARM_RESET_PAD_TIME_1US
Delay Value specifying in time 1us.
Definition: soc_rcm.h:127
@ SOC_RcmPeripheralId_MCSPI1
Value specifying MCSPI1.
Definition: soc_rcm.h:331
Definition: soc_rcm.h:560
@ SOC_RcmPeripheralId_MCSPI3
Value specifying MCSPI3.
Definition: soc_rcm.h:339
@ SOC_RcmPeripheralId_WDT3
Value specifying WDT3.
Definition: soc_rcm.h:323
SOC_RcmPllHSDIVOutId
Definition: soc_rcm.h:502
SOC_RcmXtalFreqId
Definition: soc_rcm.h:477
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
Set module clock (IP clock configuration)
Definition: soc_rcm.h:529
SOC_RcmPllId pllId
Definition: soc_rcm.h:524
SOC_RcmResetCause SOC_rcmGetResetCause(SOC_Rcmr5fssNum r5fssNum)
Get R5FSS reset cause.
void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
Set R5FSS and Sysclk frequency (Root clock configuration)
@ SOC_WARM_RESET_PAD_TIME_8192US
Delay Value specifying in time 8192us.
Definition: soc_rcm.h:179
uint32_t Finp
Definition: soc_rcm.h:530
@ SOC_WARM_RESET_PAD_TIME_16384US
Delay Value specifying in time 16384us.
Definition: soc_rcm.h:183
@ SOC_WARM_RESET_PAD_TIME_500NS
Delay Value specifying in time 500ns.
Definition: soc_rcm.h:123
@ SOC_RcmPeripheralId_I2C
Value specifying I2C.
Definition: soc_rcm.h:367
@ SOC_RcmPeripheralId_MCAN2
Value specifying MCAN2.
Definition: soc_rcm.h:283
@ SOC_RcmResetCause_FSM_TRIGGER_RESET
Value specifying R5 Reset due to FSM Trigger.
Definition: soc_rcm.h:234
uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId)
Return R5SS status operating in lockstep or dual core mode.
SOC_RcmResetCause
Definition: soc_rcm.h:194
@ RCM_PLLID_WUCPUCLK
Definition: soc_rcm.h:489
@ SOC_RcmPeripheralId_LIN5_UART5
Value specifying LIN5_UART5.
Definition: soc_rcm.h:391
void SOC_clearWarmResetCause(void)
Clear Reset Cause register.
@ SOC_RcmResetCause_DBG_CPU1_RESET
Value specifying R5 Core B Debug Reset.
Definition: soc_rcm.h:230
@ SOC_WarmResetCause_TEMP_SENSOR1_RESET
Value specifying Temperature Sensor1 Reset.
Definition: soc_rcm.h:107
void SOC_rcmMemInitMailboxMemory(void)
Wait memory initialization to complete for Mailbox memory.
@ SOC_RcmResetCause_DBG_CPU0_RESET
Value specifying R5 Core A Debug Reset.
Definition: soc_rcm.h:226
@ SOC_RcmPeripheralId_MCAN0
Value specifying MCAN0.
Definition: soc_rcm.h:275
@ RCM_PLLID_RCCLK32K
Definition: soc_rcm.h:490
@ RCM_PLLID_RCCLK10M
Definition: soc_rcm.h:491
@ SOC_WARM_RESET_PAD_TIME_16US
Delay Value specifying in time 16us.
Definition: soc_rcm.h:143
@ RCM_XTAL_FREQID_CLK_25MHZ
Value specifying XTAL frequency 25MHZ.
Definition: soc_rcm.h:481
void SOC_rcmR5SS1TriggerReset(void)
Trigger R5SS1 core reset.
@ RCM_PLLHSDIV_OUT_0
Value specifying HSDIVIDER 0.
Definition: soc_rcm.h:506
uint32_t hsdivOutEnMask
Definition: soc_rcm.h:561
void SOC_rcmSetCPSWResetBit()
Set CPSW hard reset bit.
@ SOC_WarmResetCause_HSM_WDT
Value specifying HSM WDT.
Definition: soc_rcm.h:95
Definition: soc_rcm.h:523
void SOC_rcmR5ConfigLockStep(uint32_t cpuId)
Configure R5 in lock step mode.
@ SOC_RcmPeripheralId_RTI0
Value specifying RTI0.
Definition: soc_rcm.h:295
void SOC_rcmR5SS0TriggerReset(void)
Trigger R5 core reset.
bool div2flag
Definition: soc_rcm.h:531
void SOC_rcmPerApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure PER PLL.
void SOC_rcmWaitMemInitTCMA(uint32_t cpuId)
Wait memory initialization to complete for R5 TCMA.
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
Set R5SS0/R5SS1 and SysClk frequency.
@ SOC_RcmPeripheralClockSource_RCCLK32K
Value specifying RC clock (32KHz)
Definition: soc_rcm.h:425
@ SOC_WARM_RESET_PAD_TIME_64US
Delay Value specifying in time 64us.
Definition: soc_rcm.h:151
@ SOC_RcmPeripheralId_MCSPI4
Value specifying MCSPI4.
Definition: soc_rcm.h:343
@ SOC_WarmResetCause_MSS_WDT2
Value specifying MSS WDT2.
Definition: soc_rcm.h:79
@ SOC_RcmPeripheralClockSource_EXT_REFCLK
Value specifying external reference clock.
Definition: soc_rcm.h:417
@ SOC_RcmPeripheralId_ICSSM0_UART0
Value specifying ICSSM0_UART0.
Definition: soc_rcm.h:351
@ SOC_WarmResetCause_MSS_WDT1
Value specifying MSS WDT1.
Definition: soc_rcm.h:75
@ SOC_WARM_RESET_PAD_TIME_256US
Delay Value specifying in time 256us.
Definition: soc_rcm.h:159
@ SOC_RcmPeripheralId_MCAN3
Value specifying MCAN3.
Definition: soc_rcm.h:287
uint32_t Finp
Definition: soc_rcm.h:541
SOC_RcmPllId
Definition: soc_rcm.h:485
@ RCM_PLL_FOUT_FREQID_CLK_2000MHZ
Value specifying PLL output frequency 2000MHz.
Definition: soc_rcm.h:463
SOC_RcmWarm_ResetTime123
Definition: soc_rcm.h:119
@ SOC_RcmPeripheralId_LIN3_UART3
Value specifying LIN3_UART3.
Definition: soc_rcm.h:383
@ SOC_WarmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:67
@ SOC_RcmPeripheralClockSource_WUCPUCLK
Value specifying wake up clock.
Definition: soc_rcm.h:413
@ SOC_RcmPeripheralId_RTI3
Value specifying RTI3.
Definition: soc_rcm.h:307
void SOC_rcmR5SS0PowerOnReset(void)
Reset R5SS0 Core.
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (192 Mhz)
Definition: soc_rcm.h:449
@ SOC_RcmPeripheralId_LIN1_UART1
Value specifying LIN1_UART1.
Definition: soc_rcm.h:375
@ SOC_RcmPeripheralId_MCAN1
Value specifying MCAN1.
Definition: soc_rcm.h:279
void SOC_generateSwWarmReset(void)
Generate SW WARM reset.
@ SOC_RcmPeripheralId_RTI2
Value specifying RTI2.
Definition: soc_rcm.h:303
@ SOC_WarmResetCause_TEMP_SENSOR0_RESET
Value specifying Temperature Sensor0 Reset.
Definition: soc_rcm.h:103
uint32_t N
Definition: soc_rcm.h:536
void SOC_rcmClearCPSWResetBit()
Clear CPSW hard reset bit.
@ SOC_RcmResetCause_STC_RESET
Value specifying STC Reset.
Definition: soc_rcm.h:206
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (500 Mhz)
Definition: soc_rcm.h:437
@ RCM_PLL_FOUT_FREQID_CLK_1920MHZ
Value specifying PLL output frequency 1920MHz.
Definition: soc_rcm.h:467
@ SOC_RcmResetCause_WARM_RESET
Value specifying Warm Reset.
Definition: soc_rcm.h:202
@ SOC_RcmPeripheralId_MMC0
Value specifying MMC0.
Definition: soc_rcm.h:347
void SOC_rcmR5ConfigDualCore(uint32_t cpuId)
Configure R5 in dual core mode.
void SOC_rcmMemInitL2Memory(void)
Wait memory initialization to complete for L2 Bank2 and Bank3 memory.
@ SOC_WARM_RESET_PAD_TIME_4096US
Delay Value specifying in time 4096us.
Definition: soc_rcm.h:175
SOC_WarmResetCause
Definition: soc_rcm.h:63
@ SOC_RcmResetCause_MMR_CPU1_VIM1_RESET
Value specifying R5 Core B Subsytem Reset.
Definition: soc_rcm.h:214
SOC_RcmPllHSDIVOutId hsDivOut
Definition: soc_rcm.h:525
@ SOC_WarmResetCause_DBG_RESET
Value specifying Debugger Reset.
Definition: soc_rcm.h:99
@ RCM_PLLID_EXTREFCLK
Definition: soc_rcm.h:492
@ SOC_RcmPeripheralId_QSPI0
Value specifying QSPI0.
Definition: soc_rcm.h:291
SOC_WarmResetCause SOC_getWarmResetCause(void)
Returns cause of WARM reset.
@ SOC_RcmPeripheralId_LIN2_UART2
Value specifying LIN2_UART2.
Definition: soc_rcm.h:379
SOC_RcmPllFoutFreqId
Definition: soc_rcm.h:459
@ RCM_PLLID_XTALCLK
Definition: soc_rcm.h:488
uint32_t M2
Definition: soc_rcm.h:537
@ r5fss0
Value specifying Power ON Reset.
Definition: soc_rcm.h:257
@ SOC_RcmResetCause_MMR_CPU1_RESET
Value specifying R5 Core B (core only) Reset.
Definition: soc_rcm.h:222
@ RCM_PLLHSDIV_OUT_2
Value specifying HSDIVIDER 2.
Definition: soc_rcm.h:514
@ SOC_RcmPeripheralId_WDT0
Value specifying WDT0.
Definition: soc_rcm.h:311
uint32_t SOC_rcmGetR5Clock(uint32_t cpuId)
Get R5SS0/1 frequency.
@ SOC_RcmPeripheralId_CONTROLSS_PLL
Value specifying CONTROLSS_PLL.
Definition: soc_rcm.h:363
@ SOC_RcmPeripheralId_CPTS
Value specifying CPTS.
Definition: soc_rcm.h:355
void SOC_configureWarmResetSource(uint32_t source)
Configure WARM reset source.
@ SOC_RcmPeripheralClockSource_CTPS_GENF0
Value specifying CPTS GENF0 clock.
Definition: soc_rcm.h:429
#define RCM_PLL_HSDIV_OUTPUT_COUNT
Definition: soc_rcm.h:557
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2
Value specifying PLL Core Clock Out 2 (400 Mhz)
Definition: soc_rcm.h:441
void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure CORE PLL.
@ SOC_RcmResetCause_POR_RST_CTRL0
Value specifying R5 Reset due to write to debug POR RST CTRL Reg.
Definition: soc_rcm.h:238
@ SOC_RcmPeripheralClockSource_RCCLK10M
Value specifying RC clock (10MHz)
Definition: soc_rcm.h:421