59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_soc.h>
61 #include <drivers/hw_include/cslr_lin.h>
62 #include <drivers/hw_include/hw_types.h>
74 #define LIN_IO_DFT_KEY (0xAU)
78 #define LIN_WAKEUP_KEY (0xF0U)
88 #define LIN_ID0 (0x1U)
89 #define LIN_ID1 (0x2U)
90 #define LIN_ID2 (0x4U)
91 #define LIN_ID3 (0x8U)
92 #define LIN_ID4 (0x10U)
93 #define LIN_ID5 (0x20U)
106 #define LIN_INT_WAKEUP (0x00000002U)
107 #define LIN_INT_TO (0x00000010U)
108 #define LIN_INT_TOAWUS (0x00000040U)
109 #define LIN_INT_TOA3WUS (0x00000080U)
110 #define LIN_INT_TX (0x00000100U)
111 #define LIN_INT_RX (0x00000200U)
112 #define LIN_INT_ID (0x00002000U)
113 #define LIN_INT_PE (0x01000000U)
114 #define LIN_INT_OE (0x02000000U)
115 #define LIN_INT_FE (0x04000000U)
116 #define LIN_INT_NRE (0x08000000U)
117 #define LIN_INT_ISFE (0x10000000U)
118 #define LIN_INT_CE (0x20000000U)
119 #define LIN_INT_PBE (0x40000000U)
120 #define LIN_INT_BE (0x80000000U)
121 #define LIN_INT_ALL (0xFF0023D2U)
132 #define LIN_FLAG_BREAK (CSL_LIN_SCIFLR_BRKDT_MASK)
133 #define LIN_FLAG_WAKEUP (CSL_LIN_SCIFLR_WAKEUP_MASK)
134 #define LIN_FLAG_IDLE (CSL_LIN_SCIFLR_IDLE_MASK)
135 #define LIN_FLAG_BUSY (CSL_LIN_SCIFLR_BUSY_MASK)
136 #define LIN_FLAG_TO (CSL_LIN_SCIFLR_TIMEOUT_MASK)
137 #define LIN_FLAG_TOAWUS (CSL_LIN_SCIFLR_TOAWUS_MASK)
138 #define LIN_FLAG_TOA3WUS (CSL_LIN_SCIFLR_TOA3WUS_MASK)
139 #define LIN_FLAG_TXRDY (CSL_LIN_SCIFLR_TXRDY_MASK)
140 #define LIN_FLAG_RXRDY (CSL_LIN_SCIFLR_RXRDY_MASK)
141 #define LIN_FLAG_TXWAKE (CSL_LIN_SCIFLR_TXWAKE_MASK)
142 #define LIN_FLAG_TXEMPTY (CSL_LIN_SCIFLR_TXEMPTY_MASK)
143 #define LIN_FLAG_RXWAKE (CSL_LIN_SCIFLR_RXWAKE_MASK)
144 #define LIN_FLAG_TXID (CSL_LIN_SCIFLR_IDTXFLAG_MASK)
145 #define LIN_FLAG_RXID (CSL_LIN_SCIFLR_IDRXFLAG_MASK)
146 #define LIN_FLAG_PE (CSL_LIN_SCIFLR_PE_MASK)
147 #define LIN_FLAG_OE (CSL_LIN_SCIFLR_OE_MASK)
148 #define LIN_FLAG_FE (CSL_LIN_SCIFLR_FE_MASK)
149 #define LIN_FLAG_NRE (CSL_LIN_SCIFLR_NRE_MASK)
150 #define LIN_FLAG_ISFE (CSL_LIN_SCIFLR_ISFE_MASK)
151 #define LIN_FLAG_CE (CSL_LIN_SCIFLR_CE_MASK)
152 #define LIN_FLAG_PBE (CSL_LIN_SCIFLR_PBE_MASK)
153 #define LIN_FLAG_BE (CSL_LIN_SCIFLR_BE_MASK)
165 #define LIN_VECT_NONE (0x00)
166 #define LIN_VECT_WAKEUP (0x01)
167 #define LIN_VECT_ISFE (0x02)
168 #define LIN_VECT_PE (0x03)
169 #define LIN_VECT_ID (0x04)
170 #define LIN_VECT_PBE (0x05)
171 #define LIN_VECT_FE (0x06)
172 #define LIN_VECT_BREAK (0x07)
173 #define LIN_VECT_CE (0x08)
174 #define LIN_VECT_OE (0x09)
175 #define LIN_VECT_BE (0x0A)
176 #define LIN_VECT_RX (0x0B)
177 #define LIN_VECT_TX (0x0C)
178 #define LIN_VECT_NRE (0x0D)
179 #define LIN_VECT_TOAWUS (0x0E)
180 #define LIN_VECT_TOA3WUS (0x0F)
181 #define LIN_VECT_TO (0x10)
193 #define LIN_ALL_ERRORS (0xF0000000U)
194 #define LIN_BIT_ERROR (0x80000000U)
195 #define LIN_BUS_ERROR (0x40000000U)
196 #define LIN_CHECKSUM_ERROR (0x20000000U)
197 #define LIN_ISF_ERROR (0x10000000U)
209 #define LIN_SCI_ALL_ERRORS (0x7000000U)
210 #define LIN_SCI_FRAME_ERROR (0x4000000U)
211 #define LIN_SCI_PARITY_ERROR (0x2000000U)
212 #define LIN_SCI_BREAK_ERROR (0x1000000U)
225 #define LIN_SCI_INT_BREAK (0x1U)
226 #define LIN_SCI_INT_WAKEUP (0x2U)
227 #define LIN_SCI_INT_TX (0x100U)
228 #define LIN_SCI_INT_RX (0x200U)
229 #define LIN_SCI_INT_TX_DMA (0x10000U)
230 #define LIN_SCI_INT_RX_DMA (0x20000U)
231 #define LIN_SCI_INT_PARITY (0x1000000U)
232 #define LIN_SCI_INT_OVERRUN (0x2000000U)
233 #define LIN_SCI_INT_FRAME (0x4000000U)
234 #define LIN_SCI_INT_ALL (0x7000303U)
413 #if defined (SOC_AM263X)
415 (base == CSL_LIN0_U_BASE) ||
416 (base == CSL_LIN1_U_BASE) ||
417 (base == CSL_LIN2_U_BASE) ||
418 (base == CSL_LIN3_U_BASE) ||
419 (base == CSL_LIN4_U_BASE)
445 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CLK_MASTER_MASK, CSL_LIN_SCIGCR1_CLK_MASTER_SHIFT, mode);
471 HW_WR_FIELD32_RAW((base + CSL_LIN_MBRSR), CSL_LIN_MBRSR_MBR_MASK, CSL_LIN_MBRSR_MBR_SHIFT, (clock / 20000U));
493 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_HGENCTRL_MASK, CSL_LIN_SCIGCR1_HGENCTRL_SHIFT, type);
511 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK, CSL_LIN_SCIGCR1_PARITYENA_SHIFT, CSL_TRUE);
529 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK, CSL_LIN_SCIGCR1_PARITYENA_SHIFT, CSL_FALSE);
547 static inline uint16_t
550 uint16_t p0, p1, parityIdentifier;
555 p1 = !(((identifier &
LIN_ID1) >> 1U) ^ ((identifier &
LIN_ID3) >> 3U) ^
557 parityIdentifier = identifier | ((p0 << 6U) | (p1 << 7U));
559 return(parityIdentifier);
579 HW_WR_FIELD32_RAW((base + CSL_LIN_LINID), CSL_LIN_LINID_IDBYTE_MASK, CSL_LIN_LINID_IDBYTE_SHIFT, identifier);
599 HW_WR_FIELD32_RAW((base + CSL_LIN_LINID), CSL_LIN_LINID_IDSLAVETASKBYTE_MASK, CSL_LIN_LINID_IDSLAVETASKBYTE_SHIFT, identifier);
618 HW_WR_FIELD32_RAW((base + CSL_LIN_LINTD0), CSL_LIN_LINTD0_TD0_MASK, CSL_LIN_LINTD0_TD0_SHIFT, (uint16_t)
LIN_WAKEUP_KEY);
621 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK,
622 CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
625 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_GENWU_MASK, CSL_LIN_SCIGCR2_GENWU_SHIFT, CSL_TRUE);
628 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK,
629 CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_FALSE);
653 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK, CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
672 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_SC_MASK, CSL_LIN_SCIGCR2_SC_SHIFT, CSL_TRUE);
691 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_CC_MASK, CSL_LIN_SCIGCR2_CC_SHIFT, CSL_TRUE);
712 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_TXRDY_MASK) ==
713 CSL_LIN_SCIFLR_TXRDY_MASK);
736 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIFORMAT), CSL_LIN_SCIFORMAT_LENGTH_MASK, CSL_LIN_SCIFORMAT_LENGTH_SHIFT, ((uint32_t)length - (uint32_t)1U));
760 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_COMMMODE_MASK, CSL_LIN_SCIGCR1_COMMMODE_SHIFT, (uint16_t)mode);
780 HW_WR_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_TXIDMASK_MASK, CSL_LIN_LINMASK_TXIDMASK_SHIFT, mask);
800 HW_WR_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_RXIDMASK_MASK, CSL_LIN_LINMASK_RXIDMASK_SHIFT, (uint32_t)mask);
812 static inline uint16_t
819 return(HW_RD_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_TXIDMASK_MASK, CSL_LIN_LINMASK_TXIDMASK_SHIFT));
833 static inline uint16_t
840 return(HW_RD_FIELD32_RAW((base + CSL_LIN_LINMASK), CSL_LIN_LINMASK_RXIDMASK_MASK, CSL_LIN_LINMASK_RXIDMASK_SHIFT));
861 return(HW_RD_FIELD32_RAW((base + CSL_LIN_SCIFLR), CSL_LIN_SCIFLR_RXRDY_MASK, CSL_LIN_SCIFLR_RXRDY_SHIFT));
874 static inline uint16_t
881 return(HW_RD_FIELD32_RAW((base + CSL_LIN_LINID), CSL_LIN_LINID_RECEIVEDID_MASK, CSL_LIN_LINID_RECEIVEDID_SHIFT));
902 return(HW_RD_FIELD32_RAW((base + CSL_LIN_SCIFLR), CSL_LIN_SCIFLR_IDTXFLAG_MASK, CSL_LIN_SCIFLR_IDTXFLAG_SHIFT));
923 return(HW_RD_FIELD32_RAW((base + CSL_LIN_SCIFLR), CSL_LIN_SCIFLR_IDRXFLAG_MASK, CSL_LIN_SCIFLR_IDRXFLAG_SHIFT));
966 HW_WR_REG32_RAW((base + CSL_LIN_SCISETINT), HW_RD_REG32_RAW(base + CSL_LIN_SCISETINT)|intFlags);
1009 HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINT), intFlags);
1051 HW_WR_REG32_RAW((base + CSL_LIN_SCIFLR), intFlags);
1094 HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINTLVL), intFlags);
1137 HW_WR_REG32_RAW((base + CSL_LIN_SCISETINTLVL), HW_RD_REG32_RAW(base + CSL_LIN_SCISETINTLVL)|intFlags);
1164 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)
LIN_IO_DFT_KEY);
1167 HW_WR_REG32_RAW((base + CSL_LIN_IODFTCTRL), HW_RD_REG32_RAW(base + CSL_LIN_IODFTCTRL)|errors);
1170 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)CSL_FALSE);
1195 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)
LIN_IO_DFT_KEY);
1198 HW_WR_REG32_RAW((base + CSL_LIN_IODFTCTRL), HW_RD_REG32_RAW(base + CSL_LIN_IODFTCTRL)&~(errors));
1201 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, (uint32_t)CSL_FALSE);
1223 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_ADAPT_MASK, CSL_LIN_SCIGCR1_ADAPT_SHIFT, CSL_TRUE);
1242 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_ADAPT_MASK, CSL_LIN_SCIGCR1_ADAPT_SHIFT, CSL_FALSE);
1263 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_STOPEXTFRAME_MASK, CSL_LIN_SCIGCR1_STOPEXTFRAME_SHIFT, CSL_TRUE);
1285 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CTYPE_MASK, CSL_LIN_SCIGCR1_CTYPE_SHIFT, type);
1320 HW_WR_FIELD32_RAW((base + CSL_LIN_LINCOMP), (CSL_LIN_LINCOMP_SDEL_MASK|CSL_LIN_LINCOMP_SBREAK_MASK),
1321 CSL_LIN_LINCOMP_SDEL_SHIFT, (syncBreak | (delimiter - 1U)));
1338 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LINMODE_MASK,
1339 CSL_LIN_SCIGCR1_LINMODE_SHIFT, CSL_FALSE);
1341 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CLK_MASTER_MASK,
1342 CSL_LIN_SCIGCR1_CLK_MASTER_SHIFT, CSL_TRUE);
1344 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_TIMINGMODE_MASK,
1345 CSL_LIN_SCIGCR1_TIMINGMODE_SHIFT, CSL_TRUE);
1363 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CLK_MASTER_MASK,
1364 CSL_LIN_SCIGCR1_CLK_MASTER_SHIFT, CSL_FALSE);
1366 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_TIMINGMODE_MASK,
1367 CSL_LIN_SCIGCR1_TIMINGMODE_SHIFT, CSL_FALSE);
1369 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LINMODE_MASK,
1370 CSL_LIN_SCIGCR1_LINMODE_SHIFT, CSL_TRUE);
1391 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1394 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_COMMMODE_MASK,
1395 CSL_LIN_SCIGCR1_COMMMODE_SHIFT, mode);
1415 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1418 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK,
1419 CSL_LIN_SCIGCR1_PARITYENA_SHIFT, 1U);
1421 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITY_MASK,
1422 CSL_LIN_SCIGCR1_PARITY_SHIFT, parity);
1438 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1441 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_PARITYENA_MASK,
1442 CSL_LIN_SCIGCR1_PARITYENA_SHIFT, 0U);
1462 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1465 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_STOP_MASK,
1466 CSL_LIN_SCIGCR1_STOP_SHIFT, number);
1487 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1490 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SLEEP_MASK,
1491 CSL_LIN_SCIGCR1_SLEEP_SHIFT, CSL_TRUE);
1508 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1511 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SLEEP_MASK,
1512 CSL_LIN_SCIGCR1_SLEEP_SHIFT, CSL_FALSE);
1532 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1535 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK,
1536 CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_TRUE);
1552 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1555 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR2), CSL_LIN_SCIGCR2_POWERDOWN_MASK,
1556 CSL_LIN_SCIGCR2_POWERDOWN_SHIFT, CSL_FALSE);
1575 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1579 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIFORMAT), CSL_LIN_SCIFORMAT_CHAR_MASK,
1580 CSL_LIN_SCIFORMAT_CHAR_SHIFT, (uint32_t)(numBits - 1U));
1600 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1604 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIFORMAT), CSL_LIN_SCIFORMAT_LENGTH_MASK,
1605 CSL_LIN_SCIFORMAT_LENGTH_SHIFT, (uint32_t)(length - 1U));
1624 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1627 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_RXRDY_MASK) == CSL_LIN_SCIFLR_RXRDY_MASK);
1646 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1649 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_TXRDY_MASK) == CSL_LIN_SCIFLR_TXRDY_MASK);
1673 static inline uint16_t
1678 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1682 return(emulation ? (HW_RD_REG32_RAW(base + CSL_LIN_SCIED) & CSL_LIN_SCIED_ED_MASK) :
1683 (HW_RD_REG32_RAW(base + CSL_LIN_SCIRD) & CSL_LIN_SCIRD_RD_MASK));
1705 static inline uint16_t
1710 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1719 return(emulation ? (HW_RD_REG32_RAW(base + CSL_LIN_SCIED) & CSL_LIN_SCIED_ED_MASK) :
1720 (HW_RD_REG32_RAW(base + CSL_LIN_SCIRD) & CSL_LIN_SCIRD_RD_MASK));
1742 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1747 HW_WR_FIELD32_RAW((base + CSL_LIN_SCITD), CSL_LIN_SCITD_TD_MASK, CSL_LIN_SCITD_TD_SHIFT, data);
1766 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1776 HW_WR_FIELD32_RAW((base + CSL_LIN_SCITD), CSL_LIN_SCITD_TD_MASK, CSL_LIN_SCITD_TD_SHIFT, data);
1802 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1806 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
1809 HW_WR_REG32_RAW((base + CSL_LIN_IODFTCTRL), (HW_RD_REG32_RAW(base + CSL_LIN_IODFTCTRL)|errors));
1812 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
1835 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1839 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
1842 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), errors, 0U, CSL_FALSE);
1845 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
1880 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1884 HW_WR_REG32_RAW((base + CSL_LIN_SCISETINT), (HW_RD_REG32_RAW(base + CSL_LIN_SCISETINT)|intFlags));
1919 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1923 HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINT), (HW_RD_REG32_RAW(base + CSL_LIN_SCICLEARINT)|intFlags));
1957 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
1961 HW_WR_REG32_RAW((base + CSL_LIN_SCIFLR), (HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR)|intFlags));
1996 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
2000 HW_WR_REG32_RAW((base + CSL_LIN_SCICLEARINTLVL), (HW_RD_REG32_RAW(base + CSL_LIN_SCICLEARINTLVL)|intFlags));
2034 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
2038 HW_WR_REG32_RAW((base + CSL_LIN_SCISETINTLVL), HW_RD_REG32_RAW(base + CSL_LIN_SCISETINTLVL)|intFlags);
2057 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
2061 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_IDLE_MASK) == 0U);
2081 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
2085 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_WAKEUP_MASK) == CSL_LIN_SCIFLR_WAKEUP_MASK);
2105 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
2109 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_RXWAKE_MASK) == CSL_LIN_SCIFLR_RXWAKE_MASK);
2128 DebugP_assert((HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1) & CSL_LIN_SCIGCR1_LINMODE_MASK) ==
2132 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_BRKDT_MASK) == CSL_LIN_SCIFLR_BRKDT_MASK);
2153 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR0), CSL_LIN_SCIGCR0_RESET_MASK, CSL_LIN_SCIGCR0_RESET_SHIFT, CSL_TRUE);
2156 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_RXFUNC_MASK, CSL_LIN_SCIPIO0_RXFUNC_SHIFT, CSL_TRUE);
2157 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_TXFUNC_MASK, CSL_LIN_SCIPIO0_TXFUNC_SHIFT, CSL_TRUE);
2178 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_RXFUNC_MASK, CSL_LIN_SCIPIO0_RXFUNC_SHIFT, CSL_FALSE);
2179 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIPIO0), CSL_LIN_SCIPIO0_TXFUNC_MASK, CSL_LIN_SCIPIO0_TXFUNC_SHIFT, CSL_FALSE);
2182 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR0), CSL_LIN_SCIGCR0_RESET_MASK, CSL_LIN_SCIGCR0_RESET_SHIFT, CSL_FALSE);
2206 DebugP_assert(prescaler <= (CSL_LIN_BRSR_SCI_LIN_PSL_MASK | CSL_LIN_BRSR_SCI_LIN_PSH_MASK));
2207 DebugP_assert(divider <= (CSL_LIN_BRSR_M_MASK >> CSL_LIN_BRSR_M_SHIFT));
2210 HW_WR_REG32_RAW((base + CSL_LIN_BRSR), (prescaler | (divider << CSL_LIN_BRSR_M_SHIFT)));
2229 HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)|CSL_LIN_SCIGCR1_TXENA_MASK);
2248 HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)&~(CSL_LIN_SCIGCR1_TXENA_MASK));
2267 HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)|CSL_LIN_SCIGCR1_RXENA_MASK);
2286 HW_WR_REG32_RAW((base + CSL_LIN_SCIGCR1), HW_RD_REG32_RAW(base + CSL_LIN_SCIGCR1)&~(CSL_LIN_SCIGCR1_RXENA_MASK));
2308 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SWNRST_MASK, CSL_LIN_SCIGCR1_SWNRST_SHIFT, CSL_TRUE);
2331 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SWNRST_MASK, CSL_LIN_SCIGCR1_SWNRST_SHIFT, CSL_FALSE);
2352 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_SWNRST_MASK, CSL_LIN_SCIGCR1_SWNRST_SHIFT, CSL_TRUE);
2372 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_BUSY_MASK) == CSL_LIN_SCIFLR_BUSY_MASK);
2392 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR) & CSL_LIN_SCIFLR_TXEMPTY_MASK) == CSL_LIN_SCIFLR_TXEMPTY_MASK);
2424 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
2427 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_LPBENA_MASK, CSL_LIN_IODFTCTRL_LPBENA_SHIFT, loopbackType);
2430 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_RXPENA_MASK, CSL_LIN_IODFTCTRL_RXPENA_SHIFT, path);
2451 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_LPBENA_MASK, CSL_LIN_IODFTCTRL_LPBENA_SHIFT, CSL_FALSE);
2454 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_RXPENA_MASK, CSL_LIN_IODFTCTRL_RXPENA_SHIFT, CSL_FALSE);
2473 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LOOPBACK_MASK, CSL_LIN_SCIGCR1_LOOPBACK_SHIFT, CSL_TRUE);
2492 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_LOOPBACK_MASK, CSL_LIN_SCIGCR1_LOOPBACK_SHIFT, CSL_FALSE);
2528 static inline uint32_t
2535 return(HW_RD_REG32_RAW(base + CSL_LIN_SCIFLR));
2549 static inline uint32_t
2556 return(HW_RD_REG32_RAW(base + CSL_LIN_SCISETINTLVL));
2594 static inline uint16_t
2601 return(HW_RD_REG32_RAW(base + CSL_LIN_SCIINTVECT0) & CSL_LIN_SCIINTVECT0_INTVECT0_MASK);
2639 static inline uint16_t
2646 return(HW_RD_REG32_RAW(base + CSL_LIN_SCIINTVECT1) & CSL_LIN_SCIINTVECT1_INTVECT1_MASK);
2664 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_MBUFMODE_MASK, CSL_LIN_SCIGCR1_MBUFMODE_SHIFT, CSL_TRUE);
2682 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_MBUFMODE_MASK, CSL_LIN_SCIGCR1_MBUFMODE_SHIFT, CSL_FALSE);
2706 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
2709 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_TXSHIFT_MASK, CSL_LIN_IODFTCTRL_TXSHIFT_SHIFT, delay);
2712 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
2738 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT,
LIN_IO_DFT_KEY);
2741 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_PINSAMPLEMASK_MASK, CSL_LIN_IODFTCTRL_PINSAMPLEMASK_SHIFT, mask);
2744 HW_WR_FIELD32_RAW((base + CSL_LIN_IODFTCTRL), CSL_LIN_IODFTCTRL_IODFTENA_MASK, CSL_LIN_IODFTCTRL_IODFTENA_SHIFT, CSL_FALSE);
2769 HW_WR_FIELD32_RAW((base + CSL_LIN_SCIGCR1), CSL_LIN_SCIGCR1_CONT_MASK, CSL_LIN_SCIGCR1_CONT_SHIFT, mode);
2792 HW_WR_REG32_RAW((base + CSL_LIN_LIN_GLB_INT_EN), HW_RD_REG32_RAW(base + CSL_LIN_LIN_GLB_INT_EN)|(CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line));
2815 HW_WR_REG32_RAW((base + CSL_LIN_LIN_GLB_INT_EN), HW_RD_REG32_RAW(base + CSL_LIN_LIN_GLB_INT_EN)&(~(CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line)));
2838 HW_WR_REG32_RAW((base + CSL_LIN_LIN_GLB_INT_CLR), (CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line));
2863 return((HW_RD_REG32_RAW(base + CSL_LIN_LIN_GLB_INT_FLG) & (CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line))
2864 == (CSL_LIN_LIN_GLB_INT_FLG_INT0_FLG_MASK<<(uint16_t)line));
2886 return((HW_RD_REG32_RAW(base + CSL_LIN_SCIPIO2) & pin) == pin);