MSPM0GX51X Driver Library  2.10.00.04
dl_i2c.h
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1 /*
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31  */
32 /*!****************************************************************************
33  * @file dl_i2c.h
34  * @brief Inter-Integrated Circuit (I2C) Driver Library
35  * @defgroup I2C Inter-Integrated Circuit (I2C)
36  *
37  * @anchor ti_dl_dl_i2c_Overview
38  * # Overview
39  *
40  * The I2C Library allows full configuration of the MSPM0 I2C module.
41  * The I2C module provides a standardized serial interface to transfer data
42  * between MSP devices and other external I2C devices (such as a sensors,
43  * memory, or DACs).
44  *
45  * <hr>
46  ******************************************************************************
47  */
51 #ifndef ti_dl_dl_i2c__include
52 #define ti_dl_dl_i2c__include
53 
54 #include <stdbool.h>
55 #include <stdint.h>
56 
57 #include <ti/devices/msp/msp.h>
58 #include <ti/driverlib/dl_common.h>
59 
60 #ifdef __MSPM0_HAS_I2C__
61 
62 #ifdef __cplusplus
63 extern "C" {
64 #endif
65 
66 /* clang-format off */
67 
74 #define DL_I2C_TX_FIFO_COUNT_MAXIMUM ((uint32_t)I2C_SYS_FENTRIES << 8)
75 
82 #define DL_I2C_RX_FIFO_COUNT_MAXIMUM ((uint32_t)I2C_SYS_FENTRIES)
83 
94 #define DL_I2C_CONTROLLER_STATUS_BUSY (I2C_MSR_BUSY_MASK)
95 
102 #define DL_I2C_CONTROLLER_STATUS_ERROR (I2C_MSR_ERR_MASK)
103 
107 #define DL_I2C_CONTROLLER_STATUS_ADDR_ACK (I2C_MSR_ADRACK_MASK)
108 
112 #define DL_I2C_CONTROLLER_STATUS_DATA_ACK (I2C_MSR_DATACK_MASK)
113 
117 #define DL_I2C_CONTROLLER_STATUS_ARBITRATION_LOST (I2C_MSR_ARBLST_MASK)
118 
122 #define DL_I2C_CONTROLLER_STATUS_IDLE (I2C_MSR_IDLE_MASK)
123 
129 #define DL_I2C_CONTROLLER_STATUS_BUSY_BUS (I2C_MSR_BUSBSY_MASK)
130 
141 #define DL_I2C_TARGET_STATUS_ADDRESS_MATCH (I2C_SSR_ADDRMATCH_MASK)
142 
150 #define DL_I2C_TARGET_STATUS_STALE_TX_FIFO (I2C_SSR_STALE_TXFIFO_MASK)
151 
160 #define DL_I2C_TARGET_STATUS_TX_MODE (I2C_SSR_TXMODE_MASK)
161 
169 #define DL_I2C_TARGET_STATUS_BUS_BUSY (I2C_SSR_BUSBSY_MASK)
170 
179 #define DL_I2C_TARGET_STATUS_RX_MODE (I2C_SSR_RXMODE_MASK)
180 
181 
188 #define DL_I2C_TARGET_STATUS_QUICK_COMMAND_READ_WRITE (I2C_SSR_QCMDRW_MASK)
189 
196 #define DL_I2C_TARGET_STATUS_QUICK_COMMAND_STATUS (I2C_SSR_QCMDST_MASK)
197 
201 #define DL_I2C_TARGET_STATUS_OWN_ADDR_ALTERNATE_MATCHED (I2C_SSR_OAR2SEL_MASK)
202 
206 #define DL_I2C_TARGET_STATUS_TRANSMIT_REQUEST (I2C_SSR_TREQ_MASK)
207 
211 #define DL_I2C_TARGET_STATUS_RECEIVE_REQUEST (I2C_SSR_RREQ_MASK)
212 
221 #define DL_I2C_INTERRUPT_CONTROLLER_RX_DONE (I2C_CPU_INT_IMASK_MRXDONE_SET)
222 
226 #define DL_I2C_INTERRUPT_CONTROLLER_TX_DONE (I2C_CPU_INT_IMASK_MTXDONE_SET)
227 
231 #define DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER \
232  (I2C_CPU_INT_IMASK_MRXFIFOTRG_SET)
233 
237 #define DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER \
238  (I2C_CPU_INT_IMASK_MTXFIFOTRG_SET)
239 
243 #define DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_FULL \
244  (I2C_CPU_INT_IMASK_MRXFIFOFULL_SET)
245 
249 #define DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_EMPTY \
250  (I2C_CPU_INT_IMASK_MTXEMPTY_SET)
251 
255 #define DL_I2C_INTERRUPT_CONTROLLER_NACK (I2C_CPU_INT_IMASK_MNACK_SET)
256 
260 #define DL_I2C_INTERRUPT_CONTROLLER_START (I2C_CPU_INT_IMASK_MSTART_SET)
261 
265 #define DL_I2C_INTERRUPT_CONTROLLER_STOP (I2C_CPU_INT_IMASK_MSTOP_SET)
266 
270 #define DL_I2C_INTERRUPT_CONTROLLER_ARBITRATION_LOST \
271  (I2C_CPU_INT_IMASK_MARBLOST_SET)
272 
276 #define DL_I2C_INTERRUPT_CONTROLLER_EVENT1_DMA_DONE \
277  (I2C_CPU_INT_IMASK_MDMA_DONE_TX_SET)
278 
282 #define DL_I2C_INTERRUPT_CONTROLLER_EVENT2_DMA_DONE \
283  (I2C_CPU_INT_IMASK_MDMA_DONE_RX_SET)
284 
285 
289 #define DL_I2C_INTERRUPT_CONTROLLER_PEC_RX_ERROR \
290  (I2C_CPU_INT_IMASK_MPEC_RX_ERR_SET)
291 
292 
296 #define DL_I2C_INTERRUPT_TARGET_RX_DONE (I2C_CPU_INT_IMASK_SRXDONE_SET)
297 
301 #define DL_I2C_INTERRUPT_TARGET_TX_DONE (I2C_CPU_INT_IMASK_STXDONE_SET)
302 
306 #define DL_I2C_INTERRUPT_TARGET_RXFIFO_TRIGGER \
307  (I2C_CPU_INT_IMASK_SRXFIFOTRG_SET)
308 
312 #define DL_I2C_INTERRUPT_TARGET_TXFIFO_TRIGGER \
313  (I2C_CPU_INT_IMASK_STXFIFOTRG_SET)
314 
318 #define DL_I2C_INTERRUPT_TARGET_RXFIFO_FULL \
319  (I2C_CPU_INT_IMASK_SRXFIFOFULL_SET)
320 
325 #define DL_I2C_INTERRUPT_TARGET_TXFIFO_EMPTY \
326  (I2C_CPU_INT_IMASK_STXEMPTY_SET)
327 
331 #define DL_I2C_INTERRUPT_TARGET_START \
332  (I2C_CPU_INT_IMASK_SSTART_SET)
333 
337 #define DL_I2C_INTERRUPT_TARGET_STOP (I2C_CPU_INT_IMASK_SSTOP_SET)
338 
342 #define DL_I2C_INTERRUPT_TARGET_GENERAL_CALL \
343  (I2C_CPU_INT_IMASK_SGENCALL_SET)
344 
348 #define DL_I2C_INTERRUPT_TARGET_EVENT1_DMA_DONE \
349  (I2C_CPU_INT_IMASK_SDMA_DONE_TX_SET)
350 
354 #define DL_I2C_INTERRUPT_TARGET_EVENT2_DMA_DONE \
355  (I2C_CPU_INT_IMASK_SDMA_DONE_RX_SET)
356 
357 
361 #define DL_I2C_INTERRUPT_TARGET_PEC_RX_ERROR \
362  (I2C_CPU_INT_IMASK_SPEC_RX_ERR_SET)
363 
367 #define DL_I2C_INTERRUPT_TARGET_TXFIFO_UNDERFLOW \
368  (I2C_CPU_INT_IMASK_STX_UNFL_SET)
369 
373 #define DL_I2C_INTERRUPT_TARGET_RXFIFO_OVERFLOW \
374  (I2C_CPU_INT_IMASK_SRX_OVFL_SET)
375 
379 #define DL_I2C_INTERRUPT_TARGET_ARBITRATION_LOST \
380  (I2C_CPU_INT_IMASK_SARBLOST_SET)
381 
386 #define DL_I2C_TARGET_INTERRUPT_OVERFLOW (I2C_CPU_INT_IMASK_INTR_OVFL_SET)
387 
391 #define DL_I2C_INTERRUPT_TIMEOUT_A (I2C_CPU_INT_IMASK_TIMEOUTA_SET)
392 
396 #define DL_I2C_INTERRUPT_TIMEOUT_B (I2C_CPU_INT_IMASK_TIMEOUTB_SET)
397 
398 
407 #define DL_I2C_DMA_INTERRUPT_TARGET_TXFIFO_TRIGGER \
408  (I2C_DMA_TRIG1_IMASK_STXFIFOTRG_SET)
409 
413 #define DL_I2C_DMA_INTERRUPT_TARGET_RXFIFO_TRIGGER \
414  (I2C_DMA_TRIG1_IMASK_SRXFIFOTRG_SET)
415 
419 #define DL_I2C_DMA_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER \
420  (I2C_DMA_TRIG1_IMASK_MTXFIFOTRG_SET)
421 
425 #define DL_I2C_DMA_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER \
426  (I2C_DMA_TRIG1_IMASK_MRXFIFOTRG_SET)
427 
433 #define I2C_getTargetOwnAddressAlternateMask DL_I2C_getTargetOwnAddressAlternateMask
434 
435 /* clang-format on */
436 
438 typedef enum {
440  DL_I2C_DMA_IIDX_TARGET_TXFIFO_TRIGGER = I2C_DMA_TRIG1_IIDX_STAT_MTXFIFOTRG,
442  DL_I2C_DMA_IIDX_TARGET_RXFIFO_TRIGGER = I2C_DMA_TRIG1_IIDX_STAT_MRXFIFOTRG,
444  DL_I2C_DMA_IIDX_CONTROLLER_TXFIFO_TRIGGER =
445  I2C_DMA_TRIG1_IIDX_STAT_STXFIFOTRG,
447  DL_I2C_DMA_IIDX_CONTROLLER_RXFIFO_TRIGGER =
448  I2C_DMA_TRIG1_IIDX_STAT_SRXFIFOTRG
449 } DL_I2C_DMA_IIDX;
450 
452 typedef enum {
454  DL_I2C_EVENT_ROUTE_1 = 0,
456  DL_I2C_EVENT_ROUTE_2 = 12
457 } DL_I2C_EVENT_ROUTE;
458 
460 typedef enum {
462  DL_I2C_CLOCK_BUSCLK = I2C_CLKSEL_BUSCLK_SEL_ENABLE,
464  DL_I2C_CLOCK_MFCLK = I2C_CLKSEL_MFCLK_SEL_ENABLE,
465 } DL_I2C_CLOCK;
466 
468 typedef enum {
470  DL_I2C_CLOCK_DIVIDE_1 = I2C_CLKDIV_RATIO_DIV_BY_1,
472  DL_I2C_CLOCK_DIVIDE_2 = I2C_CLKDIV_RATIO_DIV_BY_2,
474  DL_I2C_CLOCK_DIVIDE_3 = I2C_CLKDIV_RATIO_DIV_BY_3,
476  DL_I2C_CLOCK_DIVIDE_4 = I2C_CLKDIV_RATIO_DIV_BY_4,
478  DL_I2C_CLOCK_DIVIDE_5 = I2C_CLKDIV_RATIO_DIV_BY_5,
480  DL_I2C_CLOCK_DIVIDE_6 = I2C_CLKDIV_RATIO_DIV_BY_6,
482  DL_I2C_CLOCK_DIVIDE_7 = I2C_CLKDIV_RATIO_DIV_BY_7,
484  DL_I2C_CLOCK_DIVIDE_8 = I2C_CLKDIV_RATIO_DIV_BY_8,
485 } DL_I2C_CLOCK_DIVIDE;
486 
488 typedef enum {
490  DL_I2C_TARGET_ADDRESSING_MODE_7_BIT = I2C_SOAR_SMODE_MODE7,
492  DL_I2C_TARGET_ADDRESSING_MODE_10_BIT = I2C_SOAR_SMODE_MODE10,
493 } DL_I2C_TARGET_ADDRESSING_MODE;
494 
496 typedef enum {
499  DL_I2C_TARGET_PEC_STATUS_CHECKED = I2C_TARGET_PECSR_PECSTS_CHECK_SET,
502  DL_I2C_TARGET_PEC_STATUS_NOT_CHECKED =
503  I2C_TARGET_PECSR_PECSTS_CHECK_CLEARED,
504 } DL_I2C_TARGET_PEC_STATUS;
505 
507 typedef enum {
510  DL_I2C_TARGET_PEC_CHECK_ERROR_CLEARED =
511  I2C_TARGET_PECSR_PECSTS_ERROR_CLEARED,
514  DL_I2C_TARGET_PEC_CHECK_ERROR_SET = I2C_TARGET_PECSR_PECSTS_ERROR_SET,
515 } DL_I2C_TARGET_PEC_CHECK_ERROR;
516 
518 typedef enum {
520  DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_5NS = I2C_GFCTL_AGFSEL_AGLIT_5,
522  DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_10NS = I2C_GFCTL_AGFSEL_AGLIT_10,
524  DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_25NS = I2C_GFCTL_AGFSEL_AGLIT_25,
526  DL_I2C_ANALOG_GLITCH_FILTER_WIDTH_50NS = I2C_GFCTL_AGFSEL_AGLIT_50,
527 } DL_I2C_ANALOG_GLITCH_FILTER_WIDTH;
528 
530 typedef enum {
532  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_DISABLED = I2C_GFCTL_DGFSEL_DISABLED,
534  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_1 = I2C_GFCTL_DGFSEL_CLK_1,
536  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_2 = I2C_GFCTL_DGFSEL_CLK_2,
538  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_3 = I2C_GFCTL_DGFSEL_CLK_3,
540  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_4 = I2C_GFCTL_DGFSEL_CLK_4,
542  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_8 = I2C_GFCTL_DGFSEL_CLK_8,
544  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_16 = I2C_GFCTL_DGFSEL_CLK_16,
546  DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH_CLOCKS_31 = I2C_GFCTL_DGFSEL_CLK_31,
547 } DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH;
548 
550 typedef enum {
552  DL_I2C_CONTROLLER_DIRECTION_TX = I2C_MSA_DIR_TRANSMIT,
554  DL_I2C_CONTROLLER_DIRECTION_RX = I2C_MSA_DIR_RECEIVE,
555 } DL_I2C_CONTROLLER_DIRECTION;
556 
558 typedef enum {
560  DL_I2C_CONTROLLER_ADDRESSING_MODE_7_BIT = I2C_MSA_MMODE_MODE7,
562  DL_I2C_CONTROLLER_ADDRESSING_MODE_10_BIT = I2C_MSA_MMODE_MODE10,
563 } DL_I2C_CONTROLLER_ADDRESSING_MODE;
564 
566 typedef enum {
569  DL_I2C_CONTROLLER_PEC_STATUS_CHECKED =
570  I2C_CONTROLLER_PECSR_PECSTS_CHECK_SET,
573  DL_I2C_CONTROLLER_PEC_STATUS_NOT_CHECKED =
574  I2C_CONTROLLER_PECSR_PECSTS_CHECK_CLEARED,
575 } DL_I2C_CONTROLLER_PEC_STATUS;
576 
578 typedef enum {
581  DL_I2C_CONTROLLER_PEC_CHECK_ERROR_SET =
582  I2C_CONTROLLER_PECSR_PECSTS_ERROR_SET,
585  DL_I2C_CONTROLLER_PEC_CHECK_ERROR_CLEARED =
586  I2C_CONTROLLER_PECSR_PECSTS_ERROR_CLEARED,
587 } DL_I2C_CONTROLLER_PEC_CHECK_ERROR;
588 
590 typedef enum {
592  DL_I2C_CONTROLLER_SCL_HIGH = I2C_MBMON_SCL_SET,
594  DL_I2C_CONTROLLER_SCL_LOW = I2C_MBMON_SCL_CLEARED,
595 } DL_I2C_CONTROLLER_SCL;
596 
598 typedef enum {
600  DL_I2C_CONTROLLER_SDA_HIGH = I2C_MBMON_SDA_SET,
602  DL_I2C_CONTROLLER_SDA_LOW = I2C_MBMON_SDA_CLEARED,
603 } DL_I2C_CONTROLLER_SDA;
604 
606 typedef enum {
608  DL_I2C_CONTROLLER_START_ENABLE = I2C_MCTR_START_ENABLE,
610  DL_I2C_CONTROLLER_START_DISABLE = I2C_MCTR_START_DISABLE,
611 } DL_I2C_CONTROLLER_START;
612 
614 typedef enum {
616  DL_I2C_CONTROLLER_STOP_ENABLE = I2C_MCTR_STOP_ENABLE,
618  DL_I2C_CONTROLLER_STOP_DISABLE = I2C_MCTR_STOP_DISABLE,
619 } DL_I2C_CONTROLLER_STOP;
620 
622 typedef enum {
624  DL_I2C_CONTROLLER_ACK_ENABLE = I2C_MCTR_ACK_ENABLE,
626  DL_I2C_CONTROLLER_ACK_DISABLE = I2C_MCTR_ACK_DISABLE,
627 } DL_I2C_CONTROLLER_ACK;
628 
630 typedef enum {
632  DL_I2C_TX_FIFO_LEVEL_EMPTY = I2C_MFIFOCTL_TXTRIG_EMPTY,
634  DL_I2C_TX_FIFO_LEVEL_BYTES_1 = I2C_MFIFOCTL_TXTRIG_LEVEL_1,
636  DL_I2C_TX_FIFO_LEVEL_BYTES_2 = I2C_MFIFOCTL_TXTRIG_LEVEL_2,
638  DL_I2C_TX_FIFO_LEVEL_BYTES_3 = I2C_MFIFOCTL_TXTRIG_LEVEL_3,
640  DL_I2C_TX_FIFO_LEVEL_BYTES_4 = I2C_MFIFOCTL_TXTRIG_LEVEL_4,
642  DL_I2C_TX_FIFO_LEVEL_BYTES_5 = I2C_MFIFOCTL_TXTRIG_LEVEL_5,
644  DL_I2C_TX_FIFO_LEVEL_BYTES_6 = I2C_MFIFOCTL_TXTRIG_LEVEL_6,
646  DL_I2C_TX_FIFO_LEVEL_BYTES_7 = I2C_MFIFOCTL_TXTRIG_LEVEL_7,
647 } DL_I2C_TX_FIFO_LEVEL;
648 
650 typedef enum {
652  DL_I2C_RX_FIFO_LEVEL_BYTES_1 = I2C_MFIFOCTL_RXTRIG_LEVEL_1,
654  DL_I2C_RX_FIFO_LEVEL_BYTES_2 = I2C_MFIFOCTL_RXTRIG_LEVEL_2,
656  DL_I2C_RX_FIFO_LEVEL_BYTES_3 = I2C_MFIFOCTL_RXTRIG_LEVEL_3,
658  DL_I2C_RX_FIFO_LEVEL_BYTES_4 = I2C_MFIFOCTL_RXTRIG_LEVEL_4,
660  DL_I2C_RX_FIFO_LEVEL_BYTES_5 = I2C_MFIFOCTL_RXTRIG_LEVEL_5,
662  DL_I2C_RX_FIFO_LEVEL_BYTES_6 = I2C_MFIFOCTL_RXTRIG_LEVEL_6,
664  DL_I2C_RX_FIFO_LEVEL_BYTES_7 = I2C_MFIFOCTL_RXTRIG_LEVEL_7,
666  DL_I2C_RX_FIFO_LEVEL_BYTES_8 = I2C_MFIFOCTL_RXTRIG_LEVEL_8,
667 } DL_I2C_RX_FIFO_LEVEL;
668 
670 typedef enum {
672  DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE_ACK = I2C_SACKCTL_ACKOVAL_DISABLE,
674  DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE_NACK = I2C_SACKCTL_ACKOVAL_ENABLE,
675 } DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE;
676 
678 typedef enum {
680  DL_I2C_IIDX_NO_INT = I2C_CPU_INT_IIDX_STAT_NO_INTR,
682  DL_I2C_IIDX_CONTROLLER_RX_DONE = I2C_CPU_INT_IIDX_STAT_MRXDONEFG,
684  DL_I2C_IIDX_CONTROLLER_TX_DONE = I2C_CPU_INT_IIDX_STAT_MTXDONEFG,
686  DL_I2C_IIDX_CONTROLLER_RXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_MRXFIFOTRG,
688  DL_I2C_IIDX_CONTROLLER_TXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_MTXFIFOTRG,
690  DL_I2C_IIDX_CONTROLLER_RXFIFO_FULL = I2C_CPU_INT_IIDX_STAT_MRXFIFOFULL,
692  DL_I2C_IIDX_CONTROLLER_TXFIFO_EMPTY = I2C_CPU_INT_IIDX_STAT_MTX_EMPTY,
694  DL_I2C_IIDX_CONTROLLER_NACK = I2C_CPU_INT_IIDX_STAT_MNACKFG,
696  DL_I2C_IIDX_CONTROLLER_START = I2C_CPU_INT_IIDX_STAT_MSTARTFG,
698  DL_I2C_IIDX_CONTROLLER_STOP = I2C_CPU_INT_IIDX_STAT_MSTOPFG,
700  DL_I2C_IIDX_CONTROLLER_ARBITRATION_LOST = I2C_CPU_INT_IIDX_STAT_MARBLOSTFG,
702  DL_I2C_IIDX_CONTROLLER_EVENT1_DMA_DONE =
703  I2C_CPU_INT_IIDX_STAT_MDMA_DONE_TX,
705  DL_I2C_IIDX_CONTROLLER_EVENT2_DMA_DONE =
706  I2C_CPU_INT_IIDX_STAT_MDMA_DONE_RX,
707 
709  DL_I2C_IIDX_CONTROLLER_PEC_RX_ERROR = I2C_CPU_INT_IIDX_STAT_MPEC_RX_ERR,
711  DL_I2C_IIDX_TIMEOUT_A = I2C_CPU_INT_IIDX_STAT_TIMEOUTA,
713  DL_I2C_IIDX_TIMEOUT_B = I2C_CPU_INT_IIDX_STAT_TIMEOUTB,
714 
716  DL_I2C_IIDX_TARGET_RX_DONE = I2C_CPU_INT_IIDX_STAT_SRXDONEFG,
718  DL_I2C_IIDX_TARGET_TX_DONE = I2C_CPU_INT_IIDX_STAT_STXDONEFG,
720  DL_I2C_IIDX_TARGET_RXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_SRXFIFOTRG,
722  DL_I2C_IIDX_TARGET_TXFIFO_TRIGGER = I2C_CPU_INT_IIDX_STAT_STXFIFOTRG,
724  DL_I2C_IIDX_TARGET_RXFIFO_FULL = I2C_CPU_INT_IIDX_STAT_SRXFIFOFULL,
727  DL_I2C_IIDX_TARGET_TXFIFO_EMPTY = I2C_CPU_INT_IIDX_STAT_STXEMPTY,
729  DL_I2C_IIDX_TARGET_START = I2C_CPU_INT_IIDX_STAT_SSTARTFG,
731  DL_I2C_IIDX_TARGET_STOP = I2C_CPU_INT_IIDX_STAT_SSTOPFG,
733  DL_I2C_IIDX_TARGET_GENERAL_CALL = I2C_CPU_INT_IIDX_STAT_SGENCALL,
735  DL_I2C_IIDX_TARGET_EVENT1_DMA_DONE = I2C_CPU_INT_IIDX_STAT_SDMA_DONE_TX,
737  DL_I2C_IIDX_TARGET_EVENT2_DMA_DONE = I2C_CPU_INT_IIDX_STAT_SDMA_DONE_RX,
738 
740  DL_I2C_IIDX_TARGET_PEC_RX_ERROR = I2C_CPU_INT_IIDX_STAT_SPEC_RX_ERR,
742  DL_I2C_IIDX_TARGET_TXFIFO_UNDERFLOW = I2C_CPU_INT_IIDX_STAT_STX_UNFL,
744  DL_I2C_IIDX_TARGET_RXFIFO_OVERFLOW = I2C_CPU_INT_IIDX_STAT_SRX_OVFL,
746  DL_I2C_IIDX_TARGET_ARBITRATION_LOST = I2C_CPU_INT_IIDX_STAT_SARBLOST,
748  DL_I2C_IIDX_INTERRUPT_OVERFLOW = I2C_CPU_INT_IIDX_STAT_INTR_OVFL,
749 
750 } DL_I2C_IIDX;
751 
755 typedef struct {
757  DL_I2C_CLOCK clockSel;
759  DL_I2C_CLOCK_DIVIDE divideRatio;
760 } DL_I2C_ClockConfig;
761 
770 void DL_I2C_setClockConfig(I2C_Regs *i2c, const DL_I2C_ClockConfig *config);
771 
780 void DL_I2C_getClockConfig(const I2C_Regs *i2c, DL_I2C_ClockConfig *config);
781 
792 uint16_t DL_I2C_fillControllerTXFIFO(
793  I2C_Regs *i2c, const uint8_t *buffer, uint16_t count);
794 
800 void DL_I2C_flushControllerTXFIFO(I2C_Regs *i2c);
801 
807 void DL_I2C_flushControllerRXFIFO(I2C_Regs *i2c);
808 
819 __STATIC_INLINE bool DL_I2C_isControllerTXFIFOFull(const I2C_Regs *i2c)
820 {
821  return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFIFOCNT_MASK) ==
822  I2C_MFIFOSR_TXFIFOCNT_MINIMUM);
823 }
824 
835 __STATIC_INLINE bool DL_I2C_isControllerTXFIFOEmpty(const I2C_Regs *i2c)
836 {
837  return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFIFOCNT_MASK) ==
838  DL_I2C_TX_FIFO_COUNT_MAXIMUM);
839 }
840 
851 __STATIC_INLINE bool DL_I2C_isControllerRXFIFOEmpty(const I2C_Regs *i2c)
852 {
853  return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_RXFIFOCNT_MASK) ==
854  I2C_MFIFOSR_RXFIFOCNT_MINIMUM);
855 }
856 
864 __STATIC_INLINE void DL_I2C_resetControllerTransfer(I2C_Regs *i2c)
865 {
866  // Resets all Controller functionality
867  i2c->MASTER.MCTR = 0x00;
868 }
869 
882 __STATIC_INLINE void DL_I2C_startControllerTransfer(I2C_Regs *i2c,
883  uint32_t targetAddr, DL_I2C_CONTROLLER_DIRECTION direction,
884  uint16_t length)
885 {
886  // Specify target address and read/write mode
887  DL_Common_updateReg(&i2c->MASTER.MSA,
888  ((targetAddr << I2C_MSA_SADDR_OFS) | (uint32_t) direction),
889  (I2C_MSA_SADDR_MASK | I2C_MSA_DIR_MASK));
890 
891  // STOP bit is generated after burst length number of bytes transferred
892  DL_Common_updateReg(&i2c->MASTER.MCTR,
893  (((uint32_t) length << I2C_MCTR_MBLEN_OFS) | I2C_MCTR_BURSTRUN_ENABLE |
894  I2C_MCTR_START_ENABLE | I2C_MCTR_STOP_ENABLE),
895  (I2C_MCTR_MBLEN_MASK | I2C_MCTR_BURSTRUN_MASK | I2C_MCTR_START_MASK |
896  I2C_MCTR_STOP_MASK));
897 }
898 
913 __STATIC_INLINE void DL_I2C_startControllerTransferAdvanced(I2C_Regs *i2c,
914  uint32_t targetAddr, DL_I2C_CONTROLLER_DIRECTION direction,
915  uint16_t length, DL_I2C_CONTROLLER_START start,
916  DL_I2C_CONTROLLER_STOP stop, DL_I2C_CONTROLLER_ACK ack)
917 {
918  // Specify target address and read/write mode
919  DL_Common_updateReg(&i2c->MASTER.MSA,
920  ((targetAddr << I2C_MSA_SADDR_OFS) | (uint32_t) direction),
921  (I2C_MSA_SADDR_MASK | I2C_MSA_DIR_MASK));
922 
923  DL_Common_updateReg(&i2c->MASTER.MCTR,
924  (((uint32_t) length << I2C_MCTR_MBLEN_OFS) | I2C_MCTR_BURSTRUN_ENABLE |
925  (uint32_t) start | (uint32_t) stop | (uint32_t) ack),
926  (I2C_MCTR_MBLEN_MASK | I2C_MCTR_BURSTRUN_MASK | I2C_MCTR_START_MASK |
927  I2C_MCTR_STOP_MASK | I2C_MCTR_ACK_MASK));
928 }
929 
940 __STATIC_INLINE bool DL_I2C_isTargetTXFIFOFull(const I2C_Regs *i2c)
941 {
942  return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFIFOCNT_MASK) ==
943  I2C_SFIFOSR_TXFIFOCNT_MINIMUM);
944 }
945 
956 __STATIC_INLINE bool DL_I2C_isTargetTXFIFOEmpty(const I2C_Regs *i2c)
957 {
958  return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFIFOCNT_MASK) ==
959  DL_I2C_TX_FIFO_COUNT_MAXIMUM);
960 }
961 
972 __STATIC_INLINE bool DL_I2C_isTargetRXFIFOEmpty(const I2C_Regs *i2c)
973 {
974  return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_RXFIFOCNT_MASK) ==
975  I2C_SFIFOSR_RXFIFOCNT_MINIMUM);
976 }
977 
987 uint8_t DL_I2C_fillTargetTXFIFO(
988  I2C_Regs *i2c, const uint8_t *buffer, uint8_t count);
989 
995 void DL_I2C_flushTargetTXFIFO(I2C_Regs *i2c);
996 
1002 void DL_I2C_flushTargetRXFIFO(I2C_Regs *i2c);
1003 
1016 void DL_I2C_transmitTargetDataBlocking(I2C_Regs *i2c, uint8_t data);
1017 
1031 bool DL_I2C_transmitTargetDataCheck(I2C_Regs *i2c, uint8_t data);
1032 
1043 uint8_t DL_I2C_receiveTargetDataBlocking(const I2C_Regs *i2c);
1044 
1058 bool DL_I2C_receiveTargetDataCheck(const I2C_Regs *i2c, uint8_t *buffer);
1059 
1069 __STATIC_INLINE void DL_I2C_enablePower(I2C_Regs *i2c)
1070 {
1071  i2c->GPRCM.PWREN = (I2C_PWREN_KEY_UNLOCK_W | I2C_PWREN_ENABLE_ENABLE);
1072 }
1073 
1084 __STATIC_INLINE void DL_I2C_disablePower(I2C_Regs *i2c)
1085 {
1086  i2c->GPRCM.PWREN = (I2C_PWREN_KEY_UNLOCK_W | I2C_PWREN_ENABLE_DISABLE);
1087 }
1088 
1105 __STATIC_INLINE bool DL_I2C_isPowerEnabled(const I2C_Regs *i2c)
1106 {
1107  return (
1108  (i2c->GPRCM.PWREN & I2C_PWREN_ENABLE_MASK) == I2C_PWREN_ENABLE_ENABLE);
1109 }
1110 
1116 __STATIC_INLINE void DL_I2C_reset(I2C_Regs *i2c)
1117 {
1118  i2c->GPRCM.RSTCTL =
1119  (I2C_RSTCTL_KEY_UNLOCK_W | I2C_RSTCTL_RESETSTKYCLR_CLR |
1120  I2C_RSTCTL_RESETASSERT_ASSERT);
1121 }
1122 
1132 __STATIC_INLINE bool DL_I2C_isReset(const I2C_Regs *i2c)
1133 {
1134  return ((i2c->GPRCM.STAT & I2C_STAT_RESETSTKY_MASK) ==
1135  I2C_STAT_RESETSTKY_RESET);
1136 }
1137 
1148 __STATIC_INLINE void DL_I2C_selectClockSource(
1149  I2C_Regs *i2c, DL_I2C_CLOCK clockSource)
1150 {
1151  DL_Common_updateReg(&i2c->CLKSEL, (uint32_t) clockSource,
1152  I2C_CLKSEL_BUSCLK_SEL_MASK | I2C_CLKSEL_MFCLK_SEL_MASK);
1153 }
1154 
1163 __STATIC_INLINE void DL_I2C_selectClockDivider(
1164  I2C_Regs *i2c, DL_I2C_CLOCK_DIVIDE clockDivider)
1165 {
1166  DL_Common_updateReg(
1167  &i2c->CLKDIV, (uint32_t) clockDivider, I2C_CLKDIV_RATIO_MASK);
1168 }
1169 
1181 __STATIC_INLINE DL_I2C_ANALOG_GLITCH_FILTER_WIDTH
1182 DL_I2C_getAnalogGlitchFilterPulseWidth(const I2C_Regs *i2c)
1183 {
1184  uint32_t filterWidth = i2c->GFCTL & I2C_GFCTL_AGFSEL_MASK;
1185 
1186  return (DL_I2C_ANALOG_GLITCH_FILTER_WIDTH)(filterWidth);
1187 }
1188 
1198 __STATIC_INLINE void DL_I2C_setAnalogGlitchFilterPulseWidth(
1199  I2C_Regs *i2c, DL_I2C_ANALOG_GLITCH_FILTER_WIDTH filterWidth)
1200 {
1201  DL_Common_updateReg(
1202  &i2c->GFCTL, (uint32_t) filterWidth, I2C_GFCTL_AGFSEL_MASK);
1203 }
1204 
1217 __STATIC_INLINE DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH
1218 DL_I2C_getDigitalGlitchFilterPulseWidth(const I2C_Regs *i2c)
1219 {
1220  uint32_t filterWidth = i2c->GFCTL & I2C_GFCTL_DGFSEL_MASK;
1221 
1222  return (DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH)(filterWidth);
1223 }
1224 
1235 __STATIC_INLINE void DL_I2C_setDigitalGlitchFilterPulseWidth(
1236  I2C_Regs *i2c, DL_I2C_DIGITAL_GLITCH_FILTER_WIDTH filterWidth)
1237 {
1238  DL_Common_updateReg(
1239  &i2c->GFCTL, (uint32_t) filterWidth, I2C_GFCTL_DGFSEL_MASK);
1240 }
1241 
1247 __STATIC_INLINE void DL_I2C_disableAnalogGlitchFilter(I2C_Regs *i2c)
1248 {
1249  i2c->GFCTL &= ~(I2C_GFCTL_AGFEN_MASK);
1250 }
1251 
1262 __STATIC_INLINE bool DL_I2C_isAnalogGlitchFilterEnabled(const I2C_Regs *i2c)
1263 {
1264  return ((i2c->GFCTL & I2C_GFCTL_AGFEN_MASK) == I2C_GFCTL_AGFEN_ENABLE);
1265 }
1266 
1272 __STATIC_INLINE void DL_I2C_enableAnalogGlitchFilter(I2C_Regs *i2c)
1273 {
1274  i2c->GFCTL |= I2C_GFCTL_AGFEN_ENABLE;
1275 }
1276 
1286 __STATIC_INLINE DL_I2C_CONTROLLER_DIRECTION DL_I2C_getControllerDirection(
1287  const I2C_Regs *i2c)
1288 {
1289  uint32_t direction = i2c->MASTER.MSA & I2C_MSA_DIR_MASK;
1290 
1291  return (DL_I2C_CONTROLLER_DIRECTION)(direction);
1292 }
1293 
1302 __STATIC_INLINE void DL_I2C_setControllerDirection(
1303  I2C_Regs *i2c, DL_I2C_CONTROLLER_DIRECTION direction)
1304 {
1305  DL_Common_updateReg(
1306  &i2c->MASTER.MSA, (uint32_t) direction, I2C_MSA_DIR_MASK);
1307 }
1308 
1325 __STATIC_INLINE uint32_t DL_I2C_getTargetAddress(const I2C_Regs *i2c)
1326 {
1327  return ((i2c->MASTER.MSA & I2C_MSA_SADDR_MASK) >> I2C_MSA_SADDR_OFS);
1328 }
1329 
1343 __STATIC_INLINE void DL_I2C_setTargetAddress(
1344  I2C_Regs *i2c, uint32_t targetAddress)
1345 {
1346  DL_Common_updateReg(&i2c->MASTER.MSA, (targetAddress << I2C_MSA_SADDR_OFS),
1347  I2C_MSA_SADDR_MASK);
1348 }
1349 
1360 __STATIC_INLINE DL_I2C_CONTROLLER_ADDRESSING_MODE
1361 DL_I2C_getControllerAddressingMode(const I2C_Regs *i2c)
1362 {
1363  uint32_t mode = i2c->MASTER.MSA & I2C_MSA_MMODE_MASK;
1364 
1365  return (DL_I2C_CONTROLLER_ADDRESSING_MODE)(mode);
1366 }
1367 
1378 __STATIC_INLINE void DL_I2C_setControllerAddressingMode(
1379  I2C_Regs *i2c, DL_I2C_CONTROLLER_ADDRESSING_MODE mode)
1380 {
1381  DL_Common_updateReg(&i2c->MASTER.MSA, (uint32_t) mode, I2C_MSA_MMODE_MASK);
1382 }
1383 
1389 __STATIC_INLINE void DL_I2C_disableControllerACKOverride(I2C_Regs *i2c)
1390 {
1391  i2c->MASTER.MCTR &= ~(I2C_MCTR_MACKOEN_MASK);
1392 }
1393 
1404 __STATIC_INLINE bool DL_I2C_isControllerACKOverrideEnabled(const I2C_Regs *i2c)
1405 {
1406  return (
1407  (i2c->MASTER.MCTR & I2C_MCTR_MACKOEN_MASK) == I2C_MCTR_MACKOEN_ENABLE);
1408 }
1409 
1425 __STATIC_INLINE void DL_I2C_enableControllerACKOverride(I2C_Regs *i2c)
1426 {
1427  i2c->MASTER.MCTR |= I2C_MCTR_MACKOEN_ENABLE;
1428 }
1429 
1435 __STATIC_INLINE void DL_I2C_disableControllerReadOnTXEmpty(I2C_Regs *i2c)
1436 {
1437  i2c->MASTER.MCTR &= ~(I2C_MCTR_RD_ON_TXEMPTY_MASK);
1438 }
1439 
1450 __STATIC_INLINE bool DL_I2C_isControllerReadOnTXEmptyEnabled(
1451  const I2C_Regs *i2c)
1452 {
1453  return ((i2c->MASTER.MCTR & I2C_MCTR_RD_ON_TXEMPTY_MASK) ==
1454  I2C_MCTR_RD_ON_TXEMPTY_ENABLE);
1455 }
1456 
1474 __STATIC_INLINE void DL_I2C_enableControllerReadOnTXEmpty(I2C_Regs *i2c)
1475 {
1476  i2c->MASTER.MCTR |= I2C_MCTR_RD_ON_TXEMPTY_ENABLE;
1477 }
1478 
1488 __STATIC_INLINE uint32_t DL_I2C_getControllerPECCountValue(const I2C_Regs *i2c)
1489 {
1490  return (i2c->MASTER.CONTROLLER_I2CPECCTL &
1491  I2C_CONTROLLER_I2CPECCTL_PECCNT_MASK);
1492 }
1493 
1504 __STATIC_INLINE void DL_I2C_setControllerPECCountValue(
1505  I2C_Regs *i2c, uint32_t count)
1506 {
1507  DL_Common_updateReg(&i2c->MASTER.CONTROLLER_I2CPECCTL, count,
1508  I2C_CONTROLLER_I2CPECCTL_PECCNT_MASK);
1509 }
1510 
1516 __STATIC_INLINE void DL_I2C_disableControllerPEC(I2C_Regs *i2c)
1517 {
1518  i2c->MASTER.CONTROLLER_I2CPECCTL &= ~(I2C_CONTROLLER_I2CPECCTL_PECEN_MASK);
1519 }
1520 
1532 __STATIC_INLINE bool DL_I2C_isControllerPECEnabled(const I2C_Regs *i2c)
1533 {
1534  return ((i2c->MASTER.CONTROLLER_I2CPECCTL &
1535  I2C_CONTROLLER_I2CPECCTL_PECEN_MASK) ==
1536  I2C_CONTROLLER_I2CPECCTL_PECEN_ENABLE);
1537 }
1538 
1553 __STATIC_INLINE void DL_I2C_enableControllerPEC(I2C_Regs *i2c)
1554 {
1555  i2c->MASTER.CONTROLLER_I2CPECCTL |= I2C_CONTROLLER_I2CPECCTL_PECEN_ENABLE;
1556 }
1557 
1568 __STATIC_INLINE uint32_t DL_I2C_getControllerCurrentPECCount(
1569  const I2C_Regs *i2c)
1570 {
1571  return (
1572  i2c->MASTER.CONTROLLER_PECSR & I2C_CONTROLLER_PECSR_PECSTS_CHECK_MASK);
1573 }
1574 
1587 __STATIC_INLINE DL_I2C_CONTROLLER_PEC_STATUS
1588 DL_I2C_getControllerPECCheckedStatus(const I2C_Regs *i2c)
1589 {
1590  uint32_t status =
1591  i2c->MASTER.CONTROLLER_PECSR & I2C_CONTROLLER_PECSR_PECSTS_CHECK_MASK;
1592 
1593  return (DL_I2C_CONTROLLER_PEC_STATUS)(status);
1594 }
1595 
1608 __STATIC_INLINE DL_I2C_CONTROLLER_PEC_CHECK_ERROR
1609 DL_I2C_getControllerPECCheckError(const I2C_Regs *i2c)
1610 {
1611  uint32_t error =
1612  i2c->MASTER.CONTROLLER_PECSR & I2C_CONTROLLER_PECSR_PECSTS_ERROR_MASK;
1613 
1614  return (DL_I2C_CONTROLLER_PEC_CHECK_ERROR)(error);
1615 }
1616 
1622 __STATIC_INLINE void DL_I2C_disableControllerBurst(I2C_Regs *i2c)
1623 {
1624  i2c->MASTER.MCTR &= ~(I2C_MCTR_BURSTRUN_MASK);
1625 }
1626 
1637 __STATIC_INLINE bool DL_I2C_isControllerBurstEnabled(const I2C_Regs *i2c)
1638 {
1639  return ((i2c->GFCTL & I2C_MCTR_BURSTRUN_MASK) == I2C_MCTR_BURSTRUN_ENABLE);
1640 }
1641 
1647 __STATIC_INLINE void DL_I2C_enableControllerBurst(I2C_Regs *i2c)
1648 {
1649  i2c->MASTER.MCTR |= I2C_MCTR_BURSTRUN_ENABLE;
1650 }
1651 
1657 __STATIC_INLINE void DL_I2C_disableStartCondition(I2C_Regs *i2c)
1658 {
1659  i2c->MASTER.MCTR &= ~(I2C_MCTR_START_MASK);
1660 }
1661 
1672 __STATIC_INLINE bool DL_I2C_isStartConditionEnabled(const I2C_Regs *i2c)
1673 {
1674  return ((i2c->MASTER.MCTR & I2C_MCTR_START_MASK) == I2C_MCTR_START_ENABLE);
1675 }
1676 
1682 __STATIC_INLINE void DL_I2C_enableStartCondition(I2C_Regs *i2c)
1683 {
1684  i2c->MASTER.MCTR |= I2C_MCTR_START_ENABLE;
1685 }
1686 
1692 __STATIC_INLINE void DL_I2C_disableStopCondition(I2C_Regs *i2c)
1693 {
1694  i2c->MASTER.MCTR &= ~(I2C_MCTR_STOP_MASK);
1695 }
1696 
1707 __STATIC_INLINE bool DL_I2C_isStopConditionEnabled(const I2C_Regs *i2c)
1708 {
1709  return ((i2c->MASTER.MCTR & I2C_MCTR_STOP_MASK) == I2C_MCTR_STOP_ENABLE);
1710 }
1711 
1717 __STATIC_INLINE void DL_I2C_enableStopCondition(I2C_Regs *i2c)
1718 {
1719  i2c->MASTER.MCTR |= I2C_MCTR_STOP_ENABLE;
1720 }
1721 
1731 __STATIC_INLINE void DL_I2C_disableControllerACK(I2C_Regs *i2c)
1732 {
1733  i2c->MASTER.MCTR &= ~(I2C_MCTR_ACK_MASK);
1734 }
1735 
1747 __STATIC_INLINE bool DL_I2C_isControllerACKEnabled(const I2C_Regs *i2c)
1748 {
1749  return ((i2c->MASTER.MCTR & I2C_MCTR_ACK_MASK) == I2C_MCTR_ACK_ENABLE);
1750 }
1751 
1761 __STATIC_INLINE void DL_I2C_enableControllerACK(I2C_Regs *i2c)
1762 {
1763  i2c->MASTER.MCTR |= I2C_MCTR_ACK_MASK;
1764 }
1765 
1775 __STATIC_INLINE uint32_t DL_I2C_getTransactionLength(const I2C_Regs *i2c)
1776 {
1777  return ((i2c->MASTER.MCTR & I2C_MCTR_MBLEN_MASK) >> I2C_MCTR_MBLEN_OFS);
1778 }
1779 
1787 __STATIC_INLINE void DL_I2C_setTransactionLength(
1788  I2C_Regs *i2c, uint32_t length)
1789 {
1790  DL_Common_updateReg(&i2c->MASTER.MCTR, (length << I2C_MCTR_MBLEN_OFS),
1791  I2C_MCTR_MBLEN_MASK);
1792 }
1793 
1803 __STATIC_INLINE uint32_t DL_I2C_getControllerStatus(const I2C_Regs *i2c)
1804 {
1805  return (i2c->MASTER.MSR);
1806 }
1807 
1817 __STATIC_INLINE uint16_t DL_I2C_getTransactionCount(const I2C_Regs *i2c)
1818 {
1819  return ((uint16_t)(
1820  (i2c->MASTER.MSR & I2C_MSR_MBCNT_MASK) >> I2C_MSR_MBCNT_OFS));
1821 }
1822 
1834 __STATIC_INLINE uint8_t DL_I2C_receiveControllerData(const I2C_Regs *i2c)
1835 {
1836  return ((uint8_t)(i2c->MASTER.MRXDATA & I2C_MRXDATA_VALUE_MASK));
1837 }
1838 
1848 __STATIC_INLINE void DL_I2C_transmitControllerData(I2C_Regs *i2c, uint8_t data)
1849 {
1850  i2c->MASTER.MTXDATA = data;
1851 }
1852 
1874 __STATIC_INLINE uint8_t DL_I2C_getTimerPeriod(const I2C_Regs *i2c)
1875 {
1876  return ((uint8_t)(i2c->MASTER.MTPR & I2C_MTPR_TPR_MASK));
1877 }
1878 
1898 __STATIC_INLINE void DL_I2C_setTimerPeriod(I2C_Regs *i2c, uint8_t period)
1899 {
1900  i2c->MASTER.MTPR = period;
1901 }
1902 
1908 __STATIC_INLINE void DL_I2C_disableLoopbackMode(I2C_Regs *i2c)
1909 {
1910  i2c->MASTER.MCR &= ~(I2C_MCR_LPBK_MASK);
1911 }
1912 
1923 __STATIC_INLINE bool DL_I2C_isLoopbackModeEnabled(const I2C_Regs *i2c)
1924 {
1925  return ((i2c->MASTER.MCR & I2C_MCR_LPBK_MASK) == I2C_MCR_LPBK_ENABLE);
1926 }
1927 
1933 __STATIC_INLINE void DL_I2C_enableLoopbackMode(I2C_Regs *i2c)
1934 {
1935  i2c->MASTER.MCR |= I2C_MCR_LPBK_ENABLE;
1936 }
1937 
1943 __STATIC_INLINE void DL_I2C_disableMultiControllerMode(I2C_Regs *i2c)
1944 {
1945  i2c->MASTER.MCR &= ~(I2C_MCR_MMST_MASK);
1946 }
1947 
1958 __STATIC_INLINE bool DL_I2C_isMultiControllerModeEnabled(const I2C_Regs *i2c)
1959 {
1960  return ((i2c->MASTER.MCR & I2C_MCR_MMST_MASK) == I2C_MCR_MMST_ENABLE);
1961 }
1962 
1972 __STATIC_INLINE void DL_I2C_enableMultiControllerMode(I2C_Regs *i2c)
1973 {
1974  i2c->MASTER.MCR |= I2C_MCR_MMST_ENABLE;
1975 }
1976 
1982 __STATIC_INLINE void DL_I2C_disableController(I2C_Regs *i2c)
1983 {
1984  i2c->MASTER.MCR &= ~(I2C_MCR_ACTIVE_MASK);
1985 }
1986 
1997 __STATIC_INLINE bool DL_I2C_isControllerEnabled(const I2C_Regs *i2c)
1998 {
1999  return ((i2c->MASTER.MCR & I2C_MCR_ACTIVE_MASK) == I2C_MCR_ACTIVE_ENABLE);
2000 }
2001 
2010 __STATIC_INLINE void DL_I2C_enableController(I2C_Regs *i2c)
2011 {
2012  i2c->MASTER.MCR |= I2C_MCR_ACTIVE_ENABLE;
2013 }
2014 
2024 __STATIC_INLINE void DL_I2C_disableControllerClockStretching(I2C_Regs *i2c)
2025 {
2026  i2c->MASTER.MCR &= ~(I2C_MCR_CLKSTRETCH_MASK);
2027 }
2028 
2039 __STATIC_INLINE bool DL_I2C_isControllerClockStretchingEnabled(
2040  const I2C_Regs *i2c)
2041 {
2042  return ((i2c->MASTER.MCR & I2C_MCR_CLKSTRETCH_MASK) ==
2043  I2C_MCR_CLKSTRETCH_ENABLE);
2044 }
2045 
2055 __STATIC_INLINE void DL_I2C_enableControllerClockStretching(I2C_Regs *i2c)
2056 {
2057  i2c->MASTER.MCR |= I2C_MCR_CLKSTRETCH_ENABLE;
2058 }
2059 
2069 __STATIC_INLINE DL_I2C_CONTROLLER_SCL DL_I2C_getSCLStatus(const I2C_Regs *i2c)
2070 {
2071  uint32_t sclStatus = i2c->MASTER.MBMON & I2C_MBMON_SCL_MASK;
2072 
2073  return (DL_I2C_CONTROLLER_SCL)(sclStatus);
2074 }
2075 
2085 __STATIC_INLINE DL_I2C_CONTROLLER_SDA DL_I2C_getSDAStatus(const I2C_Regs *i2c)
2086 {
2087  uint32_t sdaStatus = i2c->MASTER.MBMON & I2C_MBMON_SDA_MASK;
2088 
2089  return (DL_I2C_CONTROLLER_SDA)(sdaStatus);
2090 }
2091 
2101 __STATIC_INLINE DL_I2C_TX_FIFO_LEVEL DL_I2C_getControllerTXFIFOThreshold(
2102  const I2C_Regs *i2c)
2103 {
2104  uint32_t level = i2c->MASTER.MFIFOCTL & I2C_MFIFOCTL_TXTRIG_MASK;
2105 
2106  return (DL_I2C_TX_FIFO_LEVEL)(level);
2107 }
2108 
2117 __STATIC_INLINE void DL_I2C_setControllerTXFIFOThreshold(
2118  I2C_Regs *i2c, DL_I2C_TX_FIFO_LEVEL level)
2119 {
2120  DL_Common_updateReg(
2121  &i2c->MASTER.MFIFOCTL, (uint32_t) level, I2C_MFIFOCTL_TXTRIG_MASK);
2122 }
2123 
2132 __STATIC_INLINE void DL_I2C_stopFlushControllerTXFIFO(I2C_Regs *i2c)
2133 {
2134  i2c->MASTER.MFIFOCTL &= ~(I2C_MFIFOCTL_TXFLUSH_MASK);
2135 }
2136 
2142 __STATIC_INLINE void DL_I2C_startFlushControllerTXFIFO(I2C_Regs *i2c)
2143 {
2144  i2c->MASTER.MFIFOCTL |= I2C_MFIFOCTL_TXFLUSH_MASK;
2145 }
2146 
2156 __STATIC_INLINE DL_I2C_RX_FIFO_LEVEL DL_I2C_getControllerRXFIFOThreshold(
2157  const I2C_Regs *i2c)
2158 {
2159  uint32_t level = i2c->MASTER.MFIFOCTL & I2C_MFIFOCTL_RXTRIG_MASK;
2160 
2161  return (DL_I2C_RX_FIFO_LEVEL)(level);
2162 }
2163 
2172 __STATIC_INLINE void DL_I2C_setControllerRXFIFOThreshold(
2173  I2C_Regs *i2c, DL_I2C_RX_FIFO_LEVEL level)
2174 {
2175  DL_Common_updateReg(
2176  &i2c->MASTER.MFIFOCTL, (uint32_t) level, I2C_MFIFOCTL_RXTRIG_MASK);
2177 }
2178 
2187 __STATIC_INLINE void DL_I2C_stopFlushControllerRXFIFO(I2C_Regs *i2c)
2188 {
2189  i2c->MASTER.MFIFOCTL &= ~(I2C_MFIFOCTL_RXFLUSH_MASK);
2190 }
2191 
2197 __STATIC_INLINE void DL_I2C_startFlushControllerRXFIFO(I2C_Regs *i2c)
2198 {
2199  i2c->MASTER.MFIFOCTL |= I2C_MFIFOCTL_RXFLUSH_MASK;
2200 }
2201 
2211 __STATIC_INLINE uint32_t DL_I2C_getControllerRXFIFOCounter(const I2C_Regs *i2c)
2212 {
2213  return (i2c->MASTER.MFIFOSR & I2C_MFIFOSR_RXFIFOCNT_MASK);
2214 }
2215 
2225 __STATIC_INLINE uint32_t DL_I2C_getControllerTXFIFOCounter(const I2C_Regs *i2c)
2226 {
2227  return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFIFOCNT_MASK) >>
2228  I2C_MFIFOSR_TXFIFOCNT_OFS);
2229 }
2230 
2241 __STATIC_INLINE bool DL_I2C_isControllerRXFIFOFlushActive(const I2C_Regs *i2c)
2242 {
2243  return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_RXFLUSH_MASK) ==
2244  I2C_MFIFOSR_RXFLUSH_ACTIVE);
2245 }
2246 
2257 __STATIC_INLINE bool DL_I2C_isControllerTXFIFOFlushActive(const I2C_Regs *i2c)
2258 {
2259  return ((i2c->MASTER.MFIFOSR & I2C_MFIFOSR_TXFLUSH_MASK) ==
2260  I2C_MFIFOSR_TXFLUSH_ACTIVE);
2261 }
2262 
2274 __STATIC_INLINE void DL_I2C_setTargetOwnAddress(I2C_Regs *i2c, uint32_t addr)
2275 {
2276  DL_Common_updateReg(&i2c->SLAVE.SOAR, addr, I2C_SOAR_OAR_MASK);
2277 }
2278 
2292 __STATIC_INLINE uint32_t DL_I2C_getTargetOwnAddress(const I2C_Regs *i2c)
2293 {
2294  return (i2c->SLAVE.SOAR & I2C_SOAR_OAR_MASK);
2295 }
2296 
2304 __STATIC_INLINE void DL_I2C_enableTargetOwnAddress(I2C_Regs *i2c)
2305 {
2306  i2c->SLAVE.SOAR |= I2C_SOAR_OAREN_ENABLE;
2307 }
2308 
2314 __STATIC_INLINE void DL_I2C_disableTargetOwnAddress(I2C_Regs *i2c)
2315 {
2316  i2c->SLAVE.SOAR &= ~(I2C_SOAR_OAREN_MASK);
2317 }
2318 
2329 __STATIC_INLINE bool DL_I2C_isTargetOwnAddressEnabled(const I2C_Regs *i2c)
2330 {
2331  return ((i2c->SLAVE.SOAR & I2C_SOAR_OAREN_MASK) == I2C_SOAR_OAREN_ENABLE);
2332 }
2333 
2344 __STATIC_INLINE void DL_I2C_setTargetAddressingMode(
2345  I2C_Regs *i2c, DL_I2C_TARGET_ADDRESSING_MODE mode)
2346 {
2347  DL_Common_updateReg(
2348  &i2c->SLAVE.SOAR, (uint32_t) mode, I2C_SOAR_SMODE_MASK);
2349 }
2350 
2360 __STATIC_INLINE DL_I2C_TARGET_ADDRESSING_MODE DL_I2C_getTargetAddressingMode(
2361  const I2C_Regs *i2c)
2362 {
2363  uint32_t mode = i2c->SLAVE.SOAR & I2C_SOAR_SMODE_MASK;
2364 
2365  return (DL_I2C_TARGET_ADDRESSING_MODE)(mode);
2366 }
2367 
2376 __STATIC_INLINE uint32_t I2C_getTargetOwnAddressAlternate(const I2C_Regs *i2c)
2377 {
2378  return (i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2_MASK);
2379 }
2380 
2387 __STATIC_INLINE void DL_I2C_setTargetOwnAddressAlternate(
2388  I2C_Regs *i2c, uint32_t addr)
2389 {
2390  DL_Common_updateReg(&i2c->SLAVE.SOAR2, addr, I2C_SOAR2_OAR2_MASK);
2391 }
2392 
2403 __STATIC_INLINE uint32_t DL_I2C_getTargetOwnAddressAlternateMask(
2404  const I2C_Regs *i2c)
2405 {
2406  return ((i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2_MASK_MASK) >>
2407  I2C_SOAR2_OAR2_MASK_OFS);
2408 }
2409 
2422 __STATIC_INLINE void DL_I2C_setTargetOwnAddressAlternateMask(
2423  I2C_Regs *i2c, uint32_t addressMask)
2424 {
2425  DL_Common_updateReg(&i2c->SLAVE.SOAR2,
2426  addressMask << I2C_SOAR2_OAR2_MASK_OFS, I2C_SOAR2_OAR2_MASK_MASK);
2427 }
2428 
2434 __STATIC_INLINE void DL_I2C_disableTargetOwnAddressAlternate(I2C_Regs *i2c)
2435 {
2436  i2c->SLAVE.SOAR2 &= ~(I2C_SOAR2_OAR2EN_MASK);
2437 }
2438 
2449 __STATIC_INLINE bool DL_I2C_isTargetOwnAddressAlternateEnabled(
2450  const I2C_Regs *i2c)
2451 {
2452  return (
2453  (i2c->SLAVE.SOAR2 & I2C_SOAR2_OAR2EN_MASK) == I2C_SOAR2_OAR2EN_ENABLE);
2454 }
2455 
2461 __STATIC_INLINE void DL_I2C_enableTargetOwnAddressAlternate(I2C_Regs *i2c)
2462 {
2463  i2c->SLAVE.SOAR2 |= I2C_SOAR2_OAR2EN_ENABLE;
2464 }
2465 
2476 __STATIC_INLINE uint32_t DL_I2C_getTargetAddressMatch(const I2C_Regs *i2c)
2477 {
2478  return (
2479  (i2c->SLAVE.SSR & I2C_SSR_ADDRMATCH_MASK) >> I2C_SSR_ADDRMATCH_OFS);
2480 }
2481 
2493 __STATIC_INLINE void DL_I2C_disableTargetClockStretching(I2C_Regs *i2c)
2494 {
2495  i2c->SLAVE.SCTR &= ~(I2C_SCTR_SCLKSTRETCH_MASK);
2496 }
2497 
2508 __STATIC_INLINE bool DL_I2C_isTargetClockStretchingEnabled(const I2C_Regs *i2c)
2509 {
2510  return ((i2c->SLAVE.SCTR & I2C_SCTR_SCLKSTRETCH_MASK) ==
2511  I2C_SCTR_SCLKSTRETCH_ENABLE);
2512 }
2513 
2525 __STATIC_INLINE void DL_I2C_enableTargetClockStretching(I2C_Regs *i2c)
2526 {
2527  i2c->SLAVE.SCTR |= I2C_SCTR_SCLKSTRETCH_ENABLE;
2528 }
2529 
2541 __STATIC_INLINE void DL_I2C_disableTargetTXEmptyOnTXRequest(I2C_Regs *i2c)
2542 {
2543  i2c->SLAVE.SCTR &= ~(I2C_SCTR_TXEMPTY_ON_TREQ_MASK);
2544 }
2545 
2557 __STATIC_INLINE bool DL_I2C_isTargetTXEmptyOnTXRequestEnabled(
2558  const I2C_Regs *i2c)
2559 {
2560  return ((i2c->SLAVE.SCTR & I2C_SCTR_TXEMPTY_ON_TREQ_MASK) ==
2561  I2C_SCTR_TXEMPTY_ON_TREQ_ENABLE);
2562 }
2563 
2573 __STATIC_INLINE void DL_I2C_enableTargetTXEmptyOnTXRequest(I2C_Regs *i2c)
2574 {
2575  i2c->SLAVE.SCTR |= I2C_SCTR_TXEMPTY_ON_TREQ_ENABLE;
2576 }
2577 
2586 __STATIC_INLINE void DL_I2C_disableTargetTXTriggerInTXMode(I2C_Regs *i2c)
2587 {
2588  i2c->SLAVE.SCTR &= ~(I2C_SCTR_TXTRIG_TXMODE_MASK);
2589 }
2590 
2601 __STATIC_INLINE bool DL_I2C_isTargetTXTriggerInTXModeEnabled(
2602  const I2C_Regs *i2c)
2603 {
2604  return ((i2c->SLAVE.SCTR & I2C_SCTR_TXTRIG_TXMODE_MASK) ==
2605  I2C_SCTR_TXTRIG_TXMODE_ENABLE);
2606 }
2607 
2624 __STATIC_INLINE void DL_I2C_enableTargetTXTriggerInTXMode(I2C_Regs *i2c)
2625 {
2626  i2c->SLAVE.SCTR |= I2C_SCTR_TXTRIG_TXMODE_ENABLE;
2627 }
2628 
2637 __STATIC_INLINE void DL_I2C_disableTargetTXWaitWhenTXFIFOStale(I2C_Regs *i2c)
2638 {
2639  i2c->SLAVE.SCTR &= ~(I2C_SCTR_TXWAIT_STALE_TXFIFO_MASK);
2640 }
2641 
2656 __STATIC_INLINE bool DL_I2C_isTargetTXWaitWhenTXFIFOStaleEnabled(
2657  const I2C_Regs *i2c)
2658 {
2659  return ((i2c->SLAVE.SCTR & I2C_SCTR_TXWAIT_STALE_TXFIFO_MASK) ==
2660  I2C_SCTR_TXWAIT_STALE_TXFIFO_ENABLE);
2661 }
2662 
2675 __STATIC_INLINE void DL_I2C_enableTargetTXWaitWhenTXFIFOStale(I2C_Regs *i2c)
2676 {
2677  i2c->SLAVE.SCTR |= I2C_SCTR_TXWAIT_STALE_TXFIFO_ENABLE;
2678 }
2679 
2692 __STATIC_INLINE void DL_I2C_disableTargetRXFullOnRXRequest(I2C_Regs *i2c)
2693 {
2694  i2c->SLAVE.SCTR &= ~(I2C_SCTR_RXFULL_ON_RREQ_MASK);
2695 }
2696 
2707 __STATIC_INLINE bool DL_I2C_isTargetRXFullOnRXRequestEnabled(
2708  const I2C_Regs *i2c)
2709 {
2710  return ((i2c->SLAVE.SCTR & I2C_SCTR_RXFULL_ON_RREQ_MASK) ==
2711  I2C_SCTR_RXFULL_ON_RREQ_ENABLE);
2712 }
2713 
2725 __STATIC_INLINE void DL_I2C_enableTargetRXFullOnRXRequest(I2C_Regs *i2c)
2726 {
2727  i2c->SLAVE.SCTR |= I2C_SCTR_RXFULL_ON_RREQ_ENABLE;
2728 }
2729 
2740 __STATIC_INLINE void DL_I2C_disableDefaultHostAddress(I2C_Regs *i2c)
2741 {
2742  i2c->SLAVE.SCTR &= ~(I2C_SCTR_EN_DEFHOSTADR_MASK);
2743 }
2744 
2756 __STATIC_INLINE bool DL_I2C_isDefaultHostAddressEnabled(const I2C_Regs *i2c)
2757 {
2758  return ((i2c->SLAVE.SCTR & I2C_SCTR_EN_DEFHOSTADR_MASK) ==
2759  I2C_SCTR_EN_DEFHOSTADR_ENABLE);
2760 }
2761 
2770 __STATIC_INLINE void DL_I2C_enableDefaultHostAddress(I2C_Regs *i2c)
2771 {
2772  i2c->SLAVE.SCTR |= I2C_SCTR_EN_DEFHOSTADR_ENABLE;
2773 }
2774 
2786 __STATIC_INLINE void DL_I2C_disableAlertResponseAddress(I2C_Regs *i2c)
2787 {
2788  i2c->SLAVE.SCTR &= ~(I2C_SCTR_EN_ALRESPADR_MASK);
2789 }
2790 
2802 __STATIC_INLINE bool DL_I2C_isAlertResponseAddressEnabled(const I2C_Regs *i2c)
2803 {
2804  return ((i2c->SLAVE.SCTR & I2C_SCTR_EN_ALRESPADR_MASK) ==
2805  I2C_SCTR_EN_ALRESPADR_ENABLE);
2806 }
2807 
2816 __STATIC_INLINE void DL_I2C_enableAlertResponseAddress(I2C_Regs *i2c)
2817 {
2818  i2c->SLAVE.SCTR |= I2C_SCTR_EN_ALRESPADR_ENABLE;
2819 }
2820 
2832 __STATIC_INLINE void DL_I2C_disableDefaultDeviceAddress(I2C_Regs *i2c)
2833 {
2834  i2c->SLAVE.SCTR &= ~(I2C_SCTR_EN_DEFDEVADR_MASK);
2835 }
2836 
2848 __STATIC_INLINE bool DL_I2C_isDefaultDeviceAddressEnabled(const I2C_Regs *i2c)
2849 {
2850  return ((i2c->SLAVE.SCTR & I2C_SCTR_EN_DEFDEVADR_MASK) ==
2851  I2C_SCTR_EN_DEFDEVADR_ENABLE);
2852 }
2853 
2862 __STATIC_INLINE void DL_I2C_enableDefaultDeviceAddress(I2C_Regs *i2c)
2863 {
2864  i2c->SLAVE.SCTR |= I2C_SCTR_EN_DEFDEVADR_ENABLE;
2865 }
2866 
2875 __STATIC_INLINE void DL_I2C_disableTargetWakeup(I2C_Regs *i2c)
2876 {
2877  i2c->SLAVE.SCTR &= ~(I2C_SCTR_SWUEN_MASK);
2878 }
2879 
2890 __STATIC_INLINE bool DL_I2C_isTargetWakeupEnabled(const I2C_Regs *i2c)
2891 {
2892  return ((i2c->SLAVE.SCTR & I2C_SCTR_SWUEN_MASK) == I2C_SCTR_SWUEN_ENABLE);
2893 }
2894 
2905 __STATIC_INLINE void DL_I2C_enableTargetWakeup(I2C_Regs *i2c)
2906 {
2907  i2c->SLAVE.SCTR |= I2C_SCTR_SWUEN_ENABLE;
2908 }
2909 
2915 __STATIC_INLINE void DL_I2C_disableTarget(I2C_Regs *i2c)
2916 {
2917  i2c->SLAVE.SCTR &= ~(I2C_SCTR_ACTIVE_MASK);
2918 }
2919 
2930 __STATIC_INLINE bool DL_I2C_isTargetEnabled(const I2C_Regs *i2c)
2931 {
2932  return (
2933  (i2c->SLAVE.SCTR & I2C_SCTR_ACTIVE_MASK) == I2C_SCTR_ACTIVE_ENABLE);
2934 }
2935 
2941 __STATIC_INLINE void DL_I2C_enableTarget(I2C_Regs *i2c)
2942 {
2943  i2c->SLAVE.SCTR |= I2C_SCTR_ACTIVE_ENABLE;
2944 }
2945 
2951 __STATIC_INLINE void DL_I2C_disableGeneralCall(I2C_Regs *i2c)
2952 {
2953  i2c->SLAVE.SCTR &= ~(I2C_SCTR_GENCALL_MASK);
2954 }
2955 
2966 __STATIC_INLINE bool DL_I2C_isGeneralCallEnabled(const I2C_Regs *i2c)
2967 {
2968  return (
2969  (i2c->SLAVE.SCTR & I2C_SCTR_GENCALL_MASK) == I2C_SCTR_GENCALL_ENABLE);
2970 }
2971 
2977 __STATIC_INLINE void DL_I2C_enableGeneralCall(I2C_Regs *i2c)
2978 {
2979  i2c->SLAVE.SCTR |= I2C_SCTR_GENCALL_ENABLE;
2980 }
2981 
2991 __STATIC_INLINE uint32_t DL_I2C_getTargetStatus(const I2C_Regs *i2c)
2992 {
2993  return (i2c->SLAVE.SSR);
2994 }
2995 
3007 __STATIC_INLINE uint8_t DL_I2C_receiveTargetData(const I2C_Regs *i2c)
3008 {
3009  return (uint8_t)(i2c->SLAVE.SRXDATA & I2C_SRXDATA_VALUE_MASK);
3010 }
3011 
3019 __STATIC_INLINE void DL_I2C_transmitTargetData(I2C_Regs *i2c, uint8_t data)
3020 {
3021  i2c->SLAVE.STXDATA = data;
3022 }
3023 
3032 __STATIC_INLINE void DL_I2C_disableTargetACKOverride(I2C_Regs *i2c)
3033 {
3034  i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_MASK);
3035 }
3036 
3047 __STATIC_INLINE bool DL_I2C_isTargetACKOverrideEnabled(const I2C_Regs *i2c)
3048 {
3049  return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_MASK) ==
3050  I2C_SACKCTL_ACKOEN_ENABLE);
3051 }
3052 
3064 __STATIC_INLINE void DL_I2C_enableTargetACKOverride(I2C_Regs *i2c)
3065 {
3066  i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ENABLE;
3067 }
3068 
3081 __STATIC_INLINE DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE
3082 DL_I2C_getTargetACKOverrideValue(const I2C_Regs *i2c)
3083 {
3084  uint32_t value = i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOVAL_MASK;
3085 
3086  return (DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE)(value);
3087 }
3088 
3101 __STATIC_INLINE void DL_I2C_setTargetACKOverrideValue(
3102  I2C_Regs *i2c, DL_I2C_TARGET_RESPONSE_OVERRIDE_VALUE value)
3103 {
3104  DL_Common_updateReg(
3105  &i2c->SLAVE.SACKCTL, (uint32_t) value, I2C_SACKCTL_ACKOVAL_MASK);
3106 }
3107 
3113 __STATIC_INLINE void DL_I2C_disableACKOverrideOnStart(I2C_Regs *i2c)
3114 {
3115  i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_ON_START_MASK);
3116 }
3117 
3128 __STATIC_INLINE bool DL_I2C_isACKOverrideOnStartEnabled(const I2C_Regs *i2c)
3129 {
3130  return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_ON_START_MASK) ==
3131  I2C_SACKCTL_ACKOEN_ON_START_ENABLE);
3132 }
3133 
3144 __STATIC_INLINE void DL_I2C_enableACKOverrideOnStart(I2C_Regs *i2c)
3145 {
3146  i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ON_START_ENABLE;
3147 }
3148 
3154 __STATIC_INLINE void DL_I2C_disableACKOverrideOnPECNext(I2C_Regs *i2c)
3155 {
3156  i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_ON_PECNEXT_MASK);
3157 }
3158 
3170 __STATIC_INLINE bool DL_I2C_isACKOverrideOnPECNextEnabled(const I2C_Regs *i2c)
3171 {
3172  return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_ON_PECNEXT_MASK) ==
3173  I2C_SACKCTL_ACKOEN_ON_PECNEXT_ENABLE);
3174 }
3175 
3189 __STATIC_INLINE void DL_I2C_enableACKOverrideOnPECNext(I2C_Regs *i2c)
3190 {
3191  i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ON_PECNEXT_ENABLE;
3192 }
3193 
3199 __STATIC_INLINE void DL_I2C_disableACKOverrideOnPECDone(I2C_Regs *i2c)
3200 {
3201  i2c->SLAVE.SACKCTL &= ~(I2C_SACKCTL_ACKOEN_ON_PECDONE_MASK);
3202 }
3203 
3215 __STATIC_INLINE bool DL_I2C_isACKOverrideOnPECDoneEnabled(const I2C_Regs *i2c)
3216 {
3217  return ((i2c->SLAVE.SACKCTL & I2C_SACKCTL_ACKOEN_ON_PECDONE_MASK) ==
3218  I2C_SACKCTL_ACKOEN_ON_PECDONE_ENABLE);
3219 }
3220 
3231 __STATIC_INLINE void DL_I2C_enableACKOverrideOnPECDone(I2C_Regs *i2c)
3232 {
3233  i2c->SLAVE.SACKCTL |= I2C_SACKCTL_ACKOEN_ON_PECDONE_ENABLE;
3234 }
3235 
3246 __STATIC_INLINE uint32_t DL_I2C_getTargetPECCountValue(const I2C_Regs *i2c)
3247 {
3248  return (i2c->SLAVE.TARGET_PECCTL & I2C_TARGET_PECCTL_PECCNT_MASK);
3249 }
3250 
3262 __STATIC_INLINE void DL_I2C_setTargetPECCountValue(
3263  I2C_Regs *i2c, uint32_t count)
3264 {
3265  DL_Common_updateReg(
3266  &i2c->SLAVE.TARGET_PECCTL, count, I2C_TARGET_PECCTL_PECCNT_MASK);
3267 }
3268 
3274 __STATIC_INLINE void DL_I2C_disableTargetPEC(I2C_Regs *i2c)
3275 {
3276  i2c->SLAVE.TARGET_PECCTL &= ~(I2C_TARGET_PECCTL_PECEN_MASK);
3277 }
3278 
3290 __STATIC_INLINE bool DL_I2C_isTargetPECEnabled(const I2C_Regs *i2c)
3291 {
3292  return ((i2c->SLAVE.TARGET_PECCTL & I2C_TARGET_PECCTL_PECEN_MASK) ==
3293  I2C_TARGET_PECCTL_PECEN_ENABLE);
3294 }
3295 
3310 __STATIC_INLINE void DL_I2C_enableTargetPEC(I2C_Regs *i2c)
3311 {
3312  i2c->SLAVE.TARGET_PECCTL |= I2C_TARGET_PECCTL_PECEN_ENABLE;
3313 }
3314 
3325 __STATIC_INLINE uint32_t DL_I2C_getTargetCurrentPECCount(const I2C_Regs *i2c)
3326 {
3327  return (i2c->SLAVE.TARGET_PECSR & I2C_TARGET_PECSR_PECBYTECNT_MASK);
3328 }
3329 
3343 __STATIC_INLINE DL_I2C_TARGET_PEC_STATUS DL_I2C_getTargetPECCheckedStatus(
3344  const I2C_Regs *i2c)
3345 {
3346  uint32_t status =
3347  i2c->SLAVE.TARGET_PECSR & I2C_TARGET_PECSR_PECSTS_CHECK_MASK;
3348 
3349  return (DL_I2C_TARGET_PEC_STATUS)(status);
3350 }
3351 
3364 __STATIC_INLINE DL_I2C_TARGET_PEC_CHECK_ERROR DL_I2C_getTargetPECCheckError(
3365  const I2C_Regs *i2c)
3366 {
3367  uint32_t status =
3368  i2c->SLAVE.TARGET_PECSR & I2C_TARGET_PECSR_PECSTS_ERROR_MASK;
3369 
3370  return (DL_I2C_TARGET_PEC_CHECK_ERROR)(status);
3371 }
3372 
3382 __STATIC_INLINE DL_I2C_TX_FIFO_LEVEL DL_I2C_getTargetTXFIFOThreshold(
3383  const I2C_Regs *i2c)
3384 {
3385  uint32_t level = i2c->SLAVE.SFIFOCTL & I2C_SFIFOCTL_TXTRIG_MASK;
3386 
3387  return (DL_I2C_TX_FIFO_LEVEL)(level);
3388 }
3389 
3398 __STATIC_INLINE void DL_I2C_setTargetTXFIFOThreshold(
3399  I2C_Regs *i2c, DL_I2C_TX_FIFO_LEVEL level)
3400 {
3401  DL_Common_updateReg(&i2c->SLAVE.SFIFOCTL, (uint32_t) level,
3402  (uint32_t) I2C_SFIFOCTL_TXTRIG_MASK);
3403 }
3404 
3413 __STATIC_INLINE void DL_I2C_stopFlushTargetTXFIFO(I2C_Regs *i2c)
3414 {
3415  i2c->SLAVE.SFIFOCTL &= ~(I2C_SFIFOCTL_TXFLUSH_MASK);
3416 }
3417 
3423 __STATIC_INLINE void DL_I2C_startFlushTargetTXFIFO(I2C_Regs *i2c)
3424 {
3425  i2c->SLAVE.SFIFOCTL |= I2C_SFIFOCTL_TXFLUSH_MASK;
3426 }
3427 
3436 __STATIC_INLINE void DL_I2C_stopFlushTargetRXFIFO(I2C_Regs *i2c)
3437 {
3438  i2c->SLAVE.SFIFOCTL &= ~(I2C_SFIFOCTL_RXFLUSH_MASK);
3439 }
3440 
3446 __STATIC_INLINE void DL_I2C_startFlushTargetRXFIFO(I2C_Regs *i2c)
3447 {
3448  i2c->SLAVE.SFIFOCTL |= I2C_SFIFOCTL_RXFLUSH_MASK;
3449 }
3450 
3460 __STATIC_INLINE DL_I2C_RX_FIFO_LEVEL DL_I2C_getTargetRXFIFOThreshold(
3461  const I2C_Regs *i2c)
3462 {
3463  uint32_t level = i2c->SLAVE.SFIFOCTL & I2C_SFIFOCTL_RXTRIG_MASK;
3464 
3465  return (DL_I2C_RX_FIFO_LEVEL)(level);
3466 }
3467 
3476 __STATIC_INLINE void DL_I2C_setTargetRXFIFOThreshold(
3477  I2C_Regs *i2c, DL_I2C_RX_FIFO_LEVEL level)
3478 {
3479  DL_Common_updateReg(
3480  &i2c->SLAVE.SFIFOCTL, (uint32_t) level, I2C_SFIFOCTL_RXTRIG_MASK);
3481 }
3482 
3492 __STATIC_INLINE uint32_t DL_I2C_getTargetRXFIFOCounter(const I2C_Regs *i2c)
3493 {
3494  return (i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_RXFIFOCNT_MASK);
3495 }
3496 
3506 __STATIC_INLINE uint32_t DL_I2C_getTargetTXFIFOCounter(const I2C_Regs *i2c)
3507 {
3508  return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFIFOCNT_MASK) >>
3509  I2C_SFIFOSR_TXFIFOCNT_OFS);
3510 }
3511 
3522 __STATIC_INLINE bool DL_I2C_isTargetRXFIFOFlushActive(const I2C_Regs *i2c)
3523 {
3524  return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_RXFLUSH_MASK) ==
3525  I2C_SFIFOSR_RXFLUSH_ACTIVE);
3526 }
3527 
3538 __STATIC_INLINE bool DL_I2C_isTargetTXFIFOFlushActive(const I2C_Regs *i2c)
3539 {
3540  return ((i2c->SLAVE.SFIFOSR & I2C_SFIFOSR_TXFLUSH_MASK) ==
3541  I2C_SFIFOSR_TXFLUSH_ACTIVE);
3542 }
3543 
3552 __STATIC_INLINE void DL_I2C_enableInterrupt(
3553  I2C_Regs *i2c, uint32_t interruptMask)
3554 {
3555  i2c->CPU_INT.IMASK |= interruptMask;
3556 }
3557 
3566 __STATIC_INLINE void DL_I2C_disableInterrupt(
3567  I2C_Regs *i2c, uint32_t interruptMask)
3568 {
3569  i2c->CPU_INT.IMASK &= ~(interruptMask);
3570 }
3571 
3584 __STATIC_INLINE uint32_t DL_I2C_getEnabledInterrupts(
3585  const I2C_Regs *i2c, uint32_t interruptMask)
3586 {
3587  return (i2c->CPU_INT.IMASK & interruptMask);
3588 }
3589 
3607 __STATIC_INLINE uint32_t DL_I2C_getEnabledInterruptStatus(
3608  const I2C_Regs *i2c, uint32_t interruptMask)
3609 {
3610  return (i2c->CPU_INT.MIS & interruptMask);
3611 }
3612 
3628 __STATIC_INLINE uint32_t DL_I2C_getRawInterruptStatus(
3629  const I2C_Regs *i2c, uint32_t interruptMask)
3630 {
3631  return (i2c->CPU_INT.RIS & interruptMask);
3632 }
3633 
3646 __STATIC_INLINE DL_I2C_IIDX DL_I2C_getPendingInterrupt(const I2C_Regs *i2c)
3647 {
3648  return ((DL_I2C_IIDX) i2c->CPU_INT.IIDX);
3649 }
3650 
3659 __STATIC_INLINE void DL_I2C_clearInterruptStatus(
3660  I2C_Regs *i2c, uint32_t interruptMask)
3661 {
3662  i2c->CPU_INT.ICLR = interruptMask;
3663 }
3664 
3681 __STATIC_INLINE void DL_I2C_enableDMAEvent(
3682  I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interrupt)
3683 {
3684  switch (index) {
3685  case DL_I2C_EVENT_ROUTE_1:
3686  i2c->DMA_TRIG1.IMASK = interrupt;
3687  break;
3688  case DL_I2C_EVENT_ROUTE_2:
3689  i2c->DMA_TRIG0.IMASK = interrupt;
3690  break;
3691  default:
3692  break;
3693  }
3694 }
3695 
3710 __STATIC_INLINE void DL_I2C_disableDMAEvent(
3711  I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interrupt)
3712 {
3713  switch (index) {
3714  case DL_I2C_EVENT_ROUTE_1:
3715  i2c->DMA_TRIG1.IMASK &= ~(interrupt);
3716  break;
3717  case DL_I2C_EVENT_ROUTE_2:
3718  i2c->DMA_TRIG0.IMASK &= ~(interrupt);
3719  break;
3720  default:
3721  break;
3722  }
3723 }
3724 
3743 __STATIC_INLINE uint32_t DL_I2C_getEnabledDMAEvents(
3744  I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interruptMask)
3745 {
3746  volatile uint32_t *pReg = &i2c->DMA_TRIG1.IMASK;
3747 
3748  return ((*(pReg + (uint32_t) index) & interruptMask));
3749 }
3750 
3773 __STATIC_INLINE uint32_t DL_I2C_getEnabledDMAEventStatus(
3774  const I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interruptMask)
3775 {
3776  const volatile uint32_t *pReg = &i2c->DMA_TRIG1.MIS;
3777 
3778  return ((*(pReg + (uint32_t) index) & interruptMask));
3779 }
3780 
3799 __STATIC_INLINE uint32_t DL_I2C_getRawDMAEventStatus(
3800  const I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interruptMask)
3801 {
3802  const volatile uint32_t *pReg = &i2c->DMA_TRIG1.RIS;
3803 
3804  return ((*(pReg + (uint32_t) index) & interruptMask));
3805 }
3806 
3823 __STATIC_INLINE DL_I2C_DMA_IIDX DL_I2C_getPendingDMAEvent(
3824  const I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index)
3825 {
3826  const volatile uint32_t *pReg = &i2c->DMA_TRIG1.IIDX;
3827 
3828  return (DL_I2C_DMA_IIDX)((*(pReg + (uint32_t) index)));
3829 }
3830 
3842 __STATIC_INLINE void DL_I2C_clearDMAEvent(
3843  I2C_Regs *i2c, DL_I2C_EVENT_ROUTE index, uint32_t interrupt)
3844 {
3845  switch (index) {
3846  case DL_I2C_EVENT_ROUTE_1:
3847  i2c->DMA_TRIG1.ICLR |= interrupt;
3848  break;
3849  case DL_I2C_EVENT_ROUTE_2:
3850  i2c->DMA_TRIG0.ICLR |= interrupt;
3851  break;
3852  default:
3853  break;
3854  }
3855 }
3856 
3865 __STATIC_INLINE void DL_I2C_disableGlitchFilterChaining(I2C_Regs *i2c)
3866 {
3867  i2c->GFCTL &= ~(I2C_GFCTL_CHAIN_MASK);
3868 }
3869 
3880 __STATIC_INLINE bool DL_I2C_isGlitchFilterChainingEnabled(const I2C_Regs *i2c)
3881 {
3882  return ((i2c->GFCTL & I2C_GFCTL_CHAIN_MASK) == I2C_GFCTL_CHAIN_ENABLE);
3883 }
3884 
3893 __STATIC_INLINE void DL_I2C_enableGlitchFilterChaining(I2C_Regs *i2c)
3894 {
3895  i2c->GFCTL |= I2C_GFCTL_CHAIN_ENABLE;
3896 }
3897 
3907 __STATIC_INLINE uint32_t DL_I2C_getTimeoutACount(const I2C_Regs *i2c)
3908 {
3909  return (i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTLA_MASK);
3910 }
3911 
3928 __STATIC_INLINE void DL_I2C_setTimeoutACount(I2C_Regs *i2c, uint32_t count)
3929 {
3930  DL_Common_updateReg(&i2c->TIMEOUT_CTL, count, I2C_TIMEOUT_CTL_TCNTLA_MASK);
3931 }
3932 
3938 __STATIC_INLINE void DL_I2C_disableTimeoutA(I2C_Regs *i2c)
3939 {
3940  i2c->TIMEOUT_CTL &= ~(I2C_TIMEOUT_CTL_TCNTAEN_MASK);
3941 }
3942 
3953 __STATIC_INLINE bool DL_I2C_isTimeoutAEnabled(const I2C_Regs *i2c)
3954 {
3955  return ((i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTAEN_MASK) ==
3956  I2C_TIMEOUT_CTL_TCNTAEN_ENABLE);
3957 }
3958 
3964 __STATIC_INLINE void DL_I2C_enableTimeoutA(I2C_Regs *i2c)
3965 {
3966  i2c->TIMEOUT_CTL |= I2C_TIMEOUT_CTL_TCNTAEN_ENABLE;
3967 }
3968 
3981 __STATIC_INLINE uint32_t DL_I2C_getCurrentTimeoutACounter(const I2C_Regs *i2c)
3982 {
3983  return (i2c->TIMEOUT_CNT & I2C_TIMEOUT_CNT_TCNTA_MASK);
3984 }
3985 
3995 __STATIC_INLINE uint32_t DL_I2C_getTimeoutBCount(const I2C_Regs *i2c)
3996 {
3997  return ((i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTLB_MASK) >>
3998  I2C_TIMEOUT_CTL_TCNTLB_OFS);
3999 }
4000 
4015 __STATIC_INLINE void DL_I2C_setTimeoutBCount(I2C_Regs *i2c, uint32_t count)
4016 {
4017  DL_Common_updateReg(&i2c->TIMEOUT_CTL,
4018  (count << I2C_TIMEOUT_CTL_TCNTLB_OFS), I2C_TIMEOUT_CTL_TCNTLB_MASK);
4019 }
4020 
4026 __STATIC_INLINE void DL_I2C_disableTimeoutB(I2C_Regs *i2c)
4027 {
4028  i2c->TIMEOUT_CTL &= ~(I2C_TIMEOUT_CTL_TCNTBEN_MASK);
4029 }
4030 
4041 __STATIC_INLINE bool DL_I2C_isTimeoutBEnabled(const I2C_Regs *i2c)
4042 {
4043  return ((i2c->TIMEOUT_CTL & I2C_TIMEOUT_CTL_TCNTBEN_MASK) ==
4044  I2C_TIMEOUT_CTL_TCNTBEN_ENABLE);
4045 }
4046 
4052 __STATIC_INLINE void DL_I2C_enableTimeoutB(I2C_Regs *i2c)
4053 {
4054  i2c->TIMEOUT_CTL |= I2C_TIMEOUT_CTL_TCNTBEN_ENABLE;
4055 }
4056 
4069 __STATIC_INLINE uint32_t DL_I2C_getCurrentTimeoutBCounter(const I2C_Regs *i2c)
4070 {
4071  return (i2c->TIMEOUT_CNT & I2C_TIMEOUT_CNT_TCNTB_MASK);
4072 }
4073 
4074 #ifdef __cplusplus
4075 }
4076 #endif
4077 
4078 #endif /* __MSPM0_HAS_I2C__ */
4079 
4080 #endif /* ti_dl_dl_i2c__include */
4081 
DL_Common_updateReg
__STATIC_INLINE void DL_Common_updateReg(volatile uint32_t *reg, uint32_t val, uint32_t mask)
Writes value to specified register - retaining bits unaffected by mask.
Definition: dl_common.h:63
dl_common.h
DriverLib Common APIs.
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