Configuration struct for DL_SYSCTL_configSYSPLL. More...

#include <dl_sysctl_mspm0gx51x.h>

Data Fields
uint32_t	rDivClk2x

uint32_t	rDivClk1

uint32_t	rDivClk0

uint32_t	enableCLK2x

uint32_t	enableCLK1

uint32_t	enableCLK0

DL_SYSCTL_SYSPLL_MCLK	sysPLLMCLK

DL_SYSCTL_SYSPLL_REF	sysPLLRef

uint32_t	qDiv

DL_SYSCTL_SYSPLL_PDIV	pDiv

DL_SYSCTL_SYSPLL_INPUT_FREQ	inputFreq

Detailed Description

Configuration struct for DL_SYSCTL_configSYSPLL.

Field Documentation

§ rDivClk2x

uint32_t DL_SYSCTL_SYSPLLConfig::rDivClk2x

Output divider for CLK2x. [0x0,0xF,0x1] => [/1,/16,1]

§ rDivClk1

uint32_t DL_SYSCTL_SYSPLLConfig::rDivClk1

Output divider for CLK1. [0x0,0xF,0x1] => [/2,/32,2]

§ rDivClk0

uint32_t DL_SYSCTL_SYSPLLConfig::rDivClk0

Output divider for CLK0. [0x0,0xF,0x1] => [/2,/32,2]

§ enableCLK2x

uint32_t DL_SYSCTL_SYSPLLConfig::enableCLK2x

PLL CLK2x output enabled or not. DL_SYSCTL_SYSPLL_CLK2X

§ enableCLK1

uint32_t DL_SYSCTL_SYSPLLConfig::enableCLK1

PLL CLK2x output enabled or not. DL_SYSCTL_SYSPLL_CLK1

§ enableCLK0

uint32_t DL_SYSCTL_SYSPLLConfig::enableCLK0

PLL CLK2x output enabled or not. DL_SYSCTL_SYSPLL_CLK0

§ sysPLLMCLK

DL_SYSCTL_SYSPLL_MCLK DL_SYSCTL_SYSPLLConfig::sysPLLMCLK

Select which PLL output to use as source for MCLK. DL_SYSCTL_SYSPLL_MCLK

§ sysPLLRef

DL_SYSCTL_SYSPLL_REF DL_SYSCTL_SYSPLLConfig::sysPLLRef

SYSPLL reference clock source. DL_SYSCTL_SYSPLL_REF

§ qDiv

uint32_t DL_SYSCTL_SYSPLLConfig::qDiv

PLL feedback clock divider. [0x01,0x7E,1] => [/2,/127,1]

§ pDiv

DL_SYSCTL_SYSPLL_PDIV DL_SYSCTL_SYSPLLConfig::pDiv

PLL reference clock divider. DL_SYSCTL_SYSPLL_PDIV

§ inputFreq

DL_SYSCTL_SYSPLL_INPUT_FREQ DL_SYSCTL_SYSPLLConfig::inputFreq

PLL feedback loop input clock frequency. Affects startup time and power consumption. DL_SYSCTL_SYSPLL_INPUT_FREQ

The documentation for this struct was generated from the following file:

dl_sysctl_mspm0gx51x.h

Data Fields