DL_DMA_INTERRUPT

Collaboration diagram for DL_DMA_INTERRUPT:

Macros
#define	DL_DMA_INTERRUPT_CHANNEL0   (DMA_CPU_INT_IMASK_DMACH0_SET)
	DMA channel 0 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL1   (DMA_CPU_INT_IMASK_DMACH1_SET)
	DMA channel 1 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL2   (DMA_CPU_INT_IMASK_DMACH2_SET)
	DMA channel 2 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL3   (DMA_CPU_INT_IMASK_DMACH3_SET)
	DMA channel 3 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL4   (DMA_CPU_INT_IMASK_DMACH4_SET)
	DMA channel 4 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL5   (DMA_CPU_INT_IMASK_DMACH5_SET)
	DMA channel 5 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL6   (DMA_CPU_INT_IMASK_DMACH6_SET)
	DMA channel 6 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL7   (DMA_CPU_INT_IMASK_DMACH7_SET)
	DMA channel 7 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL8   (DMA_CPU_INT_IMASK_DMACH8_SET)
	DMA channel 8 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL9   (DMA_CPU_INT_IMASK_DMACH9_SET)
	DMA channel 9 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL10   (DMA_CPU_INT_IMASK_DMACH10_SET)
	DMA channel 10 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL12   (DMA_CPU_INT_IMASK_DMACH12_SET)
	DMA channel 12 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL13   (DMA_CPU_INT_IMASK_DMACH13_SET)
	DMA channel 13 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL14   (DMA_CPU_INT_IMASK_DMACH14_SET)
	DMA channel 14 interrupt.
#define	DL_DMA_INTERRUPT_CHANNEL15   (DMA_CPU_INT_IMASK_DMACH15_SET)
	DMA channel 15 interrupt.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL0   (DMA_CPU_INT_IMASK_PREIRQCH0_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 0 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL1   (DMA_CPU_INT_IMASK_PREIRQCH1_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 1 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL2   (DMA_CPU_INT_IMASK_PREIRQCH2_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 2 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL3   (DMA_CPU_INT_IMASK_PREIRQCH3_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 3 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL4   (DMA_CPU_INT_IMASK_PREIRQCH4_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 4 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL5   (DMA_CPU_INT_IMASK_PREIRQCH5_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 5 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL6   (DMA_CPU_INT_IMASK_PREIRQCH6_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 6 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_FULL_CH_INTERRUPT_EARLY_CHANNEL7   (DMA_CPU_INT_IMASK_PREIRQCH7_SET)
	Available for FULL-channel configuration only. Early IRQ for DMA channel 7 interrupt. Size counter has reached early IRQ threshold.
#define	DL_DMA_INTERRUPT_ADDR_ERROR   (DMA_CPU_INT_IMASK_ADDRERR_SET)
	DMA address error, source address not reachable.
#define	DL_DMA_INTERRUPT_DATA_ERROR   (DMA_CPU_INT_IMASK_DATAERR_SET)
	DMA data error, source data might be corrupted (PAR or ECC error)

Detailed Description