dl_gpio.h

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/*
 * Copyright (c) 2020, Texas Instruments Incorporated
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * *  Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 * *  Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * *  Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
/*!****************************************************************************
 *  @file       dl_gpio.h
 *  @brief      General Purpose Input/Output Driver Library
 *  @defgroup   GPIO General Purpose Input/Output (GPIO)
 *
 *  @anchor ti_dl_dl_gpio_Overview
 *  # Overview
 *
 *  The GPIO Driver Library allows full configuration of
 *  the MSPM0 GPIO module. The GPIO peripheral provides the user with a means
 *  to write data out and read data in to and from the device pins.
 *  It also provides a way to detect wakeup events while the device is in a
 *  low power state.
 *
 *  <hr>
 ******************************************************************************
 */
#ifndef ti_dl_dl_gpio__include
#define ti_dl_dl_gpio__include

#include <ti/devices/msp/msp.h>
#include <ti/driverlib/dl_common.h>

#ifdef __MSPM0_HAS_GPIO__

#ifdef __cplusplus
extern "C" {
#endif

/* clang-format off */

#define DL_GPIO_PIN_0                                               (0x00000001)

#define DL_GPIO_PIN_1                                               (0x00000002)

#define DL_GPIO_PIN_2                                               (0x00000004)

#define DL_GPIO_PIN_3                                               (0x00000008)

#define DL_GPIO_PIN_4                                               (0x00000010)

#define DL_GPIO_PIN_5                                               (0x00000020)

#define DL_GPIO_PIN_6                                               (0x00000040)

#define DL_GPIO_PIN_7                                               (0x00000080)

#define DL_GPIO_PIN_8                                               (0x00000100)

#define DL_GPIO_PIN_9                                               (0x00000200)

#define DL_GPIO_PIN_10                                              (0x00000400)

#define DL_GPIO_PIN_11                                              (0x00000800)

#define DL_GPIO_PIN_12                                              (0x00001000)

#define DL_GPIO_PIN_13                                              (0x00002000)

#define DL_GPIO_PIN_14                                              (0x00004000)

#define DL_GPIO_PIN_15                                              (0x00008000)

#define DL_GPIO_PIN_16                                              (0x00010000)

#define DL_GPIO_PIN_17                                              (0x00020000)

#define DL_GPIO_PIN_18                                              (0x00040000)

#define DL_GPIO_PIN_19                                              (0x00080000)

#define DL_GPIO_PIN_20                                              (0x00100000)

#define DL_GPIO_PIN_21                                              (0x00200000)

#define DL_GPIO_PIN_22                                              (0x00400000)

#define DL_GPIO_PIN_23                                              (0x00800000)

#define DL_GPIO_PIN_24                                              (0x01000000)

#define DL_GPIO_PIN_25                                              (0x02000000)

#define DL_GPIO_PIN_26                                              (0x04000000)

#define DL_GPIO_PIN_27                                              (0x08000000)

#define DL_GPIO_PIN_28                                              (0x10000000)

#define DL_GPIO_PIN_29                                              (0x20000000)

#define DL_GPIO_PIN_30                                              (0x40000000)

#define DL_GPIO_PIN_31                                              (0x80000000)

#define DL_GPIO_PIN_0_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO0_DISABLE)

#define DL_GPIO_PIN_0_EDGE_RISE                    (GPIO_POLARITY15_0_DIO0_RISE)

#define DL_GPIO_PIN_0_EDGE_FALL                    (GPIO_POLARITY15_0_DIO0_FALL)

#define DL_GPIO_PIN_0_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO0_RISE_FALL)

#define DL_GPIO_PIN_1_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO1_DISABLE)

#define DL_GPIO_PIN_1_EDGE_RISE                    (GPIO_POLARITY15_0_DIO1_RISE)

#define DL_GPIO_PIN_1_EDGE_FALL                    (GPIO_POLARITY15_0_DIO1_FALL)

#define DL_GPIO_PIN_1_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO1_RISE_FALL)

#define DL_GPIO_PIN_2_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO2_DISABLE)

#define DL_GPIO_PIN_2_EDGE_RISE                    (GPIO_POLARITY15_0_DIO2_RISE)

#define DL_GPIO_PIN_2_EDGE_FALL                    (GPIO_POLARITY15_0_DIO2_FALL)

#define DL_GPIO_PIN_2_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO2_RISE_FALL)

#define DL_GPIO_PIN_3_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO3_DISABLE)

#define DL_GPIO_PIN_3_EDGE_RISE                    (GPIO_POLARITY15_0_DIO3_RISE)

#define DL_GPIO_PIN_3_EDGE_FALL                    (GPIO_POLARITY15_0_DIO3_FALL)

#define DL_GPIO_PIN_3_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO3_RISE_FALL)

#define DL_GPIO_PIN_4_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO4_DISABLE)

#define DL_GPIO_PIN_4_EDGE_RISE                    (GPIO_POLARITY15_0_DIO4_RISE)

#define DL_GPIO_PIN_4_EDGE_FALL                    (GPIO_POLARITY15_0_DIO4_FALL)

#define DL_GPIO_PIN_4_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO4_RISE_FALL)

#define DL_GPIO_PIN_5_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO5_DISABLE)

#define DL_GPIO_PIN_5_EDGE_RISE                    (GPIO_POLARITY15_0_DIO5_RISE)

#define DL_GPIO_PIN_5_EDGE_FALL                    (GPIO_POLARITY15_0_DIO5_FALL)

#define DL_GPIO_PIN_5_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO5_RISE_FALL)

#define DL_GPIO_PIN_6_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO6_DISABLE)

#define DL_GPIO_PIN_6_EDGE_RISE                    (GPIO_POLARITY15_0_DIO6_RISE)

#define DL_GPIO_PIN_6_EDGE_FALL                    (GPIO_POLARITY15_0_DIO6_FALL)

#define DL_GPIO_PIN_6_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO6_RISE_FALL)

#define DL_GPIO_PIN_7_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO7_DISABLE)

#define DL_GPIO_PIN_7_EDGE_RISE                    (GPIO_POLARITY15_0_DIO7_RISE)

#define DL_GPIO_PIN_7_EDGE_FALL                    (GPIO_POLARITY15_0_DIO7_FALL)

#define DL_GPIO_PIN_7_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO7_RISE_FALL)

#define DL_GPIO_PIN_8_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO8_DISABLE)

#define DL_GPIO_PIN_8_EDGE_RISE                    (GPIO_POLARITY15_0_DIO8_RISE)

#define DL_GPIO_PIN_8_EDGE_FALL                    (GPIO_POLARITY15_0_DIO8_FALL)

#define DL_GPIO_PIN_8_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO8_RISE_FALL)

#define DL_GPIO_PIN_9_EDGE_DISABLE              (GPIO_POLARITY15_0_DIO9_DISABLE)

#define DL_GPIO_PIN_9_EDGE_RISE                    (GPIO_POLARITY15_0_DIO9_RISE)

#define DL_GPIO_PIN_9_EDGE_FALL                    (GPIO_POLARITY15_0_DIO9_FALL)

#define DL_GPIO_PIN_9_EDGE_RISE_FALL          (GPIO_POLARITY15_0_DIO9_RISE_FALL)

#define DL_GPIO_PIN_10_EDGE_DISABLE            (GPIO_POLARITY15_0_DIO10_DISABLE)

#define DL_GPIO_PIN_10_EDGE_RISE                  (GPIO_POLARITY15_0_DIO10_RISE)

#define DL_GPIO_PIN_10_EDGE_FALL                  (GPIO_POLARITY15_0_DIO10_FALL)

#define DL_GPIO_PIN_10_EDGE_RISE_FALL        (GPIO_POLARITY15_0_DIO10_RISE_FALL)

#define DL_GPIO_PIN_11_EDGE_DISABLE            (GPIO_POLARITY15_0_DIO11_DISABLE)

#define DL_GPIO_PIN_11_EDGE_RISE                  (GPIO_POLARITY15_0_DIO11_RISE)

#define DL_GPIO_PIN_11_EDGE_FALL                  (GPIO_POLARITY15_0_DIO11_FALL)

#define DL_GPIO_PIN_11_EDGE_RISE_FALL        (GPIO_POLARITY15_0_DIO11_RISE_FALL)

#define DL_GPIO_PIN_12_EDGE_DISABLE            (GPIO_POLARITY15_0_DIO12_DISABLE)

#define DL_GPIO_PIN_12_EDGE_RISE                  (GPIO_POLARITY15_0_DIO12_RISE)

#define DL_GPIO_PIN_12_EDGE_FALL                  (GPIO_POLARITY15_0_DIO12_FALL)

#define DL_GPIO_PIN_12_EDGE_RISE_FALL        (GPIO_POLARITY15_0_DIO12_RISE_FALL)

#define DL_GPIO_PIN_13_EDGE_DISABLE            (GPIO_POLARITY15_0_DIO13_DISABLE)

#define DL_GPIO_PIN_13_EDGE_RISE                  (GPIO_POLARITY15_0_DIO13_RISE)

#define DL_GPIO_PIN_13_EDGE_FALL                  (GPIO_POLARITY15_0_DIO13_FALL)

#define DL_GPIO_PIN_13_EDGE_RISE_FALL        (GPIO_POLARITY15_0_DIO13_RISE_FALL)

#define DL_GPIO_PIN_14_EDGE_DISABLE            (GPIO_POLARITY15_0_DIO14_DISABLE)

#define DL_GPIO_PIN_14_EDGE_RISE                  (GPIO_POLARITY15_0_DIO14_RISE)

#define DL_GPIO_PIN_14_EDGE_FALL                  (GPIO_POLARITY15_0_DIO14_FALL)

#define DL_GPIO_PIN_14_EDGE_RISE_FALL        (GPIO_POLARITY15_0_DIO14_RISE_FALL)

#define DL_GPIO_PIN_15_EDGE_DISABLE            (GPIO_POLARITY15_0_DIO15_DISABLE)

#define DL_GPIO_PIN_15_EDGE_RISE                  (GPIO_POLARITY15_0_DIO15_RISE)

#define DL_GPIO_PIN_15_EDGE_FALL                  (GPIO_POLARITY15_0_DIO15_FALL)

#define DL_GPIO_PIN_15_EDGE_RISE_FALL        (GPIO_POLARITY15_0_DIO15_RISE_FALL)

#define DL_GPIO_PIN_16_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO16_DISABLE)

#define DL_GPIO_PIN_16_EDGE_RISE                 (GPIO_POLARITY31_16_DIO16_RISE)

#define DL_GPIO_PIN_16_EDGE_FALL                 (GPIO_POLARITY31_16_DIO16_FALL)

#define DL_GPIO_PIN_16_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO16_RISE_FALL)

#define DL_GPIO_PIN_17_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO17_DISABLE)

#define DL_GPIO_PIN_17_EDGE_RISE                 (GPIO_POLARITY31_16_DIO17_RISE)

#define DL_GPIO_PIN_17_EDGE_FALL                 (GPIO_POLARITY31_16_DIO17_FALL)

#define DL_GPIO_PIN_17_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO17_RISE_FALL)

#define DL_GPIO_PIN_18_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO18_DISABLE)

#define DL_GPIO_PIN_18_EDGE_RISE                 (GPIO_POLARITY31_16_DIO18_RISE)

#define DL_GPIO_PIN_18_EDGE_FALL                 (GPIO_POLARITY31_16_DIO18_FALL)

#define DL_GPIO_PIN_18_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO18_RISE_FALL)

#define DL_GPIO_PIN_19_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO19_DISABLE)

#define DL_GPIO_PIN_19_EDGE_RISE                 (GPIO_POLARITY31_16_DIO19_RISE)

#define DL_GPIO_PIN_19_EDGE_FALL                 (GPIO_POLARITY31_16_DIO19_FALL)

#define DL_GPIO_PIN_19_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO19_RISE_FALL)

#define DL_GPIO_PIN_20_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO20_DISABLE)

#define DL_GPIO_PIN_20_EDGE_RISE                 (GPIO_POLARITY31_16_DIO20_RISE)

#define DL_GPIO_PIN_20_EDGE_FALL                 (GPIO_POLARITY31_16_DIO20_FALL)

#define DL_GPIO_PIN_20_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO20_RISE_FALL)

#define DL_GPIO_PIN_21_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO21_DISABLE)

#define DL_GPIO_PIN_21_EDGE_RISE                 (GPIO_POLARITY31_16_DIO21_RISE)

#define DL_GPIO_PIN_21_EDGE_FALL                 (GPIO_POLARITY31_16_DIO21_FALL)

#define DL_GPIO_PIN_21_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO21_RISE_FALL)

#define DL_GPIO_PIN_22_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO22_DISABLE)

#define DL_GPIO_PIN_22_EDGE_RISE                 (GPIO_POLARITY31_16_DIO22_RISE)

#define DL_GPIO_PIN_22_EDGE_FALL                 (GPIO_POLARITY31_16_DIO22_FALL)

#define DL_GPIO_PIN_22_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO22_RISE_FALL)

#define DL_GPIO_PIN_23_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO23_DISABLE)

#define DL_GPIO_PIN_23_EDGE_RISE                 (GPIO_POLARITY31_16_DIO23_RISE)

#define DL_GPIO_PIN_23_EDGE_FALL                 (GPIO_POLARITY31_16_DIO23_FALL)

#define DL_GPIO_PIN_23_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO23_RISE_FALL)

#define DL_GPIO_PIN_24_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO24_DISABLE)

#define DL_GPIO_PIN_24_EDGE_RISE                 (GPIO_POLARITY31_16_DIO24_RISE)

#define DL_GPIO_PIN_24_EDGE_FALL                 (GPIO_POLARITY31_16_DIO24_FALL)

#define DL_GPIO_PIN_24_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO24_RISE_FALL)

#define DL_GPIO_PIN_25_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO25_DISABLE)

#define DL_GPIO_PIN_25_EDGE_RISE                 (GPIO_POLARITY31_16_DIO25_RISE)

#define DL_GPIO_PIN_25_EDGE_FALL                 (GPIO_POLARITY31_16_DIO25_FALL)

#define DL_GPIO_PIN_25_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO25_RISE_FALL)

#define DL_GPIO_PIN_26_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO26_DISABLE)

#define DL_GPIO_PIN_26_EDGE_RISE                 (GPIO_POLARITY31_16_DIO26_RISE)

#define DL_GPIO_PIN_26_EDGE_FALL                 (GPIO_POLARITY31_16_DIO26_FALL)

#define DL_GPIO_PIN_26_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO26_RISE_FALL)

#define DL_GPIO_PIN_27_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO27_DISABLE)

#define DL_GPIO_PIN_27_EDGE_RISE                 (GPIO_POLARITY31_16_DIO27_RISE)

#define DL_GPIO_PIN_27_EDGE_FALL                 (GPIO_POLARITY31_16_DIO27_FALL)

#define DL_GPIO_PIN_27_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO27_RISE_FALL)

#define DL_GPIO_PIN_28_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO28_DISABLE)

#define DL_GPIO_PIN_28_EDGE_RISE                 (GPIO_POLARITY31_16_DIO28_RISE)

#define DL_GPIO_PIN_28_EDGE_FALL                 (GPIO_POLARITY31_16_DIO28_FALL)

#define DL_GPIO_PIN_28_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO28_RISE_FALL)

#define DL_GPIO_PIN_29_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO29_DISABLE)

#define DL_GPIO_PIN_29_EDGE_RISE                 (GPIO_POLARITY31_16_DIO29_RISE)

#define DL_GPIO_PIN_29_EDGE_FALL                 (GPIO_POLARITY31_16_DIO29_FALL)

#define DL_GPIO_PIN_29_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO29_RISE_FALL)

#define DL_GPIO_PIN_30_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO30_DISABLE)

#define DL_GPIO_PIN_30_EDGE_RISE                 (GPIO_POLARITY31_16_DIO30_RISE)

#define DL_GPIO_PIN_30_EDGE_FALL                 (GPIO_POLARITY31_16_DIO30_FALL)

#define DL_GPIO_PIN_30_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO30_RISE_FALL)

#define DL_GPIO_PIN_31_EDGE_DISABLE           (GPIO_POLARITY31_16_DIO31_DISABLE)

#define DL_GPIO_PIN_31_EDGE_RISE                 (GPIO_POLARITY31_16_DIO31_RISE)

#define DL_GPIO_PIN_31_EDGE_FALL                 (GPIO_POLARITY31_16_DIO31_FALL)

#define DL_GPIO_PIN_31_EDGE_RISE_FALL       (GPIO_POLARITY31_16_DIO31_RISE_FALL)

#define DL_GPIO_PIN_0_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN0_DISABLE)

#define DL_GPIO_PIN_0_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN0_ONE_CYCLE)

#define DL_GPIO_PIN_0_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN0_THREE_CYCLE)

#define DL_GPIO_PIN_0_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN0_EIGHT_CYCLE)

#define DL_GPIO_PIN_1_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN1_DISABLE)

#define DL_GPIO_PIN_1_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN1_ONE_CYCLE)

#define DL_GPIO_PIN_1_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN1_THREE_CYCLE)

#define DL_GPIO_PIN_1_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN1_EIGHT_CYCLE)

#define DL_GPIO_PIN_2_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN2_DISABLE)

#define DL_GPIO_PIN_2_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN2_ONE_CYCLE)

#define DL_GPIO_PIN_2_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN2_THREE_CYCLE)

#define DL_GPIO_PIN_2_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN2_EIGHT_CYCLE)

#define DL_GPIO_PIN_3_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN3_DISABLE)

#define DL_GPIO_PIN_3_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN3_ONE_CYCLE)

#define DL_GPIO_PIN_3_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN3_THREE_CYCLE)

#define DL_GPIO_PIN_3_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN3_EIGHT_CYCLE)

#define DL_GPIO_PIN_4_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN4_DISABLE)

#define DL_GPIO_PIN_4_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN4_ONE_CYCLE)

#define DL_GPIO_PIN_4_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN4_THREE_CYCLE)

#define DL_GPIO_PIN_4_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN4_EIGHT_CYCLE)

#define DL_GPIO_PIN_5_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN5_DISABLE)

#define DL_GPIO_PIN_5_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN5_ONE_CYCLE)

#define DL_GPIO_PIN_5_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN5_THREE_CYCLE)

#define DL_GPIO_PIN_5_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN5_EIGHT_CYCLE)

#define DL_GPIO_PIN_6_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN6_DISABLE)

#define DL_GPIO_PIN_6_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN6_ONE_CYCLE)

#define DL_GPIO_PIN_6_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN6_THREE_CYCLE)

#define DL_GPIO_PIN_6_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN6_EIGHT_CYCLE)

#define DL_GPIO_PIN_7_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN7_DISABLE)

#define DL_GPIO_PIN_7_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN7_ONE_CYCLE)

#define DL_GPIO_PIN_7_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN7_THREE_CYCLE)

#define DL_GPIO_PIN_7_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN7_EIGHT_CYCLE)

#define DL_GPIO_PIN_8_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN8_DISABLE)

#define DL_GPIO_PIN_8_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN8_ONE_CYCLE)

#define DL_GPIO_PIN_8_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN8_THREE_CYCLE)

#define DL_GPIO_PIN_8_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN8_EIGHT_CYCLE)

#define DL_GPIO_PIN_9_INPUT_FILTER_DISABLE      (GPIO_FILTEREN15_0_DIN9_DISABLE)

#define DL_GPIO_PIN_9_INPUT_FILTER_1_CYCLE    (GPIO_FILTEREN15_0_DIN9_ONE_CYCLE)

#define DL_GPIO_PIN_9_INPUT_FILTER_3_CYCLES  \
                                            (GPIO_FILTEREN15_0_DIN9_THREE_CYCLE)

#define DL_GPIO_PIN_9_INPUT_FILTER_8_CYCLES \
                                            (GPIO_FILTEREN15_0_DIN9_EIGHT_CYCLE)

#define DL_GPIO_PIN_10_INPUT_FILTER_DISABLE     (GPIO_FILTEREN15_0_DIN10_DISABLE)

#define DL_GPIO_PIN_10_INPUT_FILTER_1_CYCLE   (GPIO_FILTEREN15_0_DIN10_ONE_CYCLE)

#define DL_GPIO_PIN_10_INPUT_FILTER_3_CYCLES  \
                                           (GPIO_FILTEREN15_0_DIN10_THREE_CYCLE)

#define DL_GPIO_PIN_10_INPUT_FILTER_8_CYCLES \
                                           (GPIO_FILTEREN15_0_DIN10_EIGHT_CYCLE)

#define DL_GPIO_PIN_11_INPUT_FILTER_DISABLE     (GPIO_FILTEREN15_0_DIN11_DISABLE)

#define DL_GPIO_PIN_11_INPUT_FILTER_1_CYCLE   (GPIO_FILTEREN15_0_DIN11_ONE_CYCLE)

#define DL_GPIO_PIN_11_INPUT_FILTER_3_CYCLES  \
                                           (GPIO_FILTEREN15_0_DIN11_THREE_CYCLE)

#define DL_GPIO_PIN_11_INPUT_FILTER_8_CYCLES \
                                           (GPIO_FILTEREN15_0_DIN11_EIGHT_CYCLE)

#define DL_GPIO_PIN_12_INPUT_FILTER_DISABLE    (GPIO_FILTEREN15_0_DIN12_DISABLE)

#define DL_GPIO_PIN_12_INPUT_FILTER_1_CYCLE  (GPIO_FILTEREN15_0_DIN12_ONE_CYCLE)

#define DL_GPIO_PIN_12_INPUT_FILTER_3_CYCLES  \
                                           (GPIO_FILTEREN15_0_DIN12_THREE_CYCLE)

#define DL_GPIO_PIN_12_INPUT_FILTER_8_CYCLES \
                                           (GPIO_FILTEREN15_0_DIN12_EIGHT_CYCLE)

#define DL_GPIO_PIN_13_INPUT_FILTER_DISABLE    (GPIO_FILTEREN15_0_DIN13_DISABLE)

#define DL_GPIO_PIN_13_INPUT_FILTER_1_CYCLE  (GPIO_FILTEREN15_0_DIN13_ONE_CYCLE)

#define DL_GPIO_PIN_13_INPUT_FILTER_3_CYCLES  \
                                           (GPIO_FILTEREN15_0_DIN13_THREE_CYCLE)

#define DL_GPIO_PIN_13_INPUT_FILTER_8_CYCLES \
                                           (GPIO_FILTEREN15_0_DIN13_EIGHT_CYCLE)

#define DL_GPIO_PIN_14_INPUT_FILTER_DISABLE    (GPIO_FILTEREN15_0_DIN14_DISABLE)

#define DL_GPIO_PIN_14_INPUT_FILTER_1_CYCLE  (GPIO_FILTEREN15_0_DIN14_ONE_CYCLE)

#define DL_GPIO_PIN_14_INPUT_FILTER_3_CYCLES  \
                                           (GPIO_FILTEREN15_0_DIN14_THREE_CYCLE)

#define DL_GPIO_PIN_14_INPUT_FILTER_8_CYCLES \
                                           (GPIO_FILTEREN15_0_DIN14_EIGHT_CYCLE)

#define DL_GPIO_PIN_15_INPUT_FILTER_DISABLE    (GPIO_FILTEREN15_0_DIN15_DISABLE)

#define DL_GPIO_PIN_15_INPUT_FILTER_1_CYCLE  (GPIO_FILTEREN15_0_DIN15_ONE_CYCLE)

#define DL_GPIO_PIN_15_INPUT_FILTER_3_CYCLES  \
                                           (GPIO_FILTEREN15_0_DIN15_THREE_CYCLE)

#define DL_GPIO_PIN_15_INPUT_FILTER_8_CYCLES \
                                           (GPIO_FILTEREN15_0_DIN15_EIGHT_CYCLE)

#define DL_GPIO_PIN_16_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN16_DISABLE)

#define DL_GPIO_PIN_16_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN16_ONE_CYCLE)

#define DL_GPIO_PIN_16_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN16_THREE_CYCLE)

#define DL_GPIO_PIN_16_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN16_EIGHT_CYCLE)

#define DL_GPIO_PIN_17_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN17_DISABLE)

#define DL_GPIO_PIN_17_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN17_ONE_CYCLE)

#define DL_GPIO_PIN_17_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN17_THREE_CYCLE)

#define DL_GPIO_PIN_17_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN17_EIGHT_CYCLE)

#define DL_GPIO_PIN_18_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN18_DISABLE)

#define DL_GPIO_PIN_18_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN18_ONE_CYCLE)

#define DL_GPIO_PIN_18_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN18_THREE_CYCLE)

#define DL_GPIO_PIN_18_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN18_EIGHT_CYCLE)

#define DL_GPIO_PIN_19_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN19_DISABLE)

#define DL_GPIO_PIN_19_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN19_ONE_CYCLE)

#define DL_GPIO_PIN_19_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN19_THREE_CYCLE)

#define DL_GPIO_PIN_19_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN19_EIGHT_CYCLE)

#define DL_GPIO_PIN_20_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN20_DISABLE)

#define DL_GPIO_PIN_20_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN20_ONE_CYCLE)

#define DL_GPIO_PIN_20_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN20_THREE_CYCLE)

#define DL_GPIO_PIN_20_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN20_EIGHT_CYCLE)

#define DL_GPIO_PIN_21_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN21_DISABLE)

#define DL_GPIO_PIN_21_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN21_ONE_CYCLE)

#define DL_GPIO_PIN_21_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN21_THREE_CYCLE)

#define DL_GPIO_PIN_21_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN21_EIGHT_CYCLE)

#define DL_GPIO_PIN_22_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN22_DISABLE)

#define DL_GPIO_PIN_22_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN22_ONE_CYCLE)

#define DL_GPIO_PIN_22_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN22_THREE_CYCLE)

#define DL_GPIO_PIN_22_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN22_EIGHT_CYCLE)

#define DL_GPIO_PIN_23_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN23_DISABLE)

#define DL_GPIO_PIN_23_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN23_ONE_CYCLE)

#define DL_GPIO_PIN_23_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN23_THREE_CYCLE)

#define DL_GPIO_PIN_23_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN23_EIGHT_CYCLE)

#define DL_GPIO_PIN_24_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN24_DISABLE)

#define DL_GPIO_PIN_24_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN24_ONE_CYCLE)

#define DL_GPIO_PIN_24_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN24_THREE_CYCLE)

#define DL_GPIO_PIN_24_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN24_EIGHT_CYCLE)

#define DL_GPIO_PIN_25_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN25_DISABLE)

#define DL_GPIO_PIN_25_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN25_ONE_CYCLE)

#define DL_GPIO_PIN_25_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN25_THREE_CYCLE)

#define DL_GPIO_PIN_25_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN25_EIGHT_CYCLE)

#define DL_GPIO_PIN_26_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN26_DISABLE)

#define DL_GPIO_PIN_26_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN26_ONE_CYCLE)

#define DL_GPIO_PIN_26_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN26_THREE_CYCLE)

#define DL_GPIO_PIN_26_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN26_EIGHT_CYCLE)

#define DL_GPIO_PIN_27_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN27_DISABLE)

#define DL_GPIO_PIN_27_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN27_ONE_CYCLE)

#define DL_GPIO_PIN_27_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN27_THREE_CYCLE)

#define DL_GPIO_PIN_27_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN27_EIGHT_CYCLE)

#define DL_GPIO_PIN_28_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN28_DISABLE)

#define DL_GPIO_PIN_28_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN28_ONE_CYCLE)

#define DL_GPIO_PIN_28_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN28_THREE_CYCLE)

#define DL_GPIO_PIN_28_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN28_EIGHT_CYCLE)

#define DL_GPIO_PIN_29_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN29_DISABLE)

#define DL_GPIO_PIN_29_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN29_ONE_CYCLE)

#define DL_GPIO_PIN_29_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN29_THREE_CYCLE)

#define DL_GPIO_PIN_29_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN29_EIGHT_CYCLE)

#define DL_GPIO_PIN_30_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN30_DISABLE)

#define DL_GPIO_PIN_30_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN30_ONE_CYCLE)

#define DL_GPIO_PIN_30_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN30_THREE_CYCLE)

#define DL_GPIO_PIN_30_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN30_EIGHT_CYCLE)

#define DL_GPIO_PIN_31_INPUT_FILTER_DISABLE   (GPIO_FILTEREN31_16_DIN31_DISABLE)

#define DL_GPIO_PIN_31_INPUT_FILTER_1_CYCLE (GPIO_FILTEREN31_16_DIN31_ONE_CYCLE)

#define DL_GPIO_PIN_31_INPUT_FILTER_3_CYCLES  \
                                          (GPIO_FILTEREN31_16_DIN31_THREE_CYCLE)

#define DL_GPIO_PIN_31_INPUT_FILTER_8_CYCLES \
                                          (GPIO_FILTEREN31_16_DIN31_EIGHT_CYCLE)

/* clang-format on */

typedef enum {
    DL_GPIO_INVERSION_ENABLE = IOMUX_PINCM_INV_ENABLE,
    DL_GPIO_INVERSION_DISABLE = IOMUX_PINCM_INV_DISABLE,
} DL_GPIO_INVERSION;

typedef enum {
    DL_GPIO_DRIVE_STRENGTH_LOW = IOMUX_PINCM_DRV_DRVVAL0,
    DL_GPIO_DRIVE_STRENGTH_HIGH = IOMUX_PINCM_DRV_DRVVAL1,
} DL_GPIO_DRIVE_STRENGTH;

typedef enum {
    DL_GPIO_RESISTOR_NONE =
        (IOMUX_PINCM_PIPU_DISABLE | IOMUX_PINCM_PIPD_DISABLE),

    DL_GPIO_RESISTOR_PULL_UP =
        (IOMUX_PINCM_PIPU_ENABLE | IOMUX_PINCM_PIPD_DISABLE),

    DL_GPIO_RESISTOR_PULL_DOWN =
        (IOMUX_PINCM_PIPU_DISABLE | IOMUX_PINCM_PIPD_ENABLE)
} DL_GPIO_RESISTOR;

typedef enum {
    DL_GPIO_HYSTERESIS_ENABLE = IOMUX_PINCM_HYSTEN_ENABLE,
    DL_GPIO_HYSTERESIS_DISABLE = IOMUX_PINCM_HYSTEN_DISABLE,
} DL_GPIO_HYSTERESIS;

typedef enum {
    DL_GPIO_WAKEUP_ENABLE = IOMUX_PINCM_WUEN_ENABLE,
    DL_GPIO_WAKEUP_DISABLE = IOMUX_PINCM_WUEN_DISABLE,
    DL_GPIO_WAKEUP_ON_0 = (IOMUX_PINCM_WUEN_ENABLE | IOMUX_PINCM_WCOMP_MATCH0),
    DL_GPIO_WAKEUP_ON_1 = (IOMUX_PINCM_WUEN_ENABLE | IOMUX_PINCM_WCOMP_MATCH1),
} DL_GPIO_WAKEUP;

typedef enum {
    DL_GPIO_WAKEUP_COMPARE_VALUE_0 = IOMUX_PINCM_WCOMP_MATCH0,
    DL_GPIO_WAKEUP_COMPARE_VALUE_1 = IOMUX_PINCM_WCOMP_MATCH1,
} DL_GPIO_WAKEUP_COMPARE_VALUE;

typedef enum {
    DL_GPIO_HIZ_ENABLE = IOMUX_PINCM_HIZ1_ENABLE,
    DL_GPIO_HIZ_DISABLE = IOMUX_PINCM_HIZ1_DISABLE,
} DL_GPIO_HIZ;

typedef enum {
    DL_GPIO_EVENT_ROUTE_1 = 0,
    DL_GPIO_EVENT_ROUTE_2 = 12
} DL_GPIO_EVENT_ROUTE;

typedef enum {
    DL_GPIO_PUBLISHER_INDEX_0 = 0,
    DL_GPIO_PUBLISHER_INDEX_1 = 1
} DL_GPIO_PUBLISHER_INDEX;

typedef enum {
    DL_GPIO_SUBSCRIBER_INDEX_0 = 0,
    DL_GPIO_SUBSCRIBER_INDEX_1 = 1
} DL_GPIO_SUBSCRIBER_INDEX;

typedef enum {
    DL_GPIO_SUBSCRIBER_OUT_POLICY_SET = GPIO_SUB0CFG_OUTPOLICY_SET,
    DL_GPIO_SUBSCRIBER_OUT_POLICY_CLEAR = GPIO_SUB0CFG_OUTPOLICY_CLR,
    DL_GPIO_SUBSCRIBER_OUT_POLICY_TOGGLE = GPIO_SUB0CFG_OUTPOLICY_TOGGLE
} DL_GPIO_SUBSCRIBER_OUT_POLICY;

typedef enum {
    DL_GPIO_SUBSCRIBER0_PIN_0 = 0x00000000,
    DL_GPIO_SUBSCRIBER0_PIN_1 = 0x00010000,
    DL_GPIO_SUBSCRIBER0_PIN_2 = 0x00020000,
    DL_GPIO_SUBSCRIBER0_PIN_3 = 0x00030000,
    DL_GPIO_SUBSCRIBER0_PIN_4 = 0x00040000,
    DL_GPIO_SUBSCRIBER0_PIN_5 = 0x00050000,
    DL_GPIO_SUBSCRIBER0_PIN_6 = 0x00060000,
    DL_GPIO_SUBSCRIBER0_PIN_7 = 0x00070000,
    DL_GPIO_SUBSCRIBER0_PIN_8 = 0x00080000,
    DL_GPIO_SUBSCRIBER0_PIN_9 = 0x00090000,
    DL_GPIO_SUBSCRIBER0_PIN_10 = 0x000A0000,
    DL_GPIO_SUBSCRIBER0_PIN_11 = 0x000B0000,
    DL_GPIO_SUBSCRIBER0_PIN_12 = 0x000C0000,
    DL_GPIO_SUBSCRIBER0_PIN_13 = 0x000D0000,
    DL_GPIO_SUBSCRIBER0_PIN_14 = 0x000E0000,
    DL_GPIO_SUBSCRIBER0_PIN_15 = 0x000F0000,
    DL_GPIO_SUBSCRIBER1_PIN_16 = 0x00000000,
    DL_GPIO_SUBSCRIBER1_PIN_17 = 0x00010000,
    DL_GPIO_SUBSCRIBER1_PIN_18 = 0x00020000,
    DL_GPIO_SUBSCRIBER1_PIN_19 = 0x00030000,
    DL_GPIO_SUBSCRIBER1_PIN_20 = 0x00040000,
    DL_GPIO_SUBSCRIBER1_PIN_21 = 0x00050000,
    DL_GPIO_SUBSCRIBER1_PIN_22 = 0x00060000,
    DL_GPIO_SUBSCRIBER1_PIN_23 = 0x00070000,
    DL_GPIO_SUBSCRIBER1_PIN_24 = 0x00080000,
    DL_GPIO_SUBSCRIBER1_PIN_25 = 0x00090000,
    DL_GPIO_SUBSCRIBER1_PIN_26 = 0x000A0000,
    DL_GPIO_SUBSCRIBER1_PIN_27 = 0x000B0000,
    DL_GPIO_SUBSCRIBER1_PIN_28 = 0x000C0000,
    DL_GPIO_SUBSCRIBER1_PIN_29 = 0x000D0000,
    DL_GPIO_SUBSCRIBER1_PIN_30 = 0x000E0000,
    DL_GPIO_SUBSCRIBER1_PIN_31 = 0x000F0000
} DL_GPIO_SUBSCRIBERx_PIN;

typedef enum {
    DL_GPIO_IIDX_NO_INTR = GPIO_CPU_INT_IIDX_STAT_NO_INTR,
    DL_GPIO_IIDX_DIO0 = GPIO_CPU_INT_IIDX_STAT_DIO0,
    DL_GPIO_IIDX_DIO1 = GPIO_CPU_INT_IIDX_STAT_DIO1,
    DL_GPIO_IIDX_DIO2 = GPIO_CPU_INT_IIDX_STAT_DIO2,
    DL_GPIO_IIDX_DIO3 = GPIO_CPU_INT_IIDX_STAT_DIO3,
    DL_GPIO_IIDX_DIO4 = GPIO_CPU_INT_IIDX_STAT_DIO4,
    DL_GPIO_IIDX_DIO5 = GPIO_CPU_INT_IIDX_STAT_DIO5,
    DL_GPIO_IIDX_DIO6 = GPIO_CPU_INT_IIDX_STAT_DIO6,
    DL_GPIO_IIDX_DIO7 = GPIO_CPU_INT_IIDX_STAT_DIO7,
    DL_GPIO_IIDX_DIO8 = GPIO_CPU_INT_IIDX_STAT_DIO8,
    DL_GPIO_IIDX_DIO9 = GPIO_CPU_INT_IIDX_STAT_DIO9,
    DL_GPIO_IIDX_DIO10 = GPIO_CPU_INT_IIDX_STAT_DIO10,
    DL_GPIO_IIDX_DIO11 = GPIO_CPU_INT_IIDX_STAT_DIO11,
    DL_GPIO_IIDX_DIO12 = GPIO_CPU_INT_IIDX_STAT_DIO12,
    DL_GPIO_IIDX_DIO13 = GPIO_CPU_INT_IIDX_STAT_DIO13,
    DL_GPIO_IIDX_DIO14 = GPIO_CPU_INT_IIDX_STAT_DIO14,
    DL_GPIO_IIDX_DIO15 = GPIO_CPU_INT_IIDX_STAT_DIO15,
    DL_GPIO_IIDX_DIO16 = GPIO_CPU_INT_IIDX_STAT_DIO16,
    DL_GPIO_IIDX_DIO17 = GPIO_CPU_INT_IIDX_STAT_DIO17,
    DL_GPIO_IIDX_DIO18 = GPIO_CPU_INT_IIDX_STAT_DIO18,
    DL_GPIO_IIDX_DIO19 = GPIO_CPU_INT_IIDX_STAT_DIO19,
    DL_GPIO_IIDX_DIO20 = GPIO_CPU_INT_IIDX_STAT_DIO20,
    DL_GPIO_IIDX_DIO21 = GPIO_CPU_INT_IIDX_STAT_DIO21,
    DL_GPIO_IIDX_DIO22 = GPIO_CPU_INT_IIDX_STAT_DIO22,
    DL_GPIO_IIDX_DIO23 = GPIO_CPU_INT_IIDX_STAT_DIO23,
    DL_GPIO_IIDX_DIO24 = GPIO_CPU_INT_IIDX_STAT_DIO24,
    DL_GPIO_IIDX_DIO25 = GPIO_CPU_INT_IIDX_STAT_DIO25,
    DL_GPIO_IIDX_DIO26 = GPIO_CPU_INT_IIDX_STAT_DIO26,
    DL_GPIO_IIDX_DIO27 = GPIO_CPU_INT_IIDX_STAT_DIO27,
    DL_GPIO_IIDX_DIO28 = GPIO_CPU_INT_IIDX_STAT_DIO28,
    DL_GPIO_IIDX_DIO29 = GPIO_CPU_INT_IIDX_STAT_DIO29,
    DL_GPIO_IIDX_DIO30 = GPIO_CPU_INT_IIDX_STAT_DIO30,
    DL_GPIO_IIDX_DIO31 = GPIO_CPU_INT_IIDX_STAT_DIO31
} DL_GPIO_IIDX;

__STATIC_INLINE void DL_GPIO_enablePower(GPIO_Regs* gpio)
{
    gpio->GPRCM.PWREN = (GPIO_PWREN_KEY_UNLOCK_W | GPIO_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_GPIO_disablePower(GPIO_Regs* gpio)
{
    gpio->GPRCM.PWREN = (GPIO_PWREN_KEY_UNLOCK_W | GPIO_PWREN_ENABLE_DISABLE);
}

__STATIC_INLINE bool DL_GPIO_isPowerEnabled(GPIO_Regs* gpio)
{
    return ((gpio->GPRCM.PWREN & GPIO_PWREN_ENABLE_MASK) ==
            GPIO_PWREN_ENABLE_ENABLE);
}

__STATIC_INLINE void DL_GPIO_reset(GPIO_Regs* gpio)
{
    gpio->GPRCM.RSTCTL =
        (GPIO_RSTCTL_KEY_UNLOCK_W | GPIO_RSTCTL_RESETSTKYCLR_CLR |
            GPIO_RSTCTL_RESETASSERT_ASSERT);
}

__STATIC_INLINE bool DL_GPIO_isReset(GPIO_Regs* gpio)
{
    return ((gpio->GPRCM.STAT & GPIO_STAT_RESETSTKY_MASK) ==
            GPIO_STAT_RESETSTKY_RESET);
}

__STATIC_INLINE void DL_GPIO_initDigitalOutput(uint32_t pincmIndex)
{
    /* GPIO functionality is always a pin function of 0x00000001 */
    IOMUX->SECCFG.PINCM[pincmIndex] =
        (IOMUX_PINCM_PC_CONNECTED | ((uint32_t) 0x00000001));
}

__STATIC_INLINE void DL_GPIO_initDigitalOutputFeatures(uint32_t pincmIndex,
    DL_GPIO_INVERSION inversion, DL_GPIO_RESISTOR internalResistor,
    DL_GPIO_DRIVE_STRENGTH driveStrength, DL_GPIO_HIZ hiZ)
{
    /* GPIO functionality is always a pin function of 0x00000001 */
    IOMUX->SECCFG.PINCM[pincmIndex] =
        IOMUX_PINCM_PC_CONNECTED | ((uint32_t) 0x00000001) |
        (uint32_t) inversion | (uint32_t) internalResistor |
        (uint32_t) driveStrength | (uint32_t) hiZ;
}

__STATIC_INLINE void DL_GPIO_setDigitalInternalResistor(
    uint32_t pincmIndex, DL_GPIO_RESISTOR internalResistor)
{
    /* GPIO functionality is always a pin function of 0x00000001 */
    IOMUX->SECCFG.PINCM[pincmIndex] = IOMUX_PINCM_PC_CONNECTED |
                                      ((uint32_t) 0x00000001) |
                                      (uint32_t) internalResistor;
}

// TODO: verify no need to add input/output variable for the Input/Output enebale functionality
__STATIC_INLINE void DL_GPIO_setAnalogInternalResistor(
    uint32_t pincmIndex, DL_GPIO_RESISTOR internalResistor)
{
    /* GPIO functionality is always a pin function of 0x00000001 */
    /* For analog use case, setting IOMUX input enable */
    IOMUX->SECCFG.PINCM[pincmIndex] =
        IOMUX_PINCM_INENA_ENABLE | IOMUX_PINCM_PC_UNCONNECTED |
        ((uint32_t) 0x00000001) | (uint32_t) internalResistor;
}

__STATIC_INLINE void DL_GPIO_initDigitalInput(uint32_t pincmIndex)
{
    /* GPIO functionality is always a pin function of 0x00000001 */
    IOMUX->SECCFG.PINCM[pincmIndex] = IOMUX_PINCM_INENA_ENABLE |
                                      IOMUX_PINCM_PC_CONNECTED |
                                      ((uint32_t) 0x00000001);
}

__STATIC_INLINE void DL_GPIO_initDigitalInputFeatures(uint32_t pincmIndex,
    DL_GPIO_INVERSION inversion, DL_GPIO_RESISTOR internalResistor,
    DL_GPIO_HYSTERESIS hysteresis, DL_GPIO_WAKEUP wakeup)
{
    /* GPIO functionality is always a pin function of 0x00000001 */
    IOMUX->SECCFG.PINCM[pincmIndex] =
        IOMUX_PINCM_INENA_ENABLE | IOMUX_PINCM_PC_CONNECTED |
        ((uint32_t) 0x00000001) | (uint32_t) inversion |
        (uint32_t) internalResistor | (uint32_t) hysteresis |
        (uint32_t) wakeup;
}

__STATIC_INLINE void DL_GPIO_initPeripheralFunction(
    uint32_t pincmIndex, uint32_t function)
{
    IOMUX->SECCFG.PINCM[pincmIndex] = function | IOMUX_PINCM_PC_CONNECTED;
}

__STATIC_INLINE void DL_GPIO_initPeripheralOutputFunction(
    uint32_t pincmIndex, uint32_t function)
{
    IOMUX->SECCFG.PINCM[pincmIndex] = function | IOMUX_PINCM_PC_CONNECTED;
}

__STATIC_INLINE void DL_GPIO_initPeripheralOutputFunctionFeatures(
    uint32_t pincmIndex, uint32_t function, DL_GPIO_INVERSION inversion,
    DL_GPIO_RESISTOR internalResistor, DL_GPIO_DRIVE_STRENGTH driveStrength,
    DL_GPIO_HIZ hiZ)
{
    IOMUX->SECCFG.PINCM[pincmIndex] =
        function | IOMUX_PINCM_PC_CONNECTED | (uint32_t) inversion |
        (uint32_t) internalResistor | (uint32_t) driveStrength |
        (uint32_t) hiZ;
}

__STATIC_INLINE void DL_GPIO_initPeripheralInputFunction(
    uint32_t pincmIndex, uint32_t function)
{
    IOMUX->SECCFG.PINCM[pincmIndex] =
        function | IOMUX_PINCM_PC_CONNECTED | IOMUX_PINCM_INENA_ENABLE;
}

__STATIC_INLINE void DL_GPIO_initPeripheralInputFunctionFeatures(
    uint32_t pincmIndex, uint32_t function, DL_GPIO_INVERSION inversion,
    DL_GPIO_RESISTOR internalResistor, DL_GPIO_HYSTERESIS hysteresis,
    DL_GPIO_WAKEUP wakeup)
{
    IOMUX->SECCFG.PINCM[pincmIndex] =
        function | IOMUX_PINCM_PC_CONNECTED | IOMUX_PINCM_INENA_ENABLE |
        (uint32_t) inversion | (uint32_t) internalResistor |
        (uint32_t) hysteresis | (uint32_t) wakeup;
}

__STATIC_INLINE void DL_GPIO_initPeripheralAnalogFunction(uint32_t pincmIndex)
{
    IOMUX->SECCFG.PINCM[pincmIndex] = IOMUX_PINCM_PC_UNCONNECTED;
}

__STATIC_INLINE void DL_GPIO_enableWakeUp(uint32_t pincmIndex)
{
    IOMUX->SECCFG.PINCM[pincmIndex] |= DL_GPIO_WAKEUP_ENABLE;
}

__STATIC_INLINE void DL_GPIO_disableWakeUp(uint32_t pincmIndex)
{
    IOMUX->SECCFG.PINCM[pincmIndex] &= ~(IOMUX_PINCM_WUEN_MASK);
}

__STATIC_INLINE bool DL_GPIO_isWakeUpEnabled(uint32_t pincmIndex)
{
    return ((IOMUX->SECCFG.PINCM[pincmIndex] & IOMUX_PINCM_WUEN_MASK) ==
            IOMUX_PINCM_WUEN_ENABLE);
}

__STATIC_INLINE void DL_GPIO_setWakeupCompareValue(
    uint32_t pincmIndex, DL_GPIO_WAKEUP_COMPARE_VALUE value)
{
    DL_Common_updateReg(&IOMUX->SECCFG.PINCM[pincmIndex], (uint32_t) value,
        IOMUX_PINCM_WCOMP_MASK);
}

__STATIC_INLINE DL_GPIO_WAKEUP_COMPARE_VALUE DL_GPIO_getWakeupCompareValue(
    uint32_t pincmIndex)
{
    uint32_t value = IOMUX->SECCFG.PINCM[pincmIndex] & IOMUX_PINCM_WCOMP_MASK;

    return (DL_GPIO_WAKEUP_COMPARE_VALUE)(value);
}

__STATIC_INLINE bool DL_GPIO_isWakeStateGenerated(uint32_t pincmIndex)
{
    return ((IOMUX->SECCFG.PINCM[pincmIndex] & IOMUX_PINCM_WAKESTAT_MASK) ==
            IOMUX_PINCM_WAKESTAT_ENABLE);
}

__STATIC_INLINE uint32_t DL_GPIO_readPins(GPIO_Regs* gpio, uint32_t pins)
{
    return (gpio->DIN31_0 & pins);
}

__STATIC_INLINE void DL_GPIO_writePins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOUT31_0 = pins;
}

__STATIC_INLINE void DL_GPIO_writePinsVal(
    GPIO_Regs* gpio, uint32_t pinsMask, uint32_t pinsVal)
{
    uint32_t doutVal = gpio->DOUT31_0;
    doutVal &= ~pinsMask;
    doutVal |= (pinsVal & pinsMask);
    gpio->DOUT31_0 = doutVal;
}

__STATIC_INLINE void DL_GPIO_setPins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOUTSET31_0 = pins;
}

__STATIC_INLINE void DL_GPIO_clearPins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOUTCLR31_0 = pins;
}

__STATIC_INLINE void DL_GPIO_togglePins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOUTTGL31_0 = pins;
}

__STATIC_INLINE void DL_GPIO_enableOutput(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOESET31_0 = pins;
}

__STATIC_INLINE void DL_GPIO_disableOutput(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->DOECLR31_0 = pins;
}

__STATIC_INLINE void DL_GPIO_enableDMAAccess(GPIO_Regs* gpio, uint32_t pins)
{
    DL_Common_updateReg(&gpio->DMAMASK, pins, pins);
}

__STATIC_INLINE void DL_GPIO_disableDMAAccess(GPIO_Regs* gpio, uint32_t pins)
{
    DL_Common_updateReg(&gpio->DMAMASK, 0x00000000, pins);
}

__STATIC_INLINE uint32_t DL_GPIO_isDMAccessEnabled(
    GPIO_Regs* gpio, uint32_t pins)
{
    return (gpio->DMAMASK & pins);
}

__STATIC_INLINE void DL_GPIO_setLowerPinsPolarity(
    GPIO_Regs* gpio, uint32_t polarity)
{
    gpio->POLARITY15_0 |= polarity;
}

__STATIC_INLINE void DL_GPIO_setUpperPinsPolarity(
    GPIO_Regs* gpio, uint32_t polarity)
{
    gpio->POLARITY31_16 |= polarity;
}

__STATIC_INLINE uint32_t DL_GPIO_getLowerPinsPolarity(GPIO_Regs* gpio)
{
    return gpio->POLARITY15_0;
}

__STATIC_INLINE uint32_t DL_GPIO_getUpperPinsPolarity(GPIO_Regs* gpio)
{
    return gpio->POLARITY31_16;
}

__STATIC_INLINE void DL_GPIO_setLowerPinsInputFilter(
    GPIO_Regs* gpio, uint32_t filter)
{
    gpio->FILTEREN15_0 |= filter;
}

__STATIC_INLINE void DL_GPIO_setUpperPinsInputFilter(
    GPIO_Regs* gpio, uint32_t filter)
{
    gpio->FILTEREN31_16 |= filter;
}

__STATIC_INLINE uint32_t DL_GPIO_getLowerPinsInputFilter(GPIO_Regs* gpio)
{
    return gpio->FILTEREN15_0;
}

__STATIC_INLINE uint32_t DL_GPIO_getUpperPinsInputFilter(GPIO_Regs* gpio)
{
    return gpio->FILTEREN31_16;
}

__STATIC_INLINE void DL_GPIO_enableGlobalFastWake(GPIO_Regs* gpio)
{
    gpio->CTL |= GPIO_CTL_FASTWAKEONLY_GLOBAL_EN;
}

__STATIC_INLINE void DL_GPIO_disableGlobalFastWake(GPIO_Regs* gpio)
{
    gpio->CTL &= ~GPIO_CTL_FASTWAKEONLY_GLOBAL_EN;
}

__STATIC_INLINE void DL_GPIO_enableFastWakePins(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->FASTWAKE |= pins;
}

__STATIC_INLINE void DL_GPIO_disableFastWakePins(
    GPIO_Regs* gpio, uint32_t pins)
{
    gpio->FASTWAKE &= ~(pins);
}

__STATIC_INLINE void DL_GPIO_enableHiZ(uint32_t pincmIndex)
{
    IOMUX->SECCFG.PINCM[pincmIndex] |= IOMUX_PINCM_HIZ1_ENABLE;
}

__STATIC_INLINE void DL_GPIO_disableHiZ(uint32_t pincmIndex)
{
    IOMUX->SECCFG.PINCM[pincmIndex] &= ~(IOMUX_PINCM_HIZ1_ENABLE);
}

__STATIC_INLINE uint32_t DL_GPIO_getEnabledFastWakePins(
    GPIO_Regs* gpio, uint32_t pins)
{
    return (gpio->FASTWAKE & pins);
}

__STATIC_INLINE void DL_GPIO_enableInterrupt(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->CPU_INT.IMASK |= pins;
}

__STATIC_INLINE void DL_GPIO_disableInterrupt(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->CPU_INT.IMASK &= ~(pins);
}

__STATIC_INLINE uint32_t DL_GPIO_getEnabledInterrupts(
    GPIO_Regs* gpio, uint32_t pins)
{
    return (gpio->CPU_INT.IMASK & pins);
}

__STATIC_INLINE uint32_t DL_GPIO_getEnabledInterruptStatus(
    GPIO_Regs* gpio, uint32_t pins)
{
    return (gpio->CPU_INT.MIS & pins);
}

__STATIC_INLINE void DL_GPIO_setInterrupt(GPIO_Regs* gpio, uint32_t pins)
{
    gpio->CPU_INT.ISET = pins;
}

__STATIC_INLINE uint32_t DL_GPIO_getRawInterruptStatus(
    GPIO_Regs* gpio, uint32_t pins)
{
    return (gpio->CPU_INT.RIS & pins);
}

__STATIC_INLINE DL_GPIO_IIDX DL_GPIO_getPendingInterrupt(GPIO_Regs* gpio)
{
    return (DL_GPIO_IIDX)(gpio->CPU_INT.IIDX);
}

__STATIC_INLINE void DL_GPIO_clearInterruptStatus(
    GPIO_Regs* gpio, uint32_t pins)
{
    gpio->CPU_INT.ICLR |= pins;
}

__STATIC_INLINE void DL_GPIO_configSubscriber(GPIO_Regs* gpio,
    DL_GPIO_SUBSCRIBER_INDEX index, DL_GPIO_SUBSCRIBER_OUT_POLICY policy,
    DL_GPIO_SUBSCRIBERx_PIN pinIndex)

{
    volatile uint32_t* pReg = &gpio->SUB0CFG;

    pReg += ((uint32_t) index << 3);

    DL_Common_updateReg(pReg, ((uint32_t) pinIndex | (uint32_t) policy),
        (GPIO_SUB0CFG_INDEX_MASK | GPIO_SUB1CFG_OUTPOLICY_MASK));
}

__STATIC_INLINE void DL_GPIO_enableSubscriber(
    GPIO_Regs* gpio, DL_GPIO_SUBSCRIBER_INDEX index)
{
    volatile uint32_t* pReg = &gpio->SUB0CFG;

    pReg += ((uint32_t) index << 3);
    *(pReg) |= (GPIO_SUB1CFG_ENABLE_SET);
}

__STATIC_INLINE void DL_GPIO_disableSubscriber(
    GPIO_Regs* gpio, DL_GPIO_SUBSCRIBER_INDEX index)
{
    volatile uint32_t* pReg = &gpio->SUB0CFG;

    pReg += ((uint32_t) index << 3);
    *(pReg) &= ~(GPIO_SUB1CFG_ENABLE_SET);
}

__STATIC_INLINE bool DL_GPIO_isSubscriberEnabled(
    GPIO_Regs* gpio, DL_GPIO_SUBSCRIBER_INDEX index)
{
    volatile uint32_t* pReg = &gpio->SUB0CFG;

    pReg += ((uint32_t) index << 3);
    return (GPIO_SUB1CFG_ENABLE_SET == (*(pReg) &GPIO_SUB1CFG_ENABLE_MASK));
}

__STATIC_INLINE void DL_GPIO_setPublisherChanID(
    GPIO_Regs* gpio, DL_GPIO_PUBLISHER_INDEX index, uint8_t chanID)
{
    volatile uint32_t* pReg = &gpio->FPUB_0;

    *(pReg + (uint32_t) index) =
        ((uint32_t) chanID & GPIO_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_GPIO_getPublisherChanID(
    GPIO_Regs* gpio, DL_GPIO_PUBLISHER_INDEX index)
{
    volatile uint32_t* pReg = &gpio->FPUB_0;

    return ((uint8_t)(*(pReg + (uint32_t) index) & GPIO_FPUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_GPIO_setSubscriberChanID(
    GPIO_Regs* gpio, DL_GPIO_SUBSCRIBER_INDEX index, uint8_t chanID)
{
    volatile uint32_t* pReg = &gpio->FSUB_0;

    *(pReg + (uint32_t) index) =
        ((uint32_t) chanID & GPIO_FSUB_0_CHANID_MAXIMUM);
}

__STATIC_INLINE uint8_t DL_GPIO_getSubscriberChanID(
    GPIO_Regs* gpio, DL_GPIO_SUBSCRIBER_INDEX index)
{
    volatile uint32_t* pReg = &gpio->FSUB_0;

    return ((uint8_t)(*(pReg + (uint32_t) index) & GPIO_FSUB_0_CHANID_MASK));
}

__STATIC_INLINE void DL_GPIO_enableEvents(
    GPIO_Regs* gpio, DL_GPIO_EVENT_ROUTE index, uint32_t pins)
{
    switch (index) {
        case DL_GPIO_EVENT_ROUTE_1:
            gpio->GEN_EVENT0.IMASK |= (pins & 0x0000FFFFU);
            break;
        case DL_GPIO_EVENT_ROUTE_2:
            gpio->GEN_EVENT1.IMASK |= (pins & 0xFFFF0000U);
            break;
        default:
            break;
    }
}

__STATIC_INLINE void DL_GPIO_disableEvents(
    GPIO_Regs* gpio, DL_GPIO_EVENT_ROUTE index, uint32_t pins)
{
    switch (index) {
        case DL_GPIO_EVENT_ROUTE_1:
            gpio->GEN_EVENT0.IMASK &= ~(pins & 0x0000FFFFU);
            break;
        case DL_GPIO_EVENT_ROUTE_2:
            gpio->GEN_EVENT1.IMASK &= ~(pins & 0xFFFF0000U);
            break;
        default:
            break;
    }
}

__STATIC_INLINE uint32_t DL_GPIO_getEnabledEvents(
    GPIO_Regs* gpio, DL_GPIO_EVENT_ROUTE index, uint32_t pins)
{
    volatile uint32_t* pReg = &gpio->GEN_EVENT0.IMASK;

    return ((*(pReg + (uint32_t) index) & pins));
}

__STATIC_INLINE uint32_t DL_GPIO_getEnabledEventStatus(
    GPIO_Regs* gpio, DL_GPIO_EVENT_ROUTE index, uint32_t pins)
{
    const volatile uint32_t* pReg = &gpio->GEN_EVENT0.MIS;

    return ((*(pReg + (uint32_t) index) & pins));
}

__STATIC_INLINE void DL_GPIO_clearEventStatus(
    GPIO_Regs* gpio, DL_GPIO_EVENT_ROUTE index, uint32_t pins)
{
    switch (index) {
        case DL_GPIO_EVENT_ROUTE_1:
            gpio->GEN_EVENT0.ICLR |= (pins & 0x0000FFFFU);
            break;
        case DL_GPIO_EVENT_ROUTE_2:
            gpio->GEN_EVENT1.ICLR |= (pins & 0xFFFF0000U);
            break;
        default:
            break;
    }
}

#ifdef __cplusplus
}
#endif

#endif /* __MSPM0_HAS_GPIO__ */

#endif /* ti_dl_dl_gpio__include */