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MSPM0C1105_C1106 Driver Library
2.05.01.00
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Analog to Digital Converter (ADC)
#include <math.h>#include <stdbool.h>#include <stdint.h>#include <ti/devices/msp/msp.h>#include <ti/driverlib/dl_common.h>#include <ti/driverlib/m0p/dl_factoryregion.h>
Go to the source code of this file.
Data Structures | |
| struct | DL_ADC12_ClockConfig |
| Configuration struct for DL_ADC12_setClockConfig. More... | |
Macros | |
| #define | DL_ADC12_SEQ_END_ADDR_00 (ADC12_CTL2_ENDADD_ADDR_00) |
| Sequence end address set to 00. | |
| #define | DL_ADC12_SEQ_END_ADDR_01 (ADC12_CTL2_ENDADD_ADDR_01) |
| Sequence end address set to 01. | |
| #define | DL_ADC12_SEQ_END_ADDR_02 (ADC12_CTL2_ENDADD_ADDR_02) |
| Sequence end address set to 02. | |
| #define | DL_ADC12_SEQ_END_ADDR_03 (ADC12_CTL2_ENDADD_ADDR_03) |
| Sequence end address set to 03. | |
| #define | DL_ADC12_SEQ_END_ADDR_04 (ADC12_CTL2_ENDADD_ADDR_04) |
| Sequence end address set to 04. | |
| #define | DL_ADC12_SEQ_END_ADDR_05 (ADC12_CTL2_ENDADD_ADDR_05) |
| Sequence end address set to 05. | |
| #define | DL_ADC12_SEQ_END_ADDR_06 (ADC12_CTL2_ENDADD_ADDR_06) |
| Sequence end address set to 06. | |
| #define | DL_ADC12_SEQ_END_ADDR_07 (ADC12_CTL2_ENDADD_ADDR_07) |
| Sequence end address set to 07. | |
| #define | DL_ADC12_SEQ_END_ADDR_08 (ADC12_CTL2_ENDADD_ADDR_08) |
| Sequence end address set to 08. | |
| #define | DL_ADC12_SEQ_END_ADDR_09 (ADC12_CTL2_ENDADD_ADDR_09) |
| Sequence end address set to 09. | |
| #define | DL_ADC12_SEQ_END_ADDR_10 (ADC12_CTL2_ENDADD_ADDR_10) |
| Sequence end address set to 10. | |
| #define | DL_ADC12_SEQ_END_ADDR_11 (ADC12_CTL2_ENDADD_ADDR_11) |
| Sequence end address set to 11. | |
| #define | DL_ADC12_SEQ_START_ADDR_00 (ADC12_CTL2_STARTADD_ADDR_00) |
| Sequence start address set to 00. | |
| #define | DL_ADC12_SEQ_START_ADDR_01 (ADC12_CTL2_STARTADD_ADDR_01) |
| Sequence start address set to 01. | |
| #define | DL_ADC12_SEQ_START_ADDR_02 (ADC12_CTL2_STARTADD_ADDR_02) |
| Sequence start address set to 02. | |
| #define | DL_ADC12_SEQ_START_ADDR_03 (ADC12_CTL2_STARTADD_ADDR_03) |
| Sequence start address set to 03. | |
| #define | DL_ADC12_SEQ_START_ADDR_04 (ADC12_CTL2_STARTADD_ADDR_04) |
| Sequence start address set to 04. | |
| #define | DL_ADC12_SEQ_START_ADDR_05 (ADC12_CTL2_STARTADD_ADDR_05) |
| Sequence start address set to 05. | |
| #define | DL_ADC12_SEQ_START_ADDR_06 (ADC12_CTL2_STARTADD_ADDR_06) |
| Sequence start address set to 06. | |
| #define | DL_ADC12_SEQ_START_ADDR_07 (ADC12_CTL2_STARTADD_ADDR_07) |
| Sequence start address set to 07. | |
| #define | DL_ADC12_SEQ_START_ADDR_08 (ADC12_CTL2_STARTADD_ADDR_08) |
| Sequence start address set to 08. | |
| #define | DL_ADC12_SEQ_START_ADDR_09 (ADC12_CTL2_STARTADD_ADDR_09) |
| Sequence start address set to 09. | |
| #define | DL_ADC12_SEQ_START_ADDR_10 (ADC12_CTL2_STARTADD_ADDR_10) |
| Sequence start address set to 10. | |
| #define | DL_ADC12_SEQ_START_ADDR_11 (ADC12_CTL2_STARTADD_ADDR_11) |
| Sequence start address set to 11. | |
| #define | DL_ADC12_SAMP_MODE_SINGLE (ADC12_CTL1_CONSEQ_SINGLE) |
| Single sample mode selected. | |
| #define | DL_ADC12_SAMP_MODE_SINGLE_REPEAT (ADC12_CTL1_CONSEQ_REPEATSINGLE) |
| Repeat single sample mode selected. | |
| #define | DL_ADC12_SAMP_MODE_SEQUENCE (ADC12_CTL1_CONSEQ_SEQUENCE) |
| Sequence sample mode selected. | |
| #define | DL_ADC12_SAMP_MODE_SEQUENCE_REPEAT (ADC12_CTL1_CONSEQ_REPEATSEQUENCE) |
| Repeat sequence sample mode selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_DISABLED (ADC12_CTL1_AVGN_DISABLE) |
| Doesn't accumulate conversions. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_2 (ADC12_CTL1_AVGN_AVG_2) |
| Accumulates 2 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_4 (ADC12_CTL1_AVGN_AVG_4) |
| Accumulates 4 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_8 (ADC12_CTL1_AVGN_AVG_8) |
| Accumulates 8 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_16 (ADC12_CTL1_AVGN_AVG_16) |
| Accumulates 16 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_32 (ADC12_CTL1_AVGN_AVG_32) |
| Accumulates 32 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_64 (ADC12_CTL1_AVGN_AVG_64) |
| Accumulates 64 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_NUM_ACC_128 (ADC12_CTL1_AVGN_AVG_128) |
| Accumulates 128 conversions and then is get divided by the denominator selected. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_1 (ADC12_CTL1_AVGD_SHIFT0) |
| Accumulated conversions are divided by 1. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_2 (ADC12_CTL1_AVGD_SHIFT1) |
| Accumulated conversions are divided by 2. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_4 (ADC12_CTL1_AVGD_SHIFT2) |
| Accumulated conversions are divided by 4. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_8 (ADC12_CTL1_AVGD_SHIFT3) |
| Accumulated conversions are divided by 8. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_16 (ADC12_CTL1_AVGD_SHIFT4) |
| Accumulated conversions are divided by 16. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_32 (ADC12_CTL1_AVGD_SHIFT5) |
| Accumulated conversions are divided by 32. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_64 (ADC12_CTL1_AVGD_SHIFT6) |
| Accumulated conversions are divided by 64. | |
| #define | DL_ADC12_HW_AVG_DEN_DIV_BY_128 (ADC12_CTL1_AVGD_SHIFT7) |
| Accumulated conversions are divided by 128. | |
| #define | DL_ADC12_POWER_DOWN_MODE_AUTO (ADC12_CTL0_PWRDN_AUTO) |
| ADC12 power down mode auto. | |
| #define | DL_ADC12_POWER_DOWN_MODE_MANUAL (ADC12_CTL0_PWRDN_MANUAL) |
| ADC12 power down mode manual. | |
| #define | DL_ADC12_INPUT_CHAN_0 (ADC12_MEMCTL_CHANSEL_CHAN_0) |
| ADC12 input channel 0 selected. | |
| #define | DL_ADC12_INPUT_CHAN_1 (ADC12_MEMCTL_CHANSEL_CHAN_1) |
| ADC12 input channel 1 selected. | |
| #define | DL_ADC12_INPUT_CHAN_2 (ADC12_MEMCTL_CHANSEL_CHAN_2) |
| ADC12 input channel 2 selected. | |
| #define | DL_ADC12_INPUT_CHAN_3 (ADC12_MEMCTL_CHANSEL_CHAN_3) |
| ADC12 input channel 3 selected. | |
| #define | DL_ADC12_INPUT_CHAN_4 (ADC12_MEMCTL_CHANSEL_CHAN_4) |
| ADC12 input channel 4 selected. | |
| #define | DL_ADC12_INPUT_CHAN_5 (ADC12_MEMCTL_CHANSEL_CHAN_5) |
| ADC12 input channel 5 selected. | |
| #define | DL_ADC12_INPUT_CHAN_6 (ADC12_MEMCTL_CHANSEL_CHAN_6) |
| ADC12 input channel 6 selected. | |
| #define | DL_ADC12_INPUT_CHAN_7 (ADC12_MEMCTL_CHANSEL_CHAN_7) |
| ADC12 input channel 7 selected. | |
| #define | DL_ADC12_INPUT_CHAN_8 (ADC12_MEMCTL_CHANSEL_CHAN_8) |
| ADC12 input channel 8 selected. | |
| #define | DL_ADC12_INPUT_CHAN_9 (ADC12_MEMCTL_CHANSEL_CHAN_9) |
| ADC12 input channel 9 selected. | |
| #define | DL_ADC12_INPUT_CHAN_10 (ADC12_MEMCTL_CHANSEL_CHAN_10) |
| ADC12 input channel 10 selected. | |
| #define | DL_ADC12_INPUT_CHAN_11 (ADC12_MEMCTL_CHANSEL_CHAN_11) |
| ADC12 input channel 11 selected. | |
| #define | DL_ADC12_INPUT_CHAN_12 (ADC12_MEMCTL_CHANSEL_CHAN_12) |
| ADC12 input channel 12 selected. | |
| #define | DL_ADC12_INPUT_CHAN_13 (ADC12_MEMCTL_CHANSEL_CHAN_13) |
| ADC12 input channel 13 selected. | |
| #define | DL_ADC12_INPUT_CHAN_14 (ADC12_MEMCTL_CHANSEL_CHAN_14) |
| ADC12 input channel 14 selected. | |
| #define | DL_ADC12_INPUT_CHAN_15 (ADC12_MEMCTL_CHANSEL_CHAN_15) |
| ADC12 input channel 15 selected. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_VDDA (ADC12_MEMCTL_VRSEL_VDDA_VSSA) |
| ADC12 voltage reference VDDA. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_EXTREF (ADC12_MEMCTL_VRSEL_EXTREF_VREFM) |
| ADC12 voltage reference external. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_INTREF (ADC12_MEMCTL_VRSEL_INTREF_VSSA) |
| ADC12 voltage reference internal. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_VDDA_VSSA (ADC12_MEMCTL_VRSEL_VDDA_VSSA) |
| ADC12 voltage reference VDDA. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_EXTREF_VREFM (ADC12_MEMCTL_VRSEL_EXTREF_VREFM) |
| ADC12 voltage reference external. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_INTREF_VSSA (ADC12_MEMCTL_VRSEL_INTREF_VSSA) |
| ADC12 voltage reference internal. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_VDDA_VREFM (ADC12_MEMCTL_VRSEL_VDDA_VREFM) |
| ADC12 voltage reference VDDA and VREFM connected to VREF+. | |
| #define | DL_ADC12_REFERENCE_VOLTAGE_INTREF_VREFM (ADC12_MEMCTL_VRSEL_INTREF_VREFM) |
| ADC12 voltage reference INTREF and VREFM connected to VREF+ and VREF-. | |
| #define | DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0 (ADC12_MEMCTL_STIME_SEL_SCOMP0) |
| ADC12 sample adc12 source 0. | |
| #define | DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP1 (ADC12_MEMCTL_STIME_SEL_SCOMP1) |
| ADC12 sample adc12 source 1. | |
| #define | DL_ADC12_AVERAGING_MODE_ENABLED (ADC12_MEMCTL_AVGEN_ENABLE) |
| ADC12 averaging mode enabled. | |
| #define | DL_ADC12_AVERAGING_MODE_DISABLED (ADC12_MEMCTL_AVGEN_DISABLE) |
| ADC12 averaging mode disabled. | |
| #define | DL_ADC12_BURN_OUT_SOURCE_ENABLED (ADC12_MEMCTL_BCSEN_ENABLE) |
| ADC12 burn out current source enabled. | |
| #define | DL_ADC12_BURN_OUT_SOURCE_DISABLED (ADC12_MEMCTL_BCSEN_DISABLE) |
| ADC12 burn out current source enabled. | |
| #define | DL_ADC12_TRIGGER_MODE_AUTO_NEXT (ADC12_MEMCTL_TRIG_AUTO_NEXT) |
| ADC12 trigger automaticaly step to next memory conversion register. | |
| #define | DL_ADC12_TRIGGER_MODE_TRIGGER_NEXT (ADC12_MEMCTL_TRIG_TRIGGER_NEXT) |
| ADC12 valid trigger will step to next memory conversion register. | |
| #define | DL_ADC12_WINDOWS_COMP_MODE_ENABLED (ADC12_MEMCTL_WINCOMP_ENABLE) |
| ADC12 window comparator enabled. | |
| #define | DL_ADC12_WINDOWS_COMP_MODE_DISABLED (ADC12_MEMCTL_WINCOMP_DISABLE) |
| ADC12 window comparator disabled. | |
| #define | DL_ADC12_STATUS_CONVERSION_ACTIVE (ADC12_STATUS_BUSY_ACTIVE) |
| Indicates sample or conversion is in progress. | |
| #define | DL_ADC12_STATUS_CONVERSION_IDLE (ADC12_STATUS_BUSY_IDLE) |
| Indicates sample or conversion is not in progress. | |
| #define | DL_ADC12_STATUS_REFERENCE_READY (ADC12_STATUS_REFBUFRDY_READY) |
| Indicates reference buffer is powered up and ready. | |
| #define | DL_ADC12_STATUS_REFERENCE_NOTREADY (ADC12_STATUS_REFBUFRDY_NOTREADY) |
| Indicates reference buffer is not ready. | |
| #define | DL_ADC12_INTERRUPT_OVERFLOW (ADC12_CPU_INT_IMASK_OVIFG_SET) |
| ADC12 MEMRESX overflow. | |
| #define | DL_ADC12_INTERRUPT_TRIG_OVF (ADC12_CPU_INT_IMASK_TOVIFG_SET) |
| ADC12 sequence conversion trigger overflow. | |
| #define | DL_ADC12_INTERRUPT_WINDOW_COMP_HIGH (ADC12_CPU_INT_IMASK_HIGHIFG_SET) |
| ADC12 MEMRESx result higher than window comparator high threshold. | |
| #define | DL_ADC12_INTERRUPT_WINDOW_COMP_LOW (ADC12_CPU_INT_IMASK_LOWIFG_SET) |
| ADC12 MEMRESx result lower than window comparator low threshold. | |
| #define | DL_ADC12_INTERRUPT_INIFG (ADC12_CPU_INT_IMASK_INIFG_SET) |
| ADC12 MEMRESx result is between low and high window comparator threshold. | |
| #define | DL_ADC12_INTERRUPT_DMA_DONE (ADC12_CPU_INT_IMASK_DMADONE_SET) |
| ADC12 DMA done. | |
| #define | DL_ADC12_INTERRUPT_UNDERFLOW (ADC12_CPU_INT_IMASK_UVIFG_SET) |
| ADC12 MEMRESX underflow. | |
| #define | DL_ADC12_INTERRUPT_MEM0_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG0_SET) |
| ADC12 MEM0 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM1_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG1_SET) |
| ADC12 MEM1 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM2_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG2_SET) |
| ADC12 MEM2 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM3_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG3_SET) |
| ADC12 MEM3 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM4_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG4_SET) |
| ADC12 MEM4 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM5_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG5_SET) |
| ADC12 MEM5 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM6_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG6_SET) |
| ADC12 MEM6 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM7_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG7_SET) |
| ADC12 MEM7 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM8_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG8_SET) |
| ADC12 MEM8 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM9_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG9_SET) |
| ADC12 MEM9 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM10_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG10_SET) |
| ADC12 MEM10 result loaded interrupt. | |
| #define | DL_ADC12_INTERRUPT_MEM11_RESULT_LOADED (ADC12_CPU_INT_IMASK_MEMRESIFG11_SET) |
| ADC12 MEM12 result loaded interrupt. | |
| #define | DL_ADC12_EVENT_WINDOW_COMP_HIGH (ADC12_GEN_EVENT_IMASK_HIGHIFG_SET) |
| ADC12 MEMRESx result higher than window comparator high threshold. | |
| #define | DL_ADC12_EVENT_WINDOW_COMP_LOW (ADC12_GEN_EVENT_IMASK_LOWIFG_SET) |
| ADC12 MEMRESx result lower than window comparator low threshold. | |
| #define | DL_ADC12_EVENT_INIFG (ADC12_GEN_EVENT_IMASK_INIFG_SET) |
| ADC12 MEMRESx result between high and low window comparator threshold. | |
| #define | DL_ADC12_EVENT_MEM0_RESULT_LOADED (ADC12_GEN_EVENT_IMASK_MEMRESIFG0_SET) |
| ADC12 MEM0 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM0_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG0_SET) |
| ADC12 MEM0 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM1_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG1_SET) |
| ADC12 MEM1 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM2_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG2_SET) |
| ADC12 MEM2 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM3_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG3_SET) |
| ADC12 MEM3 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM4_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG4_SET) |
| ADC12 MEM4 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM5_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG5_SET) |
| ADC12 MEM5 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM6_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG6_SET) |
| ADC12 MEM6 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM7_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG7_SET) |
| ADC12 MEM7 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM8_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG8_SET) |
| ADC12 MEM8 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM9_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG9_SET) |
| ADC12 MEM9 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM10_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG10_SET) |
| ADC12 MEM10 result loaded interrupt. | |
| #define | DL_ADC12_DMA_MEM11_RESULT_LOADED (ADC12_DMA_TRIG_IMASK_MEMRESIFG11_SET) |
| ADC12 MEM11 result loaded interrupt. | |
| #define | DL_ADC12_SVT_OFFSET ((uint32_t)0x555000 >> (uint32_t)2) |
| This is an internal macro is used to resolve the offset to ADC12 SVT. More... | |
Enumerations | |
| enum | DL_ADC12_MEM_IDX { DL_ADC12_MEM_IDX_0 = 0, DL_ADC12_MEM_IDX_1 = 1, DL_ADC12_MEM_IDX_2 = 2, DL_ADC12_MEM_IDX_3 = 3, DL_ADC12_MEM_IDX_4 = 4, DL_ADC12_MEM_IDX_5 = 5, DL_ADC12_MEM_IDX_6 = 6, DL_ADC12_MEM_IDX_7 = 7, DL_ADC12_MEM_IDX_8 = 8, DL_ADC12_MEM_IDX_9 = 9, DL_ADC12_MEM_IDX_10 = 10, DL_ADC12_MEM_IDX_11 = 11 } |
| enum | DL_ADC12_REPEAT_MODE { DL_ADC12_REPEAT_MODE_ENABLED = ADC12_CTL1_CONSEQ_REPEATSINGLE, DL_ADC12_REPEAT_MODE_DISABLED = ADC12_CTL1_CONSEQ_SINGLE } |
| enum | DL_ADC12_SAMPLING_SOURCE { DL_ADC12_SAMPLING_SOURCE_AUTO = ADC12_CTL1_SAMPMODE_AUTO, DL_ADC12_SAMPLING_SOURCE_MANUAL = ADC12_CTL1_SAMPMODE_MANUAL } |
| enum | DL_ADC12_TRIG_SRC { DL_ADC12_TRIG_SRC_SOFTWARE = ADC12_CTL1_TRIGSRC_SOFTWARE, DL_ADC12_TRIG_SRC_EVENT = ADC12_CTL1_TRIGSRC_EVENT } |
| enum | DL_ADC12_SAMP_CONV_RES { DL_ADC12_SAMP_CONV_RES_12_BIT = ADC12_CTL2_RES_BIT_12, DL_ADC12_SAMP_CONV_RES_10_BIT = ADC12_CTL2_RES_BIT_10, DL_ADC12_SAMP_CONV_RES_8_BIT = ADC12_CTL2_RES_BIT_8 } |
| enum | DL_ADC12_SAMP_CONV_DATA_FORMAT { DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED = ADC12_CTL2_DF_UNSIGNED, DL_ADC12_SAMP_CONV_DATA_FORMAT_SIGNED = ADC12_CTL2_DF_SIGNED } |
| enum | DL_ADC12_IIDX { DL_ADC12_IIDX_OVERFLOW = ADC12_CPU_INT_IIDX_STAT_OVIFG, DL_ADC12_IIDX_TRIG_OVERFLOW = ADC12_CPU_INT_IIDX_STAT_TOVIFG, DL_ADC12_IIDX_WINDOW_COMP_HIGH = ADC12_CPU_INT_IIDX_STAT_HIGHIFG, DL_ADC12_IIDX_WINDOW_COMP_LOW = ADC12_CPU_INT_IIDX_STAT_LOWIFG, DL_ADC12_IIDX_INIFG = ADC12_CPU_INT_IIDX_STAT_INIFG, DL_ADC12_IIDX_DMA_DONE = ADC12_CPU_INT_IIDX_STAT_DMADONE, DL_ADC12_IIDX_UNDERFLOW = ADC12_CPU_INT_IIDX_STAT_UVIFG, DL_ADC12_IIDX_MEM0_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG0, DL_ADC12_IIDX_MEM1_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG1, DL_ADC12_IIDX_MEM2_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG2, DL_ADC12_IIDX_MEM3_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG3, DL_ADC12_IIDX_MEM4_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG4, DL_ADC12_IIDX_MEM5_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG5, DL_ADC12_IIDX_MEM6_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG6, DL_ADC12_IIDX_MEM7_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG7, DL_ADC12_IIDX_MEM8_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG8, DL_ADC12_IIDX_MEM9_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG9, DL_ADC12_IIDX_MEM10_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG10, DL_ADC12_IIDX_MEM11_RESULT_LOADED = ADC12_CPU_INT_IIDX_STAT_MEMRESIFG11 } |
| enum | DL_ADC12_CLOCK { DL_ADC12_CLOCK_SYSOSC = ADC12_CLKCFG_SAMPCLK_SYSOSC, DL_ADC12_CLOCK_ULPCLK = ADC12_CLKCFG_SAMPCLK_ULPCLK, DL_ADC12_CLOCK_HFCLK = ADC12_CLKCFG_SAMPCLK_HFCLK } |
| enum | DL_ADC12_CLOCK_DIVIDE { DL_ADC12_CLOCK_DIVIDE_1 = ADC12_CTL0_SCLKDIV_DIV_BY_1, DL_ADC12_CLOCK_DIVIDE_2 = ADC12_CTL0_SCLKDIV_DIV_BY_2, DL_ADC12_CLOCK_DIVIDE_4 = ADC12_CTL0_SCLKDIV_DIV_BY_4, DL_ADC12_CLOCK_DIVIDE_8 = ADC12_CTL0_SCLKDIV_DIV_BY_8, DL_ADC12_CLOCK_DIVIDE_16 = ADC12_CTL0_SCLKDIV_DIV_BY_16, DL_ADC12_CLOCK_DIVIDE_24 = ADC12_CTL0_SCLKDIV_DIV_BY_24, DL_ADC12_CLOCK_DIVIDE_32 = ADC12_CTL0_SCLKDIV_DIV_BY_32, DL_ADC12_CLOCK_DIVIDE_48 = ADC12_CTL0_SCLKDIV_DIV_BY_48 } |
| enum | DL_ADC12_CLOCK_FREQ_RANGE { DL_ADC12_CLOCK_FREQ_RANGE_1_TO_4 = ADC12_CLKFREQ_FRANGE_RANGE1TO4, DL_ADC12_CLOCK_FREQ_RANGE_4_TO_8 = ADC12_CLKFREQ_FRANGE_RANGE4TO8, DL_ADC12_CLOCK_FREQ_RANGE_8_TO_16 = ADC12_CLKFREQ_FRANGE_RANGE8TO16, DL_ADC12_CLOCK_FREQ_RANGE_16_TO_20 = ADC12_CLKFREQ_FRANGE_RANGE16TO20, DL_ADC12_CLOCK_FREQ_RANGE_20_TO_24 = ADC12_CLKFREQ_FRANGE_RANGE20TO24, DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32 = ADC12_CLKFREQ_FRANGE_RANGE24TO32, DL_ADC12_CLOCK_FREQ_RANGE_32_TO_40 = ADC12_CLKFREQ_FRANGE_RANGE32TO40, DL_ADC12_CLOCK_FREQ_RANGE_40_TO_48 = ADC12_CLKFREQ_FRANGE_RANGE40TO48 } |
Functions | |
| __STATIC_INLINE void | DL_ADC12_enablePower (ADC12_Regs *adc12) |
| Enables the Peripheral Write Enable (PWREN) register for the ADC12. More... | |
| __STATIC_INLINE void | DL_ADC12_disablePower (ADC12_Regs *adc12) |
| Disables the Peripheral Write Enable (PWREN) register for the ADC12. More... | |
| __STATIC_INLINE bool | DL_ADC12_isPowerEnabled (const ADC12_Regs *adc12) |
| Returns if the Peripheral Write Enable (PWREN) register for the ADC12 is enabled. More... | |
| __STATIC_INLINE void | DL_ADC12_reset (ADC12_Regs *adc12) |
| Resets adc12 peripheral. More... | |
| __STATIC_INLINE bool | DL_ADC12_isReset (const ADC12_Regs *adc12) |
| Returns if adc12 peripheral was reset. More... | |
| __STATIC_INLINE void | DL_ADC12_initSingleSample (ADC12_Regs *adc12, uint32_t repeatMode, uint32_t sampleMode, uint32_t trigSrc, uint32_t resolution, uint32_t dataFormat) |
| Initializes ADC12 for single sampling mode operation. This initialization configures MEMCTL0 as the default memory control register for the conversion. If the conversion needs use a different memory control register the user can call DL_ADC12_setStartAddress to specify a different control register. More... | |
| __STATIC_INLINE void | DL_ADC12_setStartAddress (ADC12_Regs *adc12, uint32_t startAdd) |
| Sets the start address for ADC conversion. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getStartAddress (const ADC12_Regs *adc12) |
| Gets start address for ADC conversion. More... | |
| __STATIC_INLINE void | DL_ADC12_setEndAddress (ADC12_Regs *adc12, uint32_t endAdd) |
| Sets the end address for ADC conversion. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEndAddress (const ADC12_Regs *adc12) |
| Gets end address for ADC conversion. More... | |
| __STATIC_INLINE void | DL_ADC12_initSeqSample (ADC12_Regs *adc12, uint32_t repeatMode, uint32_t sampleMode, uint32_t trigSrc, uint32_t startAdd, uint32_t endAdd, uint32_t resolution, uint32_t dataFormat) |
| Initializes ADC12 for sequence sampling mode operation. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getResolution (const ADC12_Regs *adc12) |
| Returns ADC12 resolution. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getDataFormat (const ADC12_Regs *adc12) |
| Returns ADC12 data format. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getSamplingSource (const ADC12_Regs *adc12) |
| Returns ADC12 sampling source. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getSampleMode (const ADC12_Regs *adc12) |
| Returns ADC12 sampling mode. More... | |
| __STATIC_INLINE DL_ADC12_TRIG_SRC | DL_ADC12_getTriggerSource (const ADC12_Regs *adc12) |
| Returns ADC12 trigger mode. More... | |
| __STATIC_INLINE void | DL_ADC12_startConversion (ADC12_Regs *adc12) |
| Start ADC12 conversion. More... | |
| __STATIC_INLINE void | DL_ADC12_stopConversion (ADC12_Regs *adc12) |
| Stop ADC12 conversion. More... | |
| __STATIC_INLINE bool | DL_ADC12_isConversionStarted (const ADC12_Regs *adc12) |
| Check if ADC12 conversion is started. More... | |
| __STATIC_INLINE void | DL_ADC12_enableDMA (ADC12_Regs *adc12) |
| Enables DMA for data transfer. More... | |
| __STATIC_INLINE void | DL_ADC12_disableDMA (ADC12_Regs *adc12) |
| Disables DMA for data transfer. More... | |
| __STATIC_INLINE bool | DL_ADC12_isDMAEnabled (const ADC12_Regs *adc12) |
| Check if DMA is enabled. More... | |
| __STATIC_INLINE void | DL_ADC12_setDMASamplesCnt (ADC12_Regs *adc12, uint8_t sampCnt) |
| Set number of ADC results to be transfer on a DMA trigger. More... | |
| __STATIC_INLINE uint8_t | DL_ADC12_getDMASampleCnt (const ADC12_Regs *adc12) |
| Get number of ADC results to be transfer on a DMA trigger. More... | |
| __STATIC_INLINE void | DL_ADC12_enableFIFO (ADC12_Regs *adc12) |
| Enables FIFO mode. More... | |
| __STATIC_INLINE void | DL_ADC12_disableFIFO (ADC12_Regs *adc12) |
| Disables FIFO mode. More... | |
| __STATIC_INLINE bool | DL_ADC12_isFIFOEnabled (const ADC12_Regs *adc12) |
| Checks if FIFO mode is enabled. More... | |
| void | DL_ADC12_setClockConfig (ADC12_Regs *adc12, const DL_ADC12_ClockConfig *config) |
| Configures ADC12 sample clock divider and sample clock frequency range. More... | |
| void | DL_ADC12_getClockConfig (const ADC12_Regs *adc12, DL_ADC12_ClockConfig *config) |
| Returns ADC12 sample clock configuration. More... | |
| __STATIC_INLINE void | DL_ADC12_setPowerDownMode (ADC12_Regs *adc12, uint32_t powerDownMode) |
| Configures ADC12 power down mode. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getPowerDownMode (const ADC12_Regs *adc12) |
| Returns ADC power down mode. More... | |
| __STATIC_INLINE void | DL_ADC12_enableConversions (ADC12_Regs *adc12) |
| Enable ADC12 conversion. More... | |
| __STATIC_INLINE void | DL_ADC12_disableConversions (ADC12_Regs *adc12) |
| Disable ADC12 conversion. More... | |
| __STATIC_INLINE bool | DL_ADC12_isConversionsEnabled (const ADC12_Regs *adc12) |
| Check if ADC12 conversion is enabled. More... | |
| __STATIC_INLINE void | DL_ADC12_configHwAverage (ADC12_Regs *adc12, uint32_t numerator, uint32_t denominator) |
| Configure ADC12 hardware average. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getHwAverageConfig (const ADC12_Regs *adc12) |
| Return the hardware average configuration. More... | |
| __STATIC_INLINE void | DL_ADC12_setSampleTime0 (ADC12_Regs *adc12, uint16_t adcclks) |
| Set sample time 0. More... | |
| __STATIC_INLINE uint16_t | DL_ADC12_getSampleTime0 (const ADC12_Regs *adc12) |
| Get sample time 0. More... | |
| __STATIC_INLINE void | DL_ADC12_setSampleTime1 (ADC12_Regs *adc12, uint16_t adcclks) |
| Set sample time 1. More... | |
| __STATIC_INLINE uint16_t | DL_ADC12_getSampleTime1 (const ADC12_Regs *adc12) |
| Get sample time 1. More... | |
| __STATIC_INLINE void | DL_ADC12_configWinCompLowThld (ADC12_Regs *adc12, uint16_t threshold) |
| Configures window comparator low threshold. More... | |
| __STATIC_INLINE void | DL_ADC12_configWinCompHighThld (ADC12_Regs *adc12, uint16_t threshold) |
| Configures window comparator high threshold. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getFIFOData (const ADC12_Regs *adc12) |
| Returns the data from the top of FIFO. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getFIFOAddress (const ADC12_Regs *adc12) |
| Returns the address of FIFO data register. More... | |
| __STATIC_INLINE void | DL_ADC12_configConversionMem (ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx, uint32_t chansel, uint32_t vref, uint32_t stime, uint32_t avgen, uint32_t bcsen, uint32_t trig, uint32_t wincomp) |
| Configures conversion memory. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getConversionMemConfig (const ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx) |
| Returns conversion memory configuration. More... | |
| __STATIC_INLINE uint16_t | DL_ADC12_getMemResult (const ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx) |
| Returns the conversion result for the selected memory index. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getMemResultAddress (const ADC12_Regs *adc12, DL_ADC12_MEM_IDX idx) |
| Returns the conversion result memory address. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getStatus (const ADC12_Regs *adc12) |
| Returns ADC12 status. More... | |
| __STATIC_INLINE void | DL_ADC12_disableForcingSYSOSCOnInRunMode (ADC12_Regs *adc12) |
| Allows SYSOSC to not run at base frequency when device is in RUN mode. More... | |
| __STATIC_INLINE void | DL_ADC12_forceSYSOSCOnInRunMode (ADC12_Regs *adc12) |
| Forces SYSOSC to run at base frequency when device is in RUN mode. More... | |
| __STATIC_INLINE void | DL_ADC12_disableForcingSYSOSCOnInStopMode (ADC12_Regs *adc12) |
| Allows SYSOSC to not run at base frequency when device is in STOP mode. More... | |
| __STATIC_INLINE void | DL_ADC12_forceSYSOSCOnInStopMode (ADC12_Regs *adc12) |
| Forces SYSOSC to run at base frequency when device is in STOP mode. More... | |
| __STATIC_INLINE void | DL_ADC12_enableInterrupt (ADC12_Regs *adc12, uint32_t interruptMask) |
| Enable ADC12 interrupt. More... | |
| __STATIC_INLINE void | DL_ADC12_disableInterrupt (ADC12_Regs *adc12, uint32_t interruptMask) |
| Disable ADC12 interrupt. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEnabledInterrupts (const ADC12_Regs *adc12, uint32_t interruptMask) |
| Check which ADC12 interrupts are enabled. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEnabledInterruptStatus (const ADC12_Regs *adc12, uint32_t interruptMask) |
| Check interrupt flag of enabled ADC12 interrupt. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getRawInterruptStatus (const ADC12_Regs *adc12, uint32_t interruptMask) |
| Check interrupt flag of any ADC12 interrupt. More... | |
| __STATIC_INLINE DL_ADC12_IIDX | DL_ADC12_getPendingInterrupt (const ADC12_Regs *adc12) |
| Get highest priority pending ADC12 interrupt. More... | |
| __STATIC_INLINE void | DL_ADC12_clearInterruptStatus (ADC12_Regs *adc12, uint32_t interruptMask) |
| Clear pending ADC12 interrupt. More... | |
| __STATIC_INLINE void | DL_ADC12_setPublisherChanID (ADC12_Regs *adc12, uint8_t chanID) |
| Sets the event publisher channel id. More... | |
| __STATIC_INLINE uint8_t | DL_ADC12_getPublisherChanID (const ADC12_Regs *adc12) |
| Gets the event publisher channel id. More... | |
| __STATIC_INLINE void | DL_ADC12_setSubscriberChanID (ADC12_Regs *adc12, uint8_t chanID) |
| Sets the event subscriber channel id. More... | |
| __STATIC_INLINE uint8_t | DL_ADC12_getSubscriberChanID (const ADC12_Regs *adc12) |
| Gets the event subscriber channel id. More... | |
| __STATIC_INLINE void | DL_ADC12_enableEvent (ADC12_Regs *adc12, uint32_t eventMask) |
| Enable ADC12 event. More... | |
| __STATIC_INLINE void | DL_ADC12_disableEvent (ADC12_Regs *adc12, uint32_t eventMask) |
| Disable ADC12 event. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEnabledEvents (const ADC12_Regs *adc12, uint32_t eventMask) |
| Check which adc12 dma triggers are enabled. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEnabledEventStatus (const ADC12_Regs *adc12, uint32_t eventMask) |
| Check event flag of enabled adc12 event. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getRawEventsStatus (const ADC12_Regs *adc12, uint32_t eventMask) |
| Check event flag of any adc12 event. More... | |
| __STATIC_INLINE void | DL_ADC12_clearEventsStatus (ADC12_Regs *adc12, uint32_t eventMask) |
| Clear pending adc12 events. More... | |
| __STATIC_INLINE void | DL_ADC12_enableDMATrigger (ADC12_Regs *adc12, uint32_t dmaMask) |
| Enable ADC12 DMA triggers. More... | |
| __STATIC_INLINE void | DL_ADC12_disableDMATrigger (ADC12_Regs *adc12, uint32_t dmaMask) |
| Disable ADC12 DMA triggers. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEnabledDMATrigger (const ADC12_Regs *adc12, uint32_t dmaMask) |
| Check which adc12 DMA triggers are enabled. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getEnabledDMATriggerStatus (const ADC12_Regs *adc12, uint32_t dmaMask) |
| Check event flag of enabled adc12 DMA triggers. More... | |
| __STATIC_INLINE uint32_t | DL_ADC12_getRawDMATriggerStatus (const ADC12_Regs *adc12, uint32_t dmaMask) |
| Check DMA triggers flag of any adc12 dma trigger. More... | |
| __STATIC_INLINE void | DL_ADC12_clearDMATriggerStatus (ADC12_Regs *adc12, uint32_t dmaMask) |
| Clear pending adc12 DMA triggers. More... | |