MSPM0G1X0X_G3X0X TI-Driver Library
2.00.00.03
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SPIMSPM0 Hardware attributes. More...
#include <SPIMSPM0.h>
Data Fields | |
SPI_Regs * | spi |
uint8_t | intNum |
uint8_t | intPriority |
SPIMSPM0 Peripheral's interrupt priority. More... | |
uint16_t | defaultTxBufValue |
DL_SPI_CLOCK | clockSource |
DL_SPI_CLOCK_DIVIDE_RATIO | clockDivider |
uint32_t | pociPinMux |
uint32_t | picoPinMux |
uint32_t | sclkPinMux |
uint32_t | csnPinMux |
uint_least8_t | pociPincm |
uint_least8_t | pociPin |
uint_least8_t | picoPincm |
uint_least8_t | picoPin |
uint_least8_t | sclkPincm |
uint_least8_t | sclkPin |
uint_least8_t | csnPincm |
uint_least8_t | csnPin |
DL_SPI_TX_FIFO_LEVEL | txFifoThreshold |
DL_SPI_RX_FIFO_LEVEL | rxFifoThreshold |
SPI_Chip_Select | cssel |
uint8_t | noOfDMAChannels |
SPIMSPM0 Hardware attributes.
These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For driverlib these definitions are found in:
intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().
A sample structure is shown below:
SPI_Regs* SPIMSPM0_HWAttrs::spi |
SPI Peripheral's instance
uint8_t SPIMSPM0_HWAttrs::intNum |
SPIMSPM0 Peripheral's interrupt vector
uint8_t SPIMSPM0_HWAttrs::intPriority |
SPIMSPM0 Peripheral's interrupt priority.
Note for MSPM0: The Arm Cortex-M0+ uses two of the priority bits, meaning ~0 has the same effect as (3 << 6). (3 << 6) will apply the lowest priority. (1 << 6) will apply the highest priority.
Setting the priority to 0 is not supported by this driver.
HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.
uint16_t SPIMSPM0_HWAttrs::defaultTxBufValue |
Default TX value if txBuf == NULL
DL_SPI_CLOCK SPIMSPM0_HWAttrs::clockSource |
SPI clock source
DL_SPI_CLOCK_DIVIDE_RATIO SPIMSPM0_HWAttrs::clockDivider |
SPI clock divider
uint32_t SPIMSPM0_HWAttrs::pociPinMux |
POCI PIN mux function value. Can be applied to either PICO or POCI
uint32_t SPIMSPM0_HWAttrs::picoPinMux |
PICO PIN mux function value. Can be applied to either PICO or POCI
uint32_t SPIMSPM0_HWAttrs::sclkPinMux |
SCLK PIN mux function value for flow control
uint32_t SPIMSPM0_HWAttrs::csnPinMux |
CSN PIN mux function value for flow control
uint_least8_t SPIMSPM0_HWAttrs::pociPincm |
POCI Pincm value
uint_least8_t SPIMSPM0_HWAttrs::pociPin |
SPI POCI pin index
uint_least8_t SPIMSPM0_HWAttrs::picoPincm |
PICO Pincm value
uint_least8_t SPIMSPM0_HWAttrs::picoPin |
SPI PICO pin index
uint_least8_t SPIMSPM0_HWAttrs::sclkPincm |
SCLK Pincm value
uint_least8_t SPIMSPM0_HWAttrs::sclkPin |
SPI SCLK pin index
uint_least8_t SPIMSPM0_HWAttrs::csnPincm |
CSN Pincm value
uint_least8_t SPIMSPM0_HWAttrs::csnPin |
SPI CSn pin index
DL_SPI_TX_FIFO_LEVEL SPIMSPM0_HWAttrs::txFifoThreshold |
Tx FIFO threshold
DL_SPI_RX_FIFO_LEVEL SPIMSPM0_HWAttrs::rxFifoThreshold |
Rx FIFO threshold
SPI_Chip_Select SPIMSPM0_HWAttrs::cssel |
Select the CS line to control on data transfer
uint8_t SPIMSPM0_HWAttrs::noOfDMAChannels |
Total DMA channels used