SPIMSPM0 Hardware attributes. More...

#include <SPIMSPM0.h>

Data Fields
SPI_Regs *	spi

uint8_t	intNum

uint8_t	intPriority
	SPIMSPM0 Peripheral's interrupt priority. More...

uint16_t	defaultTxBufValue

DL_SPI_CLOCK	clockSource

DL_SPI_CLOCK_DIVIDE_RATIO	clockDivider

uint32_t	pociPinMux

uint32_t	picoPinMux

uint32_t	sclkPinMux

uint32_t	csnPinMux

uint_least8_t	pociPincm

uint_least8_t	pociPin

uint_least8_t	picoPincm

uint_least8_t	picoPin

uint_least8_t	sclkPincm

uint_least8_t	sclkPin

uint_least8_t	csnPincm

uint_least8_t	csnPin

DL_SPI_TX_FIFO_LEVEL	txFifoThreshold

DL_SPI_RX_FIFO_LEVEL	rxFifoThreshold

SPI_Chip_Select	cssel

uint8_t	noOfDMAChannels

Detailed Description

SPIMSPM0 Hardware attributes.

These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For driverlib these definitions are found in:

ti/devices/DeviceFamily.h>
ti/driverlib/dl_spi.h
ti/drivers/dpl/HwiP.h

intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

A sample structure is shown below:

const SPIMSPM0_HWAttrs SPIMSPM0objects[] =
{
   {
      .spi = SPI_1_INST,
      .intNum = SPI_1_INST_INT_IRQN,
      .intPriority = (~0),
      .clockSource = DL_SPI_CLOCK_BUSCLK,
      .clockDivider = DL_SPI_CLOCK_DIVIDE_RATIO_1,
      .defaultTxBufValue = 0xFF,
      .pociPin = GPIO_SPI_1_POCI_PIN,
      .pociPincm = GPIO_SPI_1_IOMUX_POCI,
      .pociPinMux = GPIO_SPI_1_IOMUX_POCI_FUNC,
      .picoPin = GPIO_SPI_1_PICO_PIN,
      .picoPincm = GPIO_SPI_1_IOMUX_PICO,
      .picoPinMux = GPIO_SPI_1_IOMUX_PICO_FUNC,
      .sclkPin = GPIO_SPI_1_SCLK_PIN,
      .sclkPincm = GPIO_SPI_1_IOMUX_SCLK,
      .sclkPinMux = GPIO_SPI_1_IOMUX_SCLK_FUNC,
      .csnPin = GPIO_SPI_1_CS0_PIN,
      .csnPincm = GPIO_SPI_1_IOMUX_CS0,
      .csnPinMux = GPIO_SPI_1_IOMUX_CS0_FUNC,
      .txFifoThreshold = DL_SPI_TX_FIFO_LEVEL_ONE_FRAME,
      .rxFifoThreshold = DL_SPI_RX_FIFO_LEVEL_ONE_FRAME,
      .cssel = 0,
      .noOfDMAChannels = 2,
   },
};

Field Documentation

§ spi

SPI_Regs* SPIMSPM0_HWAttrs::spi

SPI Peripheral's instance

§ intNum

uint8_t SPIMSPM0_HWAttrs::intNum

SPIMSPM0 Peripheral's interrupt vector

§ intPriority

uint8_t SPIMSPM0_HWAttrs::intPriority

SPIMSPM0 Peripheral's interrupt priority.

Note for MSPM0: The Arm Cortex-M0+ uses two of the priority bits, meaning ~0 has the same effect as (3 << 6). (3 << 6) will apply the lowest priority. (1 << 6) will apply the highest priority.

Setting the priority to 0 is not supported by this driver.

HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

§ defaultTxBufValue

uint16_t SPIMSPM0_HWAttrs::defaultTxBufValue

Default TX value if txBuf == NULL

§ clockSource

DL_SPI_CLOCK SPIMSPM0_HWAttrs::clockSource

SPI clock source

§ clockDivider

DL_SPI_CLOCK_DIVIDE_RATIO SPIMSPM0_HWAttrs::clockDivider

SPI clock divider

§ pociPinMux

uint32_t SPIMSPM0_HWAttrs::pociPinMux

POCI PIN mux function value. Can be applied to either PICO or POCI

§ picoPinMux

uint32_t SPIMSPM0_HWAttrs::picoPinMux

PICO PIN mux function value. Can be applied to either PICO or POCI

§ sclkPinMux

uint32_t SPIMSPM0_HWAttrs::sclkPinMux

SCLK PIN mux function value for flow control

§ csnPinMux

uint32_t SPIMSPM0_HWAttrs::csnPinMux

CSN PIN mux function value for flow control

§ pociPincm

uint_least8_t SPIMSPM0_HWAttrs::pociPincm

POCI Pincm value

§ pociPin

uint_least8_t SPIMSPM0_HWAttrs::pociPin

SPI POCI pin index

§ picoPincm

uint_least8_t SPIMSPM0_HWAttrs::picoPincm

PICO Pincm value

§ picoPin

uint_least8_t SPIMSPM0_HWAttrs::picoPin

SPI PICO pin index

§ sclkPincm

uint_least8_t SPIMSPM0_HWAttrs::sclkPincm

SCLK Pincm value

§ sclkPin

uint_least8_t SPIMSPM0_HWAttrs::sclkPin

SPI SCLK pin index

§ csnPincm

uint_least8_t SPIMSPM0_HWAttrs::csnPincm

CSN Pincm value

§ csnPin

uint_least8_t SPIMSPM0_HWAttrs::csnPin

SPI CSn pin index

§ txFifoThreshold

DL_SPI_TX_FIFO_LEVEL SPIMSPM0_HWAttrs::txFifoThreshold

Tx FIFO threshold

§ rxFifoThreshold

DL_SPI_RX_FIFO_LEVEL SPIMSPM0_HWAttrs::rxFifoThreshold

Rx FIFO threshold

§ cssel

SPI_Chip_Select SPIMSPM0_HWAttrs::cssel

Select the CS line to control on data transfer

§ noOfDMAChannels

uint8_t SPIMSPM0_HWAttrs::noOfDMAChannels

Total DMA channels used

The documentation for this struct was generated from the following file:

SPIMSPM0.h

Data Fields