Collaboration diagram for ADC driver APIs:

Data Structures
struct	ADCMSPM0_HWAttrs
	ADCMSPM0 Hardware attributes These fields are used by driverlib APIs and therefore must be populated by driverlib macro definitions. Currently the Single channel single conversion and the Repeat single channel conversion are supported. For the other conversion modes, user has to modify or add the needed parameters to below structure. More...

struct	ADCMSPM0_Object
	ADCMSPM0 Object. More...

Macros
#define	ADC_ALL_INTERRUPTS_MASK 0xFFFFFFFFUL

Enumerations
enum	ADCMSPM0_Resolution_Bits { ADCMSPM0_RESOLUTION_12_BIT = DL_ADC12_SAMP_CONV_RES_12_BIT, ADCMSPM0_RESOLUTION_10_BIT = DL_ADC12_SAMP_CONV_RES_10_BIT, ADCMSPM0_RESOLUTION_8_BIT = DL_ADC12_SAMP_CONV_RES_8_BIT }
	Resolution of ADC-conversion. More...

enum	ADCMSPM0_Reference_Source { ADCMSPM0_VDDA_REFERENCE = DL_ADC12_REFERENCE_VOLTAGE_VDDA, ADCMSPM0_INTERNAL_REFERENCE = DL_ADC12_REFERENCE_VOLTAGE_INTREF, ADCMSPM0_EXTERNAL_REFERENCE = DL_ADC12_REFERENCE_VOLTAGE_EXTREF }
	Specifies the source of the ADC reference voltage. More...

enum	ADCMSPM0_Clock_Divider { ADCMSPM0_CLKDIV_1 = DL_ADC12_CLOCK_DIVIDE_1, ADCMSPM0_CLKDIV_2 = DL_ADC12_CLOCK_DIVIDE_2, ADCMSPM0_CLKDIV_4 = DL_ADC12_CLOCK_DIVIDE_4, ADCMSPM0_CLKDIV_8 = DL_ADC12_CLOCK_DIVIDE_8, ADCMSPM0_CLKDIV_16 = DL_ADC12_CLOCK_DIVIDE_16, ADCMSPM0_CLKDIV_24 = DL_ADC12_CLOCK_DIVIDE_24, ADCMSPM0_CLKDIV_32 = DL_ADC12_CLOCK_DIVIDE_32, ADCMSPM0_CLKDIV_48 = DL_ADC12_CLOCK_DIVIDE_48 }
	ADC clock-divider. More...

enum	ADCMSPM0_Clock_Select { ADCMSPM0_CLK_SYSOSC = DL_ADC12_CLOCK_SYSOSC, ADCMSPM0_CLK_ULPCLK = DL_ADC12_CLOCK_ULPCLK, ADCMSPM0_CLK_HFCLK = DL_ADC12_CLOCK_HFCLK }
	ADC clock source select. More...

enum	ADCMSPM0_Freq_Range { ADCMSPM0_CLK_FREQ_RANGE_1TO4 = DL_ADC12_CLOCK_FREQ_RANGE_1_TO_4, ADCMSPM0_CLK_FREQ_RANGE_4TO8 = DL_ADC12_CLOCK_FREQ_RANGE_4_TO_8, ADCMSPM0_CLK_FREQ_RANGE_8TO16 = DL_ADC12_CLOCK_FREQ_RANGE_8_TO_16, ADCMSPM0_CLK_FREQ_RANGE_16TO20 = DL_ADC12_CLOCK_FREQ_RANGE_16_TO_20, ADCMSPM0_CLK_FREQ_RANGE_20TO24 = DL_ADC12_CLOCK_FREQ_RANGE_20_TO_24, ADCMSPM0_CLK_FREQ_RANGE_24TO32 = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32, ADCMSPM0_CLK_FREQ_RANGE_32TO40 = DL_ADC12_CLOCK_FREQ_RANGE_32_TO_40, ADCMSPM0_CLK_FREQ_RANGE_40TO48 = DL_ADC12_CLOCK_FREQ_RANGE_40_TO_48 }
	ADC clock freq range. More...

enum	ADCMSPM0_Conversion_Mode { ADCMSPM0_SINGLE_CH_SINGLE_CONV = DL_ADC12_SAMP_MODE_SINGLE, ADCMSPM0_MULTI_CH_SEQUENCE_CONV = DL_ADC12_SAMP_MODE_SEQUENCE }
	ADC conversion mode. More...

enum	ADCMSPM0_Repeat_Conversion_Mode { ADCMSPM0_REPEAT_MODE_ENABLED = DL_ADC12_REPEAT_MODE_ENABLED, ADCMSPM0_REPEAT_MODE_DISABLED = DL_ADC12_REPEAT_MODE_DISABLED }
	ADC Repeat conversion mode. More...

enum	ADCMSPM0_Sampling_Mode { ADCMSPM0_SAMPLING_MODE_AUTO = DL_ADC12_SAMPLING_SOURCE_AUTO, ADCMSPM0_SAMPLING_MODE_MANUAL = DL_ADC12_SAMPLING_SOURCE_MANUAL }
	ADC sampling mode. More...

enum	ADCMSPM0_Sampling_Trg { ADCMSPM0_SAMPLING_TRIG_SW = DL_ADC12_TRIG_SRC_SOFTWARE, ADCMSPM0_SAMPLING_TRIG_EVENT = DL_ADC12_TRIG_SRC_EVENT }
	ADC sampling trigger source. More...

enum	ADCMSPM0_Conv_Data_Format { ADCMSPM0_CONV_DATA_FORMAT_UNSIGNED = DL_ADC12_SAMP_CONV_DATA_FORMAT_UNSIGNED, ADCMSPM0_CONV_DATA_FORMAT_SIGNED = DL_ADC12_SAMP_CONV_DATA_FORMAT_SIGNED }
	ADC conversion data format. More...

enum	ADCMSPM0_Sample_Timer_Source { ADCMSPM0_SAMP_TMR_SOURCE_SCOMP0 = DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP0, ADCMSPM0_SAMP_TMR_SOURCE_SCOMP1 = DL_ADC12_SAMPLE_TIMER_SOURCE_SCOMP1 }
	ADC sample timer source. More...

enum	ADCMSPM0_Conv_Trig_Src { ADCMSPM0_NEXT_CONV_AUTO = DL_ADC12_TRIGGER_MODE_AUTO_NEXT, ADCMSPM0_NEXT_CONV_WITH_TRIG = DL_ADC12_TRIGGER_MODE_TRIGGER_NEXT }
	ADC conversion trigger. More...

enum	ADCMSPM0_HW_Avg { ADCMSPM0_HW_AVG_ENABLED = DL_ADC12_AVERAGING_MODE_ENABLED, ADCMSPM0_HW_AVG_DISABLED = DL_ADC12_AVERAGING_MODE_DISABLED }
	ADC HW averaging. More...

enum	ADCMSPM0_AVGN { ADCMSPM0_HW_AVG_NUM_ACC_DISABLED = DL_ADC12_HW_AVG_NUM_ACC_DISABLED, ADCMSPM0_HW_AVG_NUM_ACC_2 = DL_ADC12_HW_AVG_NUM_ACC_2, ADCMSPM0_HW_AVG_NUM_ACC_4 = DL_ADC12_HW_AVG_NUM_ACC_4, ADCMSPM0_HW_AVG_NUM_ACC_8 = DL_ADC12_HW_AVG_NUM_ACC_8, ADCMSPM0_HW_AVG_NUM_ACC_16 = DL_ADC12_HW_AVG_NUM_ACC_16, ADCMSPM0_HW_AVG_NUM_ACC_32 = DL_ADC12_HW_AVG_NUM_ACC_32, ADCMSPM0_HW_AVG_NUM_ACC_64 = DL_ADC12_HW_AVG_NUM_ACC_64, ADCMSPM0_HW_AVG_NUM_ACC_128 = DL_ADC12_HW_AVG_NUM_ACC_128 }
	Hardware averager numerator. More...

enum	ADCMSPM0_AVGD { ADCMSPM0_HW_AVG_DEN_DIV_BY_1 = DL_ADC12_HW_AVG_DEN_DIV_BY_1, ADCMSPM0_HW_AVG_DEN_DIV_BY_2 = DL_ADC12_HW_AVG_DEN_DIV_BY_2, ADCMSPM0_HW_AVG_DEN_DIV_BY_4 = DL_ADC12_HW_AVG_DEN_DIV_BY_4, ADCMSPM0_HW_AVG_DEN_DIV_BY_8 = DL_ADC12_HW_AVG_DEN_DIV_BY_8, ADCMSPM0_HW_AVG_DEN_DIV_BY_16 = DL_ADC12_HW_AVG_DEN_DIV_BY_16, ADCMSPM0_HW_AVG_DEN_DIV_BY_32 = DL_ADC12_HW_AVG_DEN_DIV_BY_32, ADCMSPM0_HW_AVG_DEN_DIV_BY_64 = DL_ADC12_HW_AVG_DEN_DIV_BY_64, ADCMSPM0_HW_AVG_DEN_DIV_BY_128 = DL_ADC12_HW_AVG_DEN_DIV_BY_128 }
	Hardware averager denominator. More...

enum	ADCMSPM0_Pwr_Dn_Mode { ADCMSPM0_Pwr_Dn_MODE_AUTO = DL_ADC12_POWER_DOWN_MODE_AUTO, ADCMSPM0_Pwr_Dn_MODE_MANUAL = DL_ADC12_POWER_DOWN_MODE_MANUAL }
	ADC power down mode. More...

enum	ADCMSPM0_CONV_START_ADDRESS { ADCMSPM0_SEQ_START_ADDR_00 = DL_ADC12_SEQ_START_ADDR_00, ADCMSPM0_SEQ_START_ADDR_01 = DL_ADC12_SEQ_START_ADDR_01, ADCMSPM0_SEQ_START_ADDR_02 = DL_ADC12_SEQ_START_ADDR_02, ADCMSPM0_SEQ_START_ADDR_03 = DL_ADC12_SEQ_START_ADDR_03, ADCMSPM0_SEQ_START_ADDR_04 = DL_ADC12_SEQ_START_ADDR_04, ADCMSPM0_SEQ_START_ADDR_05 = DL_ADC12_SEQ_START_ADDR_05, ADCMSPM0_SEQ_START_ADDR_06 = DL_ADC12_SEQ_START_ADDR_06, ADCMSPM0_SEQ_START_ADDR_07 = DL_ADC12_SEQ_START_ADDR_07, ADCMSPM0_SEQ_START_ADDR_08 = DL_ADC12_SEQ_START_ADDR_08, ADCMSPM0_SEQ_START_ADDR_09 = DL_ADC12_SEQ_START_ADDR_09, ADCMSPM0_SEQ_START_ADDR_10 = DL_ADC12_SEQ_START_ADDR_10, ADCMSPM0_SEQ_START_ADDR_11 = DL_ADC12_SEQ_START_ADDR_11 }
	Sequence start address. More...

enum	ADCMSPM0_CONV_END_ADDRESS { ADCMSPM0_SEQ_END_ADDR_00 = DL_ADC12_SEQ_END_ADDR_00, ADCMSPM0_SEQ_END_ADDR_01 = DL_ADC12_SEQ_END_ADDR_01, ADCMSPM0_SEQ_END_ADDR_02 = DL_ADC12_SEQ_END_ADDR_02, ADCMSPM0_SEQ_END_ADDR_03 = DL_ADC12_SEQ_END_ADDR_03, ADCMSPM0_SEQ_END_ADDR_04 = DL_ADC12_SEQ_END_ADDR_04, ADCMSPM0_SEQ_END_ADDR_05 = DL_ADC12_SEQ_END_ADDR_05, ADCMSPM0_SEQ_END_ADDR_06 = DL_ADC12_SEQ_END_ADDR_06, ADCMSPM0_SEQ_END_ADDR_07 = DL_ADC12_SEQ_END_ADDR_07, ADCMSPM0_SEQ_END_ADDR_08 = DL_ADC12_SEQ_END_ADDR_08, ADCMSPM0_SEQ_END_ADDR_09 = DL_ADC12_SEQ_END_ADDR_09, ADCMSPM0_SEQ_END_ADDR_10 = DL_ADC12_SEQ_END_ADDR_10, ADCMSPM0_SEQ_END_ADDR_11 = DL_ADC12_SEQ_END_ADDR_11 }
	Sequence end address. More...

Detailed Description

This ADC driver implementation is designed to operate on a ADC peripheral for MSPM0 devices.

Refer to ADC.h for a complete description of APIs & example of use.

Macro Definition Documentation

§ ADC_ALL_INTERRUPTS_MASK

#define ADC_ALL_INTERRUPTS_MASK 0xFFFFFFFFUL

An interrupt mask for all ADC CPU interrupts

Enumeration Type Documentation

§ ADCMSPM0_Resolution_Bits

enum ADCMSPM0_Resolution_Bits

Resolution of ADC-conversion.

This sets the resolution of the ADC conversion, and will affect how long a conversion takes.

Enumerator
ADCMSPM0_RESOLUTION_12_BIT	ADC resolution 12bit
ADCMSPM0_RESOLUTION_10_BIT	ADC resolution 10bit
ADCMSPM0_RESOLUTION_8_BIT	ADC resolution 8bit

§ ADCMSPM0_Reference_Source

enum ADCMSPM0_Reference_Source

Specifies the source of the ADC reference voltage.

The ADC reference voltage will determine the upper limit of the input voltage.

Note: The actual reference values are slightly different for each device. The function ADCMSPM0_ADCValueToMicrovolts() must be used to derive actual voltage values. Do not attempt to compare raw values between devices or derive a voltage from them yourself. The results of doing so will only be approximately correct.

Warning: Refer to the datasheet to make sure the input voltage to the ADC never exceeds the specifies limits.

Enumerator
ADCMSPM0_VDDA_REFERENCE	ADC reference voltage VDDA
ADCMSPM0_INTERNAL_REFERENCE	ADC reference voltage internal
ADCMSPM0_EXTERNAL_REFERENCE	ADC reference voltage external

§ ADCMSPM0_Clock_Divider

enum ADCMSPM0_Clock_Divider

ADC clock-divider.

This sets the clock divider value for the ADC sample clock(SAMPCLK) which can be derived from the SYSOSC/ULPCLK/HFCLK.

Enumerator
ADCMSPM0_CLKDIV_1	Do not divide clock source
ADCMSPM0_CLKDIV_2	Divide clock source by 2
ADCMSPM0_CLKDIV_4	Divide clock source by 4
ADCMSPM0_CLKDIV_8	Divide clock source by 8
ADCMSPM0_CLKDIV_16	Divide clock source by 16
ADCMSPM0_CLKDIV_24	Divide clock source by 24
ADCMSPM0_CLKDIV_32	Divide clock source by 32
ADCMSPM0_CLKDIV_48	Divide clock source by 48

§ ADCMSPM0_Clock_Select

enum ADCMSPM0_Clock_Select

ADC clock source select.

This selects the clock source

Enumerator
ADCMSPM0_CLK_SYSOSC	SYSOSC is the source of ADC sample clock
ADCMSPM0_CLK_ULPCLK	ULPCLK is the source of ADC sample clock
ADCMSPM0_CLK_HFCLK	HFCLK is the source of ADC sample clock

§ ADCMSPM0_Freq_Range

enum ADCMSPM0_Freq_Range

ADC clock freq range.

This sets the clock freq range for the configured ADC clock

Enumerator
ADCMSPM0_CLK_FREQ_RANGE_1TO4	Specifies ADC clock (ADCCLK) frequency range is from 1 MHz to 4 MHz
ADCMSPM0_CLK_FREQ_RANGE_4TO8	Specifies ADC clock (ADCCLK) frequency range is from 4 MHz to 8 MHz
ADCMSPM0_CLK_FREQ_RANGE_8TO16	Specifies ADC clock (ADCCLK) frequency range is from 8 MHz to 16 MHz
ADCMSPM0_CLK_FREQ_RANGE_16TO20	Specifies ADC clock (ADCCLK) frequency range is from 16 MHz to 20 MHz
ADCMSPM0_CLK_FREQ_RANGE_20TO24	Specifies ADC clock (ADCCLK) frequency range is from 20 MHz to 24 MHz
ADCMSPM0_CLK_FREQ_RANGE_24TO32	Specifies ADC clock (ADCCLK) frequency range is from 24 MHz to 32 MHz
ADCMSPM0_CLK_FREQ_RANGE_32TO40	Specifies ADC clock (ADCCLK) frequency range is from 32 MHz to 40 MHz
ADCMSPM0_CLK_FREQ_RANGE_40TO48	Specifies ADC clock (ADCCLK) frequency range is from 40 MHz to 48 MHz

§ ADCMSPM0_Conversion_Mode

enum ADCMSPM0_Conversion_Mode

ADC conversion mode.

This sets the ADC conversion mode

Enumerator
ADCMSPM0_SINGLE_CH_SINGLE_CONV	Single channel conversion selected
ADCMSPM0_MULTI_CH_SEQUENCE_CONV	Multi channel conversion selected

§ ADCMSPM0_Repeat_Conversion_Mode

enum ADCMSPM0_Repeat_Conversion_Mode

ADC Repeat conversion mode.

This sets the ADC repeat conversion mode to enable or disable

Enumerator
ADCMSPM0_REPEAT_MODE_ENABLED	Enable the repetition of the selected conversion
ADCMSPM0_REPEAT_MODE_DISABLED	Disable the repetition of the selected conversion

§ ADCMSPM0_Sampling_Mode

enum ADCMSPM0_Sampling_Mode

ADC sampling mode.

This sets the ADC sampling mode

Enumerator
ADCMSPM0_SAMPLING_MODE_AUTO	Timer high phase is used as source of the sample signal Internal ADC sampling timer is used in this mode. It can be selected/configured from ADCMSPM0_Sample_Timer_Source.
ADCMSPM0_SAMPLING_MODE_MANUAL	External or software trigger is used as source of the sample signal

§ ADCMSPM0_Sampling_Trg

enum ADCMSPM0_Sampling_Trg

ADC sampling trigger source.

This sets the ADC sampling trigger source

Enumerator
ADCMSPM0_SAMPLING_TRIG_SW	Conversion is triggered by software.
ADCMSPM0_SAMPLING_TRIG_EVENT	Conversion is triggered by hardware

§ ADCMSPM0_Conv_Data_Format

enum ADCMSPM0_Conv_Data_Format

ADC conversion data format.

This sets the ADC conversion data format

Enumerator
ADCMSPM0_CONV_DATA_FORMAT_UNSIGNED	Results are read as binary unsigned, right aligned.
ADCMSPM0_CONV_DATA_FORMAT_SIGNED	Result are read as signed binary (2s complement), left aligned.

§ ADCMSPM0_Sample_Timer_Source

enum ADCMSPM0_Sample_Timer_Source

ADC sample timer source.

Selects the source of sample timer period between SCOMP0 and SCOMP1. This selection is valid when ADCMSPM0_SAMPLING_MODE_AUTO is selected as a sampling mode from ADCMSPM0_Sampling_Mode .

Enumerator
ADCMSPM0_SAMP_TMR_SOURCE_SCOMP0	sample adc sample timer source 0
ADCMSPM0_SAMP_TMR_SOURCE_SCOMP1	sample adc sample timer source 1

§ ADCMSPM0_Conv_Trig_Src

enum ADCMSPM0_Conv_Trig_Src

ADC conversion trigger.

Selects the source of the trigger to start next conversion

Enumerator
ADCMSPM0_NEXT_CONV_AUTO	ADC triggers automaticaly to the next memory conversion register
ADCMSPM0_NEXT_CONV_WITH_TRIG	A valid trigger will step to the next memory conversion register

§ ADCMSPM0_HW_Avg

enum ADCMSPM0_HW_Avg

ADC HW averaging.

Hardware Averaging enabled/disabled

Enumerator
ADCMSPM0_HW_AVG_ENABLED	HW averaging mode enabled
ADCMSPM0_HW_AVG_DISABLED	HW averaging mode disabled

§ ADCMSPM0_AVGN

enum ADCMSPM0_AVGN

Hardware averager numerator.

Selects number of conversions to accumulate for current MEMCTLx and then it is divided by AVGD

§ ADCMSPM0_AVGD

enum ADCMSPM0_AVGD

Hardware averager denominator.

The number to divide the accumulated value by (this is a shift).

§ ADCMSPM0_Pwr_Dn_Mode

enum ADCMSPM0_Pwr_Dn_Mode

ADC power down mode.

Selects the power down mode

Enumerator
ADCMSPM0_Pwr_Dn_MODE_AUTO	Power down mode auto
ADCMSPM0_Pwr_Dn_MODE_MANUAL	Power down mode manual

§ ADCMSPM0_CONV_START_ADDRESS

enum ADCMSPM0_CONV_START_ADDRESS

Sequence start address.

These bits select which MEMCTLx is used for single conversion or as first MEMCTL for sequence mode

§ ADCMSPM0_CONV_END_ADDRESS

enum ADCMSPM0_CONV_END_ADDRESS

Sequence end address.

These bits select which MEMCTLx is the last one for the sequence mode.

Data Structures

Macros

Enumerations