DL_I2C_CONTROLLER_STATUS

Collaboration diagram for DL_I2C_CONTROLLER_STATUS:

Macros
#define	DL_I2C_CONTROLLER_STATUS_BUSY   (I2C_MSR_BUSY_MASK)
	I2C is busy. More...
#define	DL_I2C_CONTROLLER_STATUS_ERROR   (I2C_MSR_ERR_MASK)
	I2C error detected. More...
#define	DL_I2C_CONTROLLER_STATUS_ADDR_ACK   (I2C_MSR_ADRACK_MASK)
	I2C address acknowledged.
#define	DL_I2C_CONTROLLER_STATUS_DATA_ACK   (I2C_MSR_DATACK_MASK)
	I2C data acknowledged.
#define	DL_I2C_CONTROLLER_STATUS_ARBITRATION_LOST   (I2C_MSR_ARBLST_MASK)
	I2C arbitration lost.
#define	DL_I2C_CONTROLLER_STATUS_IDLE   (I2C_MSR_IDLE_MASK)
	I2C idle.
#define	DL_I2C_CONTROLLER_STATUS_BUSY_BUS   (I2C_MSR_BUSBSY_MASK)
	I2C bus busy. More...

Detailed Description

Macro Definition Documentation

DL_I2C_CONTROLLER_STATUS_BUSY

#define DL_I2C_CONTROLLER_STATUS_BUSY   (I2C_MSR_BUSY_MASK)

I2C is busy.

The BUSY bit is set during an ongoing transaction, so is set during the transmit/receive of the amount of data set in WBLEN including START, RESTART, Address and STOP signal generation when required for the current transaction

DL_I2C_CONTROLLER_STATUS_ERROR

#define DL_I2C_CONTROLLER_STATUS_ERROR   (I2C_MSR_ERR_MASK)

I2C error detected.

The error can be from the target address not being acknowledged or the transmit data not being acknowledged

DL_I2C_CONTROLLER_STATUS_BUSY_BUS

#define DL_I2C_CONTROLLER_STATUS_BUSY_BUS   (I2C_MSR_BUSBSY_MASK)

I2C bus busy.

The bit changes based on the START and STOP conditions