DL_I2C_INTERRUPT

Collaboration diagram for DL_I2C_INTERRUPT:

Macros
#define	DL_I2C_INTERRUPT_CONTROLLER_RX_DONE   (I2C_INT_EVENT0_IMASK_MRXDONE_SET)
	Controller Receive Transaction completed Interrupt.
#define	DL_I2C_INTERRUPT_CONTROLLER_TX_DONE   (I2C_INT_EVENT0_IMASK_MTXDONE_SET)
	Controller Transmit Transaction completed Interrupt.
#define	DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_TRIGGER   (I2C_INT_EVENT0_IMASK_MRXFIFOTRG_SET)
	Controller Receive FIFO Trigger when >= defined bytes.
#define	DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_TRIGGER   (I2C_INT_EVENT0_IMASK_MTXFIFOTRG_SET)
	Controller Transmit FIFO Trigger when <= defined bytes.
#define	DL_I2C_INTERRUPT_CONTROLLER_RXFIFO_FULL   (I2C_INT_EVENT0_IMASK_MRXFIFOFULL_SET)
	Controller Receive FIFO is full.
#define	DL_I2C_INTERRUPT_CONTROLLER_TXFIFO_EMPTY   (I2C_INT_EVENT0_IMASK_MTXEMPTY_SET)
	Controller Transmit FIFO is empty.
#define	DL_I2C_INTERRUPT_CONTROLLER_NACK   (I2C_INT_EVENT0_IMASK_MNACK_SET)
	Address/Data NACK Interrupt.
#define	DL_I2C_INTERRUPT_CONTROLLER_START   (I2C_INT_EVENT0_IMASK_MSTART_SET)
	START Detection Interrupt.
#define	DL_I2C_INTERRUPT_CONTROLLER_STOP   (I2C_INT_EVENT0_IMASK_MSTOP_SET)
	STOP Detection Interrupt.
#define	DL_I2C_INTERRUPT_CONTROLLER_ARBITRATION_LOST   (I2C_INT_EVENT0_IMASK_MARBLOST_SET)
	Arbitration Lost Interrupt.
#define	DL_I2C_INTERRUPT_CONTROLLER_EVENT1_DMA_DONE   (I2C_INT_EVENT0_IMASK_MDMA_DONE_TX_SET)
	Controller DMA Done on Event 1 publisher.
#define	DL_I2C_INTERRUPT_CONTROLLER_EVENT2_DMA_DONE   (I2C_INT_EVENT0_IMASK_MDMA_DONE_RX_SET)
	Controller DMA Done on Event 2 publisher.
#define	DL_I2C_INTERRUPT_CONTROLLER_PEC_RX_ERROR   (I2C_INT_EVENT0_IMASK_MPEC_RX_ERR_SET)
	Controller SMBus/PMBus PEC Receive Error Interrupt.
#define	DL_I2C_INTERRUPT_TARGET_RX_DONE   (I2C_INT_EVENT0_IMASK_SRXDONE_SET)
	Target Receive Data Interrupt (byte has been received)
#define	DL_I2C_INTERRUPT_TARGET_TX_DONE   (I2C_INT_EVENT0_IMASK_STXDONE_SET)
	Target Transmit Transaction completed Interrupt.
#define	DL_I2C_INTERRUPT_TARGET_RXFIFO_TRIGGER   (I2C_INT_EVENT0_IMASK_SRXFIFOTRG_SET)
	Target Receive FIFO Trigger.
#define	DL_I2C_INTERRUPT_TARGET_TXFIFO_TRIGGER   (I2C_INT_EVENT0_IMASK_STXFIFOTRG_SET)
	Target Transmit FIFO Trigger.
#define	DL_I2C_INTERRUPT_TARGET_RXFIFO_FULL   (I2C_INT_EVENT0_IMASK_SRXFIFOFULL_SET)
	Target RX FIFO full.
#define	DL_I2C_INTERRUPT_TARGET_TXFIFO_EMPTY   (I2C_INT_EVENT0_IMASK_STXEMPTY_SET)
	Target TX FIFO empty. All data in Transmit FIFO shifted out and transmit goes into idle mode.
#define	DL_I2C_INTERRUPT_TARGET_START   (I2C_INT_EVENT0_IMASK_SSTART_SET)
	Target Start Condition detected.
#define	DL_I2C_INTERRUPT_TARGET_STOP   (I2C_INT_EVENT0_IMASK_SSTOP_SET)
	Target Stop Condition detected.
#define	DL_I2C_INTERRUPT_TARGET_GENERAL_CALL   (I2C_INT_EVENT0_IMASK_SGENCALL_SET)
	General Call Interrupt.
#define	DL_I2C_INTERRUPT_TARGET_EVENT1_DMA_DONE   (I2C_INT_EVENT0_IMASK_SDMA_DONE_TX_SET)
	Target DMA Done on Event 1 Publisher.
#define	DL_I2C_INTERRUPT_TARGET_EVENT2_DMA_DONE   (I2C_INT_EVENT0_IMASK_SDMA_DONE_RX_SET)
	Target DMA Done on Event 2 Publisher.
#define	DL_I2C_INTERRUPT_TARGET_PEC_RX_ERROR   (I2C_INT_EVENT0_IMASK_SPEC_RX_ERR_SET)
	Target SMBus/PMBus PEC Receive Error Interrupt.
#define	DL_I2C_INTERRUPT_TARGET_TXFIFO_UNDERFLOW   (I2C_INT_EVENT0_IMASK_STX_UNFL_SET)
	Target TX FIFO Underflow Interrupt.
#define	DL_I2C_INTERRUPT_TARGET_RXFIFO_OVERFLOW   (I2C_INT_EVENT0_IMASK_SRX_OVFL_SET)
	Target RX FIFO Overflow Interrupt.
#define	DL_I2C_INTERRUPT_TARGET_ARBITRATION_LOST   (I2C_INT_EVENT0_IMASK_SARBLOST_SET)
	Target Arbitration Lost Interrupt.
#define	DL_I2C_TARGET_INTERRUPT_OVERFLOW   (I2C_INT_EVENT0_IMASK_INTR_OVFL_SET)
	Interrupt Overflow Interrupt. Occurs when Target START or STOP interrupts overflow (i.e. occurs twice without being serviced)
#define	DL_I2C_INTERRUPT_TIMEOUT_A   (I2C_INT_EVENT0_IMASK_TIMEOUTA_SET)
	Timeout A Interrupt.
#define	DL_I2C_INTERRUPT_TIMEOUT_B   (I2C_INT_EVENT0_IMASK_TIMEOUTB_SET)
	Timeout B Interrupt.

Detailed Description