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Cdd_IpcCfg.h
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1/*
2*
3* Copyright (c) 2024 Texas Instruments Incorporated
4*
5* All rights reserved not granted herein.
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7* Limited License.
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11* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
12* terms herein. With respect to the foregoing patent license, such license is granted
13* solely to the extent that any such patent is necessary to Utilize the software alone.
14* The patent license shall not apply to any combinations which include this software,
15* other than combinations with devices manufactured by or for TI ("TI Devices").
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62
71/******************************************************************************
72 Project : CDD_IPC_AM62DX
73 Date : 2025-01-30 01:28:06
74 SW Ver : 11.1.0
75 Module Rele Ver : AUTOSAR 4.3.1
76
77 This file is generated by EB Tresos
78 Do not modify this file,otherwise the software may behave in unexpected way.
79******************************************************************************/
80
88#ifndef CDD_IPC_CFG_H_
89#define CDD_IPC_CFG_H_
90/* Generic requirements covered mapping */
91/*
92 * Design : DES_CDD_IPC_020
93 */
94/*
95 * Requirements : MCAL-3698
96 */
97
98/* ========================================================================== */
99/* Include Files */
100/* ========================================================================== */
101#include "Dem.h"
102#include "Os.h"
103#include <CddIpc/ipc_baremetal_hw/include/ipc_config.h>
104
105
106#ifdef __cplusplus
107extern "C" {
108#endif
109
110/* ========================================================================== */
111/* Macros & Typedefs */
112/* ========================================================================== */
113/*
114 * Design : DES_CDD_IPC_004, DES_CDD_IPC_002, DES_CDD_IPC_017
115 */
116/*
117 * Requirements : MCAL-921, MCAL-3703
118 */
123#define CDD_IPC_PRE_COMPILE_VARIANT (STD_ON)
124
126#define CDD_IPC_REMOTE_CORE_QNX (STD_OFF)
127
136#define CDD_IPC_ISR_VOID (0x00U)
138#define CDD_IPC_ISR_CAT1 (0x01U)
140#define CDD_IPC_ISR_CAT2 (0x02U)
141
142/*
143 * Design : DES_CDD_IPC_012
144 */
145/*
146 * Requirements : MCAL-3693
147 */
149#define CDD_IPC_DEV_ERROR_DETECT (STD_ON)
150/*
151 * Design : DES_CDD_IPC_012
152 */
153/*
154 * Requirements : MCAL-3692
155 */
157#define CDD_IPC_ISR_TYPE (CDD_IPC_ISR_CAT2)
158
163/*
164 * Design : DES_CDD_IPC_012
165 */
166/*
167 * Requirements : MCAL-3741
168 */
170#define CDD_IPC_VERSION_INFO_API (STD_ON)
171/*
172 * Design : DES_CDD_IPC_012
173 */
174/*
175 * Requirements : MCAL-3688
176 */
178#define CDD_IPC_DEINIT_API (STD_ON)
179/*
180 * Design : DES_CDD_IPC_012
181 */
182/*
183 * Requirements : MCAL-3689
184 */
186#define CDD_IPC_ANNOUNCE_API (STD_OFF)
187/*
188 * Design : DES_CDD_IPC_005, DES_CDD_IPC_012
189 */
190/*
191 * Requirements : MCAL-3687
192 */
194#define CDD_IPC_REGISTER_READBACK_API (STD_ON)
195/*
196 * Design :
197 */
198/*
199 * Requirements : MCAL-8266
200 */
202#define CDD_IPC_SAFETY_DIAGNOSTIC_API (STD_OFF)
203/*
204 * Design : DES_CDD_IPC_040
205 */
206/*
207 * Requirements : MCAL-4452
208 */
209
211#define CDD_IPC_IS_INIT_DONE_API (STD_ON)
212
213/*
214 * Design : DES_CDD_IPC_041
215 */
216/*
217 * Requirements : MCAL-4453
218 */
219
221#define CDD_IPC_GET_MAX_MSG_SIZE_API (STD_ON)
222
223
224/* @} */
225
230/*
231 * Design : DES_CDD_IPC_012
232 */
233/*
234 * Requirements : MCAL-3694, MCAL-3694
235 */
237#define CDD_IPC_OS_COUNTER_ID ((CounterType)OsCounter_0)
238
245/*
246 * Design : DES_CDD_IPC_020
247 */
248/*
249 * Requirements : MCAL-3693
250 */
251
252#ifndef CDD_IPC_E_HARDWARE_ERROR
254#define CDD_IPC_E_HARDWARE_ERROR (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
255#endif
256/* @} */
257
262/*
263 * Design : DES_CDD_IPC_018
264 */
265/*
266 * Requirements : MCAL-3699, MCAL-3700
267 */
268
269#define CDD_IPC_CORE_MCU_R5FSS0_0 (0U)
271#define CDD_IPC_CORE_R5FSS0_0 (1U)
273#define CDD_IPC_CORE_A53SS0_0 (2U)
275#define CDD_IPC_CORE_A53SS0_1 (3U)
277#define CDD_IPC_CORE_A53SS1_0 (4U)
279#define CDD_IPC_CORE_A53SS1_1 (5U)
281#define CDD_IPC_CORE_HSM_M4FSS0_0 (6U)
283#define CDD_IPC_CORE_C75SS0_0 (7U)
286#define CDD_IPC_CORE_MAX_PROCS (8U)
290#define CDD_IPC_OWN_CORE_ID (CDD_IPC_CORE_MCU_R5FSS0_0)
292#define CDD_IPC_REMOTE_CORE_R5FSS0_0_USED
294#define CDD_IPC_REMOTE_CORE_A53SS0_0_USED
296#define CDD_IPC_REMOTE_CORE_C75SS0_0_USED
299/* @} */
300
301
302
303
308/*
309 * Design : DES_CDD_IPC_005, DES_CDD_IPC_016
310 */
311/*
312 * Requirements : MCAL-3686,
313 */
314#define CDD_IPC_VERTIO_OBJECT_SIZE (0x1000U)
315 /* @} */
316
321/*
322 * Design : DES_CDD_IPC_016
323 */
324/*
325 * Requirements : MCAL-3686,
326 */
327#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_R5FSS0_0 (0U)
329#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_A53SS0_0 (1U)
331#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_C75SS0_0 (2U)
334/*
335 * Design : DES_CDD_IPC_016
336 */
337/*
338 * Requirements : MCAL-3755, MCAL-3682
339 */
340#define CDD_IPC_RPMSG_OBJ_SIZE (256U)
341
343#define CDD_IPC_NUM_VRING_BUFF (256U)
344
346#define CDD_IPC_MAX_MSG_LENGTH (496U)
347
349#define CDD_IPC_CH_0_BUFF_SIZE ((256U * ((496U) + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
351#define CDD_IPC_CH_1_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
353#define CDD_IPC_CH_2_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
355#define CDD_IPC_MAX_CHANNEL_CFG (3U)
362#define IPC_VRING_BUFFER_SIZE (0x100000U)
363
366#define IPC_MCU_R5FSS0_0 (0U)
367#define IPC_R5FSS0_0 (1U)
368#define IPC_A53SS0_0 (2U)
369#define IPC_A53SS0_1 (3U)
370#define IPC_A53SS1_0 (4U)
371#define IPC_A53SS1_1 (5U)
372#define IPC_HSM_M4FSS0_0 (6U)
373#define IPC_C75SS0_0 (7U)
375#define IPC_MAX_PROCS (8U)
379#define CDD_IPC_CORE_ID_MAX (8U)
380
381#define CDD_IPC_CORE_USED (3U)
382
383#define IPC_MAILBOX_CLUSTER_CNT (4U)
384
385/* @} */
386/* ========================================================================== */
387/* Globals Variables */
388/* ========================================================================== */
389/* Mailbox Cluster Base Address */
391
395extern Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS];
396
397extern Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS];
398
399/* ========================================================================== */
400/* Function Declarations */
401/* ========================================================================== */
402/*
403 * Design : DES_CDD_IPC_002, DES_CDD_IPC_017
404 */
405/*
406 * Requirements : MCAL-3703
407 */
408extern const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC;
409
410
411 /* \brief New Message notification function
412 *
413 */
414/*
415 * Design : DES_CDD_IPC_012, DES_CDD_IPC_026
416 */
417/*
418 * Requirements : MCAL-3701, MCAL-3691
419 */
420extern void Cdd_IpcNewMessageNotify(void);
423
424
425#if (STD_ON == CDD_IPC_ANNOUNCE_API)
426
431/*
432 * Design : DES_CDD_IPC_039
433 */
434/*
435 * Requirements : MCAL-4067, MCAL-4066
436 */
437extern void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId);
438
439#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify
440
441#endif /* STD_ON == CDD_IPC_ANNOUNCE_API */
442
443/*
444 * Design : DES_CDD_IPC_013
445 */
446/*
447 * Requirements : MCAL-3674
448 */
454
469ISR(Cdd_IpcIrqMbxFrom_R5FSS0_0);
470
472ISR(Cdd_IpcIrqMbxFrom_A53SS0_0);
473
475ISR( Cdd_IpcIrqMbxFromC75SS0_0 );
476
477
478#ifdef __cplusplus
479}
480#endif
481
482#endif /* #ifndef CDD_IPC_CFG_H_ */
483
484/* @} */
485
#define IPC_MAX_PROCS
Definition Cdd_IpcCfg.h:375
const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]
#define IPC_MAILBOX_CLUSTER_CNT
Definition Cdd_IpcCfg.h:383
void Cdd_IpcNewMessageNotify(void)
Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]
#define CDD_IPC_VERTIO_OBJECT_SIZE
Definition Cdd_IpcCfg.h:314
uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]
Communication Channels configured.
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
void Cdd_IpcNewMessageNotify_C75Core(void)
void Cdd_IpcNewMessageNotify_A53Core(void)
Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]
Processor IDs to name mapping for all processor.
void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
New Control Message notification function.
ISR(Cdd_IpcIrqMbxFrom_R5FSS0_0)
A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is...