103#include <CddIpc/ipc_baremetal_hw/include/ipc_config.h>
123#define CDD_IPC_PRE_COMPILE_VARIANT (STD_ON)
126#define CDD_IPC_REMOTE_CORE_QNX (STD_OFF)
136#define CDD_IPC_ISR_VOID (0x00U)
138#define CDD_IPC_ISR_CAT1 (0x01U)
140#define CDD_IPC_ISR_CAT2 (0x02U)
149#define CDD_IPC_DEV_ERROR_DETECT (STD_ON)
157#define CDD_IPC_ISR_TYPE (CDD_IPC_ISR_CAT2)
170#define CDD_IPC_VERSION_INFO_API (STD_ON)
178#define CDD_IPC_DEINIT_API (STD_ON)
186#define CDD_IPC_ANNOUNCE_API (STD_OFF)
194#define CDD_IPC_REGISTER_READBACK_API (STD_ON)
202#define CDD_IPC_SAFETY_DIAGNOSTIC_API (STD_OFF)
211#define CDD_IPC_IS_INIT_DONE_API (STD_ON)
221#define CDD_IPC_GET_MAX_MSG_SIZE_API (STD_ON)
237#define CDD_IPC_OS_COUNTER_ID ((CounterType)OsCounter_0)
252#ifndef CDD_IPC_E_HARDWARE_ERROR
254#define CDD_IPC_E_HARDWARE_ERROR (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
269#define CDD_IPC_CORE_MCU_R5FSS0_0 (0U)
271#define CDD_IPC_CORE_R5FSS0_0 (1U)
273#define CDD_IPC_CORE_A53SS0_0 (2U)
275#define CDD_IPC_CORE_A53SS0_1 (3U)
277#define CDD_IPC_CORE_A53SS1_0 (4U)
279#define CDD_IPC_CORE_A53SS1_1 (5U)
281#define CDD_IPC_CORE_HSM_M4FSS0_0 (6U)
283#define CDD_IPC_CORE_C75SS0_0 (7U)
286#define CDD_IPC_CORE_MAX_PROCS (8U)
290#define CDD_IPC_OWN_CORE_ID (CDD_IPC_CORE_MCU_R5FSS0_0)
292#define CDD_IPC_REMOTE_CORE_R5FSS0_0_USED
294#define CDD_IPC_REMOTE_CORE_A53SS0_0_USED
296#define CDD_IPC_REMOTE_CORE_C75SS0_0_USED
314#define CDD_IPC_VERTIO_OBJECT_SIZE (0x1000U)
327#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_R5FSS0_0 (0U)
329#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_A53SS0_0 (1U)
331#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_C75SS0_0 (2U)
340#define CDD_IPC_RPMSG_OBJ_SIZE (256U)
343#define CDD_IPC_NUM_VRING_BUFF (256U)
346#define CDD_IPC_MAX_MSG_LENGTH (496U)
349#define CDD_IPC_CH_0_BUFF_SIZE ((256U * ((496U) + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
351#define CDD_IPC_CH_1_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
353#define CDD_IPC_CH_2_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
355#define CDD_IPC_MAX_CHANNEL_CFG (3U)
362#define IPC_VRING_BUFFER_SIZE (0x100000U)
366#define IPC_MCU_R5FSS0_0 (0U)
367#define IPC_R5FSS0_0 (1U)
368#define IPC_A53SS0_0 (2U)
369#define IPC_A53SS0_1 (3U)
370#define IPC_A53SS1_0 (4U)
371#define IPC_A53SS1_1 (5U)
372#define IPC_HSM_M4FSS0_0 (6U)
373#define IPC_C75SS0_0 (7U)
375#define IPC_MAX_PROCS (8U)
379#define CDD_IPC_CORE_ID_MAX (8U)
381#define CDD_IPC_CORE_USED (3U)
383#define IPC_MAILBOX_CLUSTER_CNT (4U)
425#if (STD_ON == CDD_IPC_ANNOUNCE_API)
439#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify
469ISR(Cdd_IpcIrqMbxFrom_R5FSS0_0);
472ISR(Cdd_IpcIrqMbxFrom_A53SS0_0);
475ISR( Cdd_IpcIrqMbxFromC75SS0_0 );
#define IPC_MAX_PROCS
Definition Cdd_IpcCfg.h:375
const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]
#define IPC_MAILBOX_CLUSTER_CNT
Definition Cdd_IpcCfg.h:383
void Cdd_IpcNewMessageNotify(void)
Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]
#define CDD_IPC_VERTIO_OBJECT_SIZE
Definition Cdd_IpcCfg.h:314
uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]
Communication Channels configured.
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
void Cdd_IpcNewMessageNotify_C75Core(void)
void Cdd_IpcNewMessageNotify_A53Core(void)
Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]
Processor IDs to name mapping for all processor.
void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
New Control Message notification function.
ISR(Cdd_IpcIrqMbxFrom_R5FSS0_0)
A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is...