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Macros
CDD Ipc Configuration

Introduction

This files defines CDD Ipc configuration structures

Macros

#define CDD_IPC_PRE_COMPILE_VARIANT   (STD_ON)
 Pre-Compile Build Variant flag. STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild.
 
#define CDD_IPC_REMOTE_CORE_QNX   (STD_OFF)
 Is One of Remote Core QNX.
 

Communication Channel ID & Configured Buffer sizes

const uint32 IPC_Mailbox_BasePhyAddr [IPC_MAILBOX_CLUSTER_CNT]
 
Ipc_ProcInfo g_Ipc_mp_procInfo [IPC_MAX_PROCS]
 Processor IDs to name mapping for all processor.
 
Ipc_MailboxInfo g_IPC_MailboxInfo [IPC_MAX_PROCS][IPC_MAX_PROCS]
 
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
 
uint8 Cdd_IpcDrvVertIoObj [CDD_IPC_VERTIO_OBJECT_SIZE]
 Communication Channels configured.
 
void Cdd_IpcNewMessageNotify (void)
 
void Cdd_IpcNewMessageNotify_A53Core (void)
 
void Cdd_IpcNewMessageNotify_C75Core (void)
 
void Cdd_IpcNewCtrlMessageNotify (uint32 remoteProcId)
 New Control Message notification function.
 
 ISR (Cdd_IpcIrqMbxFrom_R5FSS0_0)
 A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is used determine presence of data from the remote core in the vring.
 
 ISR (Cdd_IpcIrqMbxFrom_A53SS0_0)
 ISR for New Message, from A53 0 0.
 
 ISR (Cdd_IpcIrqMbxFromC75SS0_0)
 ISR for New Message, from C75SS0_0.
 
#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_R5FSS0_0   (0U)
 
#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_A53SS0_0   (1U)
 
#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_C75SS0_0   (2U)
 
#define CDD_IPC_RPMSG_OBJ_SIZE   (256U)
 
#define CDD_IPC_NUM_VRING_BUFF   (256U)
 
#define CDD_IPC_MAX_MSG_LENGTH   (496U)
 
#define CDD_IPC_CH_0_BUFF_SIZE   ((256U * ((496U) + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
 
#define CDD_IPC_CH_1_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
 
#define CDD_IPC_CH_2_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
 
#define CDD_IPC_MAX_CHANNEL_CFG   (3U)
 
#define IPC_VRING_BUFFER_SIZE   (0x100000U)
 VRing Buffer Size required for all core combinations.
 
#define IPC_MCU_R5FSS0_0   (0U)
 Core definitions.
 
#define IPC_R5FSS0_0   (1U)
 
#define IPC_A53SS0_0   (2U)
 
#define IPC_A53SS0_1   (3U)
 
#define IPC_A53SS1_0   (4U)
 
#define IPC_A53SS1_1   (5U)
 
#define IPC_HSM_M4FSS0_0   (6U)
 
#define IPC_C75SS0_0   (7U)
 
#define IPC_MAX_PROCS   (8U)
 
#define CDD_IPC_CORE_ID_MAX   (8U)
 IPC maximum possible core ID.
 
#define CDD_IPC_CORE_USED   (3U)
 
#define IPC_MAILBOX_CLUSTER_CNT   (4U)
 
#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN   Cdd_IpcNewCtrlMessageNotify
 

CDD Driver ISR category level

Defines for CDD Driver ISR ISR category level

#define CDD_IPC_ISR_VOID   (0x00U)
 void ISR type
 
#define CDD_IPC_ISR_CAT1   (0x01U)
 Category 1 ISR type.
 
#define CDD_IPC_ISR_CAT2   (0x02U)
 Category 2 ISR type.
 
#define CDD_IPC_DEV_ERROR_DETECT   (STD_ON)
 Enable/disable CDD Ipc dev detect error.
 
#define CDD_IPC_ISR_TYPE   (CDD_IPC_ISR_CAT2)
 ISR type.
 

Pre-Compile Switches for API Services

#define CDD_IPC_VERSION_INFO_API   (STD_ON)
 Enable/disable version info API.
 
#define CDD_IPC_DEINIT_API   (STD_ON)
 Enable/disable De Initialization API.
 
#define CDD_IPC_ANNOUNCE_API   (STD_OFF)
 Enable/disable Service Announcement API.
 
#define CDD_IPC_REGISTER_READBACK_API   (STD_ON)
 Enable/disable Critical Register read back API.
 
#define CDD_IPC_SAFETY_DIAGNOSTIC_API   (STD_OFF)
 Enable/disable safety diagnostics API.
 
#define CDD_IPC_IS_INIT_DONE_API   (STD_ON)
 Enable/disable Cdd_IpcIsInitDone API.
 
#define CDD_IPC_GET_MAX_MSG_SIZE_API   (STD_ON)
 Enable/disable Cdd_IpcGetMaxMsgSize API.
 

Dependency configurations

#define CDD_IPC_OS_COUNTER_ID   ((CounterType)OsCounter_0)
 Counter ID for counter used to count wait ticks.
 

Cdd Ipc DEM Error codes to report

Pre-compile switches for enabling/disabling DEM events

#define CDD_IPC_E_HARDWARE_ERROR   (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
 Hardware failed.
 

CORE Names

#define CDD_IPC_CORE_MCU_R5FSS0_0   (0U)
 
#define CDD_IPC_CORE_R5FSS0_0   (1U)
 
#define CDD_IPC_CORE_A53SS0_0   (2U)
 
#define CDD_IPC_CORE_A53SS0_1   (3U)
 
#define CDD_IPC_CORE_A53SS1_0   (4U)
 
#define CDD_IPC_CORE_A53SS1_1   (5U)
 
#define CDD_IPC_CORE_HSM_M4FSS0_0   (6U)
 
#define CDD_IPC_CORE_C75SS0_0   (7U)
 
#define CDD_IPC_CORE_MAX_PROCS   (8U)
 
#define CDD_IPC_OWN_CORE_ID   (CDD_IPC_CORE_MCU_R5FSS0_0)
 Used core identifiers.
 
#define CDD_IPC_REMOTE_CORE_R5FSS0_0_USED
 
#define CDD_IPC_REMOTE_CORE_A53SS0_0_USED
 
#define CDD_IPC_REMOTE_CORE_C75SS0_0_USED
 

VirtIO Object

#define CDD_IPC_VERTIO_OBJECT_SIZE   (0x1000U)
 

Macro Definition Documentation

◆ CDD_IPC_PRE_COMPILE_VARIANT

#define CDD_IPC_PRE_COMPILE_VARIANT   (STD_ON)

Pre-Compile Build Variant flag. STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild.

◆ CDD_IPC_REMOTE_CORE_QNX

#define CDD_IPC_REMOTE_CORE_QNX   (STD_OFF)

Is One of Remote Core QNX.

◆ CDD_IPC_ISR_VOID

#define CDD_IPC_ISR_VOID   (0x00U)

void ISR type

◆ CDD_IPC_ISR_CAT1

#define CDD_IPC_ISR_CAT1   (0x01U)

Category 1 ISR type.

◆ CDD_IPC_ISR_CAT2

#define CDD_IPC_ISR_CAT2   (0x02U)

Category 2 ISR type.

◆ CDD_IPC_DEV_ERROR_DETECT

#define CDD_IPC_DEV_ERROR_DETECT   (STD_ON)

Enable/disable CDD Ipc dev detect error.

◆ CDD_IPC_ISR_TYPE

#define CDD_IPC_ISR_TYPE   (CDD_IPC_ISR_CAT2)

ISR type.

◆ CDD_IPC_VERSION_INFO_API

#define CDD_IPC_VERSION_INFO_API   (STD_ON)

Enable/disable version info API.

◆ CDD_IPC_DEINIT_API

#define CDD_IPC_DEINIT_API   (STD_ON)

Enable/disable De Initialization API.

◆ CDD_IPC_ANNOUNCE_API

#define CDD_IPC_ANNOUNCE_API   (STD_OFF)

Enable/disable Service Announcement API.

◆ CDD_IPC_REGISTER_READBACK_API

#define CDD_IPC_REGISTER_READBACK_API   (STD_ON)

Enable/disable Critical Register read back API.

◆ CDD_IPC_SAFETY_DIAGNOSTIC_API

#define CDD_IPC_SAFETY_DIAGNOSTIC_API   (STD_OFF)

Enable/disable safety diagnostics API.

◆ CDD_IPC_IS_INIT_DONE_API

#define CDD_IPC_IS_INIT_DONE_API   (STD_ON)

Enable/disable Cdd_IpcIsInitDone API.

◆ CDD_IPC_GET_MAX_MSG_SIZE_API

#define CDD_IPC_GET_MAX_MSG_SIZE_API   (STD_ON)

Enable/disable Cdd_IpcGetMaxMsgSize API.

◆ CDD_IPC_OS_COUNTER_ID

#define CDD_IPC_OS_COUNTER_ID   ((CounterType)OsCounter_0)

Counter ID for counter used to count wait ticks.

◆ CDD_IPC_E_HARDWARE_ERROR

#define CDD_IPC_E_HARDWARE_ERROR   (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)

Hardware failed.

◆ CDD_IPC_CORE_MCU_R5FSS0_0

#define CDD_IPC_CORE_MCU_R5FSS0_0   (0U)

ARM MCU R5FSS0_0 - core0

◆ CDD_IPC_CORE_R5FSS0_0

#define CDD_IPC_CORE_R5FSS0_0   (1U)

ARM DM R5FSS0_0 - core0

◆ CDD_IPC_CORE_A53SS0_0

#define CDD_IPC_CORE_A53SS0_0   (2U)

ARM A53SS0_0 - core0

◆ CDD_IPC_CORE_A53SS0_1

#define CDD_IPC_CORE_A53SS0_1   (3U)

ARM A53SS0_1 - core0

◆ CDD_IPC_CORE_A53SS1_0

#define CDD_IPC_CORE_A53SS1_0   (4U)

ARM MCU R5FSS0_0 - core1

◆ CDD_IPC_CORE_A53SS1_1

#define CDD_IPC_CORE_A53SS1_1   (5U)

ARM A53SS1_1 - core1

◆ CDD_IPC_CORE_HSM_M4FSS0_0

#define CDD_IPC_CORE_HSM_M4FSS0_0   (6U)

ARM HSM_M4FSS0_0 - core0

◆ CDD_IPC_CORE_C75SS0_0

#define CDD_IPC_CORE_C75SS0_0   (7U)

ARM C75SS0_0 - core0

◆ CDD_IPC_CORE_MAX_PROCS

#define CDD_IPC_CORE_MAX_PROCS   (8U)

MAX processors

◆ CDD_IPC_OWN_CORE_ID

#define CDD_IPC_OWN_CORE_ID   (CDD_IPC_CORE_MCU_R5FSS0_0)

Used core identifiers.

Own core ID

◆ CDD_IPC_REMOTE_CORE_R5FSS0_0_USED

#define CDD_IPC_REMOTE_CORE_R5FSS0_0_USED

Remote core DM R5FSS0_0 is being used

◆ CDD_IPC_REMOTE_CORE_A53SS0_0_USED

#define CDD_IPC_REMOTE_CORE_A53SS0_0_USED

Remote core A53SS0_0 is being used

◆ CDD_IPC_REMOTE_CORE_C75SS0_0_USED

#define CDD_IPC_REMOTE_CORE_C75SS0_0_USED

Remote core C75SS0_0 is being used

◆ CDD_IPC_VERTIO_OBJECT_SIZE

#define CDD_IPC_VERTIO_OBJECT_SIZE   (0x1000U)

◆ CddIpcConf_IpcComChanId_CDD_IPC_CORE_R5FSS0_0

#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_R5FSS0_0   (0U)

Channel identifiers

◆ CddIpcConf_IpcComChanId_CDD_IPC_CORE_A53SS0_0

#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_A53SS0_0   (1U)

Channel identifiers

◆ CddIpcConf_IpcComChanId_CDD_IPC_CORE_C75SS0_0

#define CddIpcConf_IpcComChanId_CDD_IPC_CORE_C75SS0_0   (2U)

Channel identifiers

◆ CDD_IPC_RPMSG_OBJ_SIZE

#define CDD_IPC_RPMSG_OBJ_SIZE   (256U)

Number of VRING Buffers

◆ CDD_IPC_NUM_VRING_BUFF

#define CDD_IPC_NUM_VRING_BUFF   (256U)

Max size of a buffer in a VRING

◆ CDD_IPC_MAX_MSG_LENGTH

#define CDD_IPC_MAX_MSG_LENGTH   (496U)

Size of RP Message Object

◆ CDD_IPC_CH_0_BUFF_SIZE

#define CDD_IPC_CH_0_BUFF_SIZE   ((256U * ((496U) + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)

Size of buffer allocated to the channel

◆ CDD_IPC_CH_1_BUFF_SIZE

#define CDD_IPC_CH_1_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)

Size of buffer allocated to the channel

◆ CDD_IPC_CH_2_BUFF_SIZE

#define CDD_IPC_CH_2_BUFF_SIZE   ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)

Size of buffer allocated to the channel

◆ CDD_IPC_MAX_CHANNEL_CFG

#define CDD_IPC_MAX_CHANNEL_CFG   (3U)

Maximum number of communication channels configured

◆ IPC_VRING_BUFFER_SIZE

#define IPC_VRING_BUFFER_SIZE   (0x100000U)

VRing Buffer Size required for all core combinations.

◆ IPC_MCU_R5FSS0_0

#define IPC_MCU_R5FSS0_0   (0U)

Core definitions.

ARM MCU R5FSS0_0 - core0

◆ IPC_R5FSS0_0

#define IPC_R5FSS0_0   (1U)

ARM DM R5FSS0_0 - core0

◆ IPC_A53SS0_0

#define IPC_A53SS0_0   (2U)

ARM A53SS0_0 - core0

◆ IPC_A53SS0_1

#define IPC_A53SS0_1   (3U)

ARM A53SS0_1 - core0

◆ IPC_A53SS1_0

#define IPC_A53SS1_0   (4U)

ARM A53SS1_0 - core1

◆ IPC_A53SS1_1

#define IPC_A53SS1_1   (5U)

ARM A53SS1_1 - core1

◆ IPC_HSM_M4FSS0_0

#define IPC_HSM_M4FSS0_0   (6U)

ARM HSM_M4FSS0_0 - core0

◆ IPC_C75SS0_0

#define IPC_C75SS0_0   (7U)

ARM C75SS0_0 - core0

◆ IPC_MAX_PROCS

#define IPC_MAX_PROCS   (8U)

Maximum Processors

◆ CDD_IPC_CORE_ID_MAX

#define CDD_IPC_CORE_ID_MAX   (8U)

IPC maximum possible core ID.

◆ CDD_IPC_CORE_USED

#define CDD_IPC_CORE_USED   (3U)

◆ IPC_MAILBOX_CLUSTER_CNT

#define IPC_MAILBOX_CLUSTER_CNT   (4U)

◆ CDD_IPC_NEW_CTRL_MSG_NTFY_FXN

#define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN   Cdd_IpcNewCtrlMessageNotify

Function Documentation

◆ Cdd_IpcNewMessageNotify()

void Cdd_IpcNewMessageNotify ( void )
extern

◆ Cdd_IpcNewMessageNotify_A53Core()

void Cdd_IpcNewMessageNotify_A53Core ( void )
extern

◆ Cdd_IpcNewMessageNotify_C75Core()

void Cdd_IpcNewMessageNotify_C75Core ( void )
extern

◆ Cdd_IpcNewCtrlMessageNotify()

void Cdd_IpcNewCtrlMessageNotify ( uint32 remoteProcId)
extern

New Control Message notification function.

◆ ISR() [1/3]

ISR ( Cdd_IpcIrqMbxFrom_R5FSS0_0 )

A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is used determine presence of data from the remote core in the vring.

Typically, we would have 1 interrupt for each remote core. Due to system resource needs, multiple remote cores could use a single interrupt.

Depending on the SoC variant, the isr to registered with interrupt will change. Please refer CDD IPC example application to associate right ISR with interrupt.

ISR for New Message, from DM R5F 0 0

◆ ISR() [2/3]

ISR ( Cdd_IpcIrqMbxFrom_A53SS0_0 )

ISR for New Message, from A53 0 0.

◆ ISR() [3/3]

ISR ( Cdd_IpcIrqMbxFromC75SS0_0 )

ISR for New Message, from C75SS0_0.

Variable Documentation

◆ IPC_Mailbox_BasePhyAddr

const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]
extern

◆ g_Ipc_mp_procInfo

Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]
extern

Processor IDs to name mapping for all processor.

◆ g_IPC_MailboxInfo

Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]
extern

◆ CddIpcConfiguraions_PC

const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
extern

◆ Cdd_IpcDrvVertIoObj

uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]
extern

Communication Channels configured.