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Spi.h
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1/*
2*
3* Copyright (c) 2024 Texas Instruments Incorporated
4*
5* All rights reserved not granted herein.
6*
7* Limited License.
8*
9* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
10* license under copyrights and patents it now or hereafter owns or controls to make,
11* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
12* terms herein. With respect to the foregoing patent license, such license is granted
13* solely to the extent that any such patent is necessary to Utilize the software alone.
14* The patent license shall not apply to any combinations which include this software,
15* other than combinations with devices manufactured by or for TI ("TI Devices").
16* No hardware patent is licensed hereunder.
17*
18* Redistributions must preserve existing copyright notices and reproduce this license
19* (including the above copyright notice and the disclaimer and (if applicable) source
20* code license limitations below) in the documentation and/or other materials provided
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22*
23* Redistribution and use in binary form, without modification, are permitted provided
24* that the following conditions are met:
25*
26* * No reverse engineering, decompilation, or disassembly of this software is
27* permitted with respect to any software provided in binary form.
28*
29* * any redistribution and use are licensed by TI for use only with TI Devices.
30*
31* * Nothing shall obligate TI to provide you with source code for the software
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33*
34* If software source code is provided to you, modification and redistribution of the
35* source code are permitted provided that the following conditions are met:
36*
37* * any redistribution and use of the source code, including any resulting derivative
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47*
48* DISCLAIMER.
49*
50* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
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60*
61*/
62
116/*
117 * Below are the global design requirements which are met by this SPI handler
118 * driver which can't be mapped to a particular source ID
119 */
120/*
121 * Design: MCAL-6422,MCAL-6412,MCAL-6690,MCAL-6487,MCAL-6429,MCAL-6683,MCAL-6384,MCAL-6478,MCAL-6383,MCAL-6593,MCAL-6573,MCAL-6381,MCAL-6492,MCAL-6610,MCAL-6658,MCAL-6451,MCAL-6449,MCAL-6448,MCAL-6581,MCAL-6710,MCAL-6527,MCAL-6642,MCAL-6458,MCAL-6544
122 */
123
124/*
125 * Below are the SPI's module environment design requirements which can't be mapped
126 * to this driver.
127 */
128/*
129 * Design: MCAL-6719,MCAL-6486,MCAL-6415,MCAL-6685,MCAL-6421,MCAL-6390,MCAL-6608,MCAL-6670,MCAL-6643
130 */
131
132#ifndef SPI_H_
133#define SPI_H_
134
135/* ========================================================================== */
136/* Include Files */
137/* ========================================================================== */
138#include "Std_Types.h"
139#include "Spi_Cfg.h"
140#if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) || defined (SOC_J742S2)
141#include <ti/drv/udma/udma.h>
142#endif
143#include "Spi/mcspi_hw/V0/mcspi.h"
144
145#ifdef __cplusplus
146extern "C"
147{
148#endif
149
150/* ========================================================================== */
151/* Macros & Typedefs */
152/* ========================================================================== */
153
161#define SPI_SW_MAJOR_VERSION (9U)
163#define SPI_SW_MINOR_VERSION (2U)
165#define SPI_SW_PATCH_VERSION (0U)
166/* @} */
167
175#define SPI_AR_RELEASE_MAJOR_VERSION (4U)
177#define SPI_AR_RELEASE_MINOR_VERSION (3U)
179#define SPI_AR_RELEASE_REVISION_VERSION (1U)
180/* @} */
181
187#define SPI_VENDOR_ID ((uint16) 44U)
189#define SPI_MODULE_ID ((uint16) 83U)
191#define SPI_INSTANCE_ID ((uint8) 0U)
192/* @} */
193
199#define SPI_IB (0U)
201#define SPI_EB (1U)
203#define SPI_IB_EB (2U)
204/* @} */
205
206
208/*
209 * Design: MCAL-6691,MCAL-6394,MCAL-6615
210 */
211typedef uint8 Spi_DataBufferType;
216/*
217 * Design: MCAL-6625,MCAL-6669
218 */
219typedef uint16 Spi_NumberOfDataType;
221/*
222 * Design: MCAL-6528,MCAL-6493,MCAL-6687
223 */
224typedef uint8 Spi_ChannelType;
226/*
227 * Design: MCAL-6457,MCAL-6689,MCAL-6728
228 */
229typedef uint16 Spi_JobType;
231/*
232 * Design: MCAL-6639,MCAL-6505,MCAL-6729
233 */
234typedef uint8 Spi_SequenceType;
239/*
240 * Design: MCAL-6655,MCAL-6682,MCAL-6707
241 */
242typedef uint8 Spi_HWUnitType;
243
250#ifndef SPI_E_PARAM_CHANNEL
252#define SPI_E_PARAM_CHANNEL ((uint8) 0x0AU)
253#endif
254#ifndef SPI_E_PARAM_JOB
256#define SPI_E_PARAM_JOB ((uint8) 0x0BU)
257#endif
258#ifndef SPI_E_PARAM_SEQ
260#define SPI_E_PARAM_SEQ ((uint8) 0x0CU)
261#endif
262#ifndef SPI_E_PARAM_LENGTH
264#define SPI_E_PARAM_LENGTH ((uint8) 0x0DU)
265#endif
266#ifndef SPI_E_PARAM_UNIT
268#define SPI_E_PARAM_UNIT ((uint8) 0x0EU)
269#endif
270#ifndef SPI_E_PARAM_POINTER
272#define SPI_E_PARAM_POINTER ((uint8) 0x10U)
273#endif
274#ifndef SPI_E_UNINIT
276#define SPI_E_UNINIT ((uint8) 0x1AU)
277#endif
278#ifndef SPI_E_SEQ_PENDING
280#define SPI_E_SEQ_PENDING ((uint8) 0x2AU)
281#endif
282#ifndef SPI_E_SEQ_IN_PROCESS
284#define SPI_E_SEQ_IN_PROCESS ((uint8) 0x3AU)
285#endif
286#ifndef SPI_E_ALREADY_INITIALIZED
291#define SPI_E_ALREADY_INITIALIZED ((uint8) 0x4AU)
292#endif
293#ifndef SPI_E_SEQUENCE_NOT_OK
295#define SPI_E_SEQUENCE_NOT_OK ((uint8) 0x5AU)
296#endif
297
298/* @} */
299
308#define SPI_SID_INIT ((uint8) 0x00U)
310#define SPI_SID_DEINIT ((uint8) 0x01U)
312#define SPI_SID_WRITE_IB ((uint8) 0x02U)
314#define SPI_SID_ASYNC_TRANSMIT ((uint8) 0x03U)
316#define SPI_SID_READ_IB ((uint8) 0x04U)
318#define SPI_SID_SETUP_EB ((uint8) 0x05U)
320#define SPI_SID_GET_STATUS ((uint8) 0x06U)
322#define SPI_SID_GET_JOB_RESULT ((uint8) 0x07U)
324#define SPI_SID_GET_SEQ_RESULT ((uint8) 0x08U)
326#define SPI_SID_GET_VERSION_INFO ((uint8) 0x09U)
328#define SPI_SID_SYNC_TRANSMIT ((uint8) 0x0AU)
330#define SPI_SID_GET_HW_UNIT_STATUS ((uint8) 0x0BU)
332#define SPI_SID_CANCEL ((uint8) 0x0CU)
334#define SPI_SID_SET_ASYNC_MODE ((uint8) 0x0DU)
336#define SPI_SID_MAINFUNCTION_HANDLING ((uint8) 0x10U)
338#define SPI_SID_DMA_INIT ((uint8) 0x20U)
339/* @} */
340
347/*
348 * Design: MCAL-6699
349 */
350#define SPI_MCSPI_FCLK (48000000U)
351
360#define SPI_CFG_ID_0 (0x01U)
363#define SPI_CFG_ID_1 (0x02U)
365#define SPI_CFG_ID_2 (0x04U)
367#define SPI_CFG_ID_3 (0x08U)
369#define SPI_CFG_ID_4 (0x10U)
371#define SPI_CFG_ID_5 (0x20U)
373#define SPI_CFG_ID_6 (0x40U)
375#define SPI_CFG_ID_7 (0x80U)
377#define SPI_CFG_ID_8 (0x100U)
378/* @} */
379
380/* ========================================================================== */
381/* Structures and Enums */
382/* ========================================================================== */
383
392/*
393 * Design: MCAL-6531,MCAL-6648,MCAL-6537,MCAL-6574
394 */
395typedef enum
396{
397 SPI_UNINIT = 0U,
399 SPI_IDLE = 1U,
401 SPI_BUSY = 2U
404
409/*
410 * Design: MCAL-6703,MCAL-6425,MCAL-6430
411 */
412typedef enum
413{
414 SPI_JOB_OK = 0U,
416 SPI_JOB_PENDING = 1U,
419 SPI_JOB_FAILED = 2U,
421 SPI_JOB_QUEUED = 3U
425
430/*
431 * Design: MCAL-6512,MCAL-6607,MCAL-6686
432 */
433typedef enum
434{
435 SPI_SEQ_OK = 0U,
437 SPI_SEQ_PENDING = 1U,
440 SPI_SEQ_FAILED = 2U,
445
450typedef enum
451{
452 SPI_HW_UNIT_OK = 0U,
459
464/*
465 * Design: MCAL-6502,MCAL-6659,MCAL-6420,MCAL-6475,MCAL-6419,MCAL-6517,MCAL-6641
466 */
467typedef enum
468{
469 SPI_POLLING_MODE = 0U,
477
481typedef enum
482{
483 SPI_MSB = 0U,
485 SPI_LSB = 1U
488
492typedef enum
493{
494 SPI_LOW = STD_LOW,
499
503typedef enum
504{
505 SPI_CS0 = 0U,
507 SPI_CS1,
509 SPI_CS2,
511 SPI_CS3
514
519typedef enum
520{
521 SPI_CLK_MODE_0 = 0x00U,
523 SPI_CLK_MODE_1 = 0x01U,
525 SPI_CLK_MODE_2 = 0x02U,
527 SPI_CLK_MODE_3 = 0x03U,
530
543typedef enum
544{
545 SPI_TX_RX_MODE_BOTH = 0x00U,
550
554/*
555 * Design: MCAL-6597
556 */
568
572typedef enum
573{
574 SPI_SINGLE = 0U,
576 SPI_CONTINUOUS = 1U
579
584typedef enum
585{
586 SPI_DATADELAY_0 = 0U,
588 SPI_DATADELAY_1 = 1U,
590 SPI_DATADELAY_2 = 2U,
592 SPI_DATADELAY_3 = 3U,
595
599typedef enum
600{
606
621
625typedef enum
626{
627 SPI_NO_EVENT = 0U,
634
642typedef void (*Spi_CacheWbInv)(uint8 *BufPtr,
643 uint16 LenByte);
644
652typedef void (*Spi_CacheWb)(uint8 *BufPtr,
653 uint16 LenByte);
654
662typedef void (*Spi_CacheInv)(uint8 *BufPtr,
663 uint16 LenByte);
664
668/*
669 * Design: MCAL-6529,MCAL-6519,MCAL-6649,MCAL-6716,MCAL-6619
670 */
694
735
745
749/*
750 * Design: MCAL-6692,MCAL-6437,MCAL-6684,MCAL-6522,MCAL-6572,MCAL-6406,MCAL-6632,MCAL-6476
751 */
766
770/*
771 * Design: MCAL-6496,MCAL-6536,MCAL-6742,MCAL-6413
772 */
785
800
804/*
805 * Design: MCAL-6570,MCAL-6423,MCAL-6588,MCAL-6485,MCAL-6733
806 */
847
851typedef struct Spi_ChannelConfigType_PC_s
852{
856
857/*
858 * Design: MCAL-6717,MCAL-6650
859 */
863typedef struct Spi_JobConfigType_PC_s
864{
873
877typedef struct Spi_SeqConfigType_PC_s
878{
882
883#if (STD_ON == SPI_REGISTER_READBACK_API)
888typedef struct
889{
890 /*
891 * McSPI related registers
892 */
899 uint32 mcspiRev;
903 uint32 mcspiSyst;
917#endif /* #if (STD_ON == SPI_REGISTER_READBACK_API) */
918/* @} */
919/* @} */
920/* ========================================================================== */
921/* Function Declarations */
922/* ========================================================================== */
923
941FUNC(void, SPI_CODE) Spi_Init(
942 P2CONST(Spi_ConfigType, AUTOMATIC, SPI_CONFIG_DATA) CfgPtr);
943
964FUNC(Std_ReturnType, SPI_CODE) Spi_DeInit(void);
965
983FUNC(Spi_StatusType, SPI_CODE) Spi_GetStatus(void);
984
1005
1028 Spi_SequenceType Sequence);
1029
1030#if (STD_ON == SPI_VERSION_INFO_API)
1051FUNC(void, SPI_CODE) Spi_GetVersionInfo(
1052 P2VAR(Std_VersionInfoType, AUTOMATIC, SPI_APPL_DATA) versioninfo);
1053#endif /* #if (STD_ON == SPI_VERSION_INFO_API) */
1054
1055#if (STD_ON == SPI_HW_STATUS_API)
1078#endif /* #if (STD_ON == SPI_HW_STATUS_API) */
1079
1080#if ((SPI_CHANNELBUFFERS == SPI_IB) || (SPI_CHANNELBUFFERS == SPI_IB_EB))
1109FUNC(Std_ReturnType, SPI_CODE) Spi_WriteIB(
1110 Spi_ChannelType Channel,
1111 P2CONST(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) DataBufferPtr);
1112
1138FUNC(Std_ReturnType, SPI_CODE) Spi_ReadIB(
1139 Spi_ChannelType Channel,
1140 P2VAR(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) DataBufferPointer);
1141#endif /* #if SPI_IB || SPI_IB_EB */
1142
1143#if ((SPI_CHANNELBUFFERS == SPI_EB) || (SPI_CHANNELBUFFERS == SPI_IB_EB))
1176FUNC(Std_ReturnType, SPI_CODE) Spi_SetupEB(
1177 Spi_ChannelType Channel,
1178 P2CONST(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) SrcDataBufferPtr,
1179 P2VAR(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) DesDataBufferPtr,
1180 Spi_NumberOfDataType Length);
1181#endif /* #if ((SPI_CHANNELBUFFERS == SPI_EB) || (SPI_CHANNELBUFFERS ==
1182 *SPI_IB_EB)) */
1183
1184#if ((SPI_SCALEABILITY == SPI_LEVEL_1) || (SPI_SCALEABILITY == \
1185 SPI_LEVEL_2))
1206FUNC(Std_ReturnType, SPI_CODE) Spi_AsyncTransmit(Spi_SequenceType Sequence);
1207#endif /* #if ((SPI_SCALEABILITY == SPI_LEVEL_1) ||
1208 *(SPI_SCALEABILITY == SPI_LEVEL_2)) */
1209
1210#if (STD_ON == SPI_CANCEL_API)
1229FUNC(void, SPI_CODE) Spi_Cancel(Spi_SequenceType Sequence);
1230#endif /* #if (STD_ON == SPI_CANCEL_API) */
1231
1232#if ((SPI_SCALEABILITY == SPI_LEVEL_0) || (SPI_SCALEABILITY == \
1233 SPI_LEVEL_2))
1254FUNC(Std_ReturnType, SPI_CODE) Spi_SyncTransmit(Spi_SequenceType Sequence);
1255#endif /* #if ((SPI_SCALEABILITY == SPI_LEVEL_0) ||
1256 *(SPI_SCALEABILITY == SPI_LEVEL_2)) */
1257
1258#if (SPI_SCALEABILITY == SPI_LEVEL_2)
1281FUNC(Std_ReturnType, SPI_CODE) Spi_SetAsyncMode(Spi_AsyncModeType Mode);
1282#endif /* #if (SPI_SCALEABILITY == SPI_LEVEL_2) */
1283
1306FUNC(void, SPI_CODE) Spi_MainFunction_Handling(void);
1307
1308#if (STD_ON == SPI_DMA_ENABLE)
1326FUNC(Std_ReturnType, SPI_CODE) Spi_GetDmaHandle(
1327 struct Udma_DrvObj* udmaObjPtr);
1328#endif
1329
1330#if (STD_ON == SPI_REGISTER_READBACK_API)
1360FUNC(Std_ReturnType, SPI_CODE) Spi_RegisterReadback(
1361 Spi_HWUnitType HWUnit,
1362 P2VAR(Spi_RegisterReadbackType, AUTOMATIC, SPI_APPL_DATA) RegRbPtr);
1363#endif /* #if (STD_ON == SPI_REGISTER_READBACK_API) */
1364
1365#if (STD_ON == SPI_SAFETY_API)
1384FUNC(Std_ReturnType, SPI_CODE) Spi_dataOverflowUnderflowIntrEnable(
1385 Spi_HWUnitType HWUnit, uint32 intFlags );
1386
1406FUNC(Std_ReturnType, SPI_CODE) Spi_dataOverflowUnderflowIntrDisable(
1407 Spi_HWUnitType HWUnit, uint32 intFlags);
1408
1429 Spi_HWUnitType HWUnit, uint32 intFlags);
1430
1450FUNC(Std_ReturnType, SPI_CODE) Spi_dataOverflowUnderflowIntrStatusClear(
1451 Spi_HWUnitType HWUnit, uint32 intFlags);
1452
1453#endif /* #if (STD_ON == SPI_SAFETY_API) */
1454
1455#ifdef __cplusplus
1456}
1457#endif
1458
1459#endif /* #ifndef SPI_H_ */
1460
1461/* @} */
This file contains generated pre compile configuration file for SPI MCAL driver.
Spi_CsModeType
SPI Chip Select Mode.
Definition Spi.h:573
uint8 Spi_SequenceType
Specifies the identification (ID) for a sequence of jobs.
Definition Spi.h:234
Spi_DataDelayType
Spi_DataDelayType defines the number of interface clock cycles between CS toggling and first or last ...
Definition Spi.h:585
uint16 Spi_NumberOfDataType
Type for defining the number of data elements of the type Spi_DataBufferType to send and / or receive...
Definition Spi.h:219
Spi_HwUnitResultType
This type defines a range of specific HW unit status for SPI Handler/Driver.
Definition Spi.h:451
Spi_StatusType Spi_GetHWUnitStatus(Spi_HWUnitType HWUnit)
This service returns the status of the specified SPI Hardware microcontroller peripheral.
Std_ReturnType Spi_WriteIB(Spi_ChannelType Channel, const Spi_DataBufferType *DataBufferPtr)
Service for writing one or more data to an IB SPI Handler/Driver Channel specified by parameter.
Spi_SeqResultType Spi_GetSequenceResult(Spi_SequenceType Sequence)
This service returns the last transmission result of the specified Sequence.
Std_ReturnType Spi_dataOverflowUnderflowIntrStatusClear(Spi_HWUnitType HWUnit, uint32 intFlags)
This function status clear Under/Overflow Interupts of the hardware unit and returns the status.
uint16 Spi_JobType
Specifies the identification (ID) for a Job.
Definition Spi.h:229
Spi_LevelType
Type for SPI Chip Select Polarity and Clock Idle Level.
Definition Spi.h:493
void Spi_Cancel(Spi_SequenceType Sequence)
Service cancels the specified on-going sequence transmission.
Spi_JobResultType Spi_GetJobResult(Spi_JobType Job)
This service returns the last transmission result of the specified Job.
Spi_JobResultType
This type defines a range of specific Jobs status for SPI Handler/Driver.
Definition Spi.h:413
Std_ReturnType Spi_dataOverflowUnderflowIntrDisable(Spi_HWUnitType HWUnit, uint32 intFlags)
This function Disable Under/Overflow Interupts of the hardware unit and returns the status.
Std_ReturnType Spi_SetupEB(Spi_ChannelType Channel, const Spi_DataBufferType *SrcDataBufferPtr, Spi_DataBufferType *DesDataBufferPtr, Spi_NumberOfDataType Length)
Service to setup the buffers and the length of data for the EB SPI Handler/Driver Channel specified.
Std_ReturnType Spi_RegisterReadback(Spi_HWUnitType HWUnit, Spi_RegisterReadbackType *RegRbPtr)
This function reads the important registers of the hardware unit and returns the value in the structu...
Spi_DataLineReceiveType
Spi_DataLineReceiveType defines the lines selected for reception.
Definition Spi.h:600
void(* Spi_CacheWb)(uint8 *BufPtr, uint16 LenByte)
Cache write-back function.
Definition Spi.h:652
Spi_ClkMode
SPI Clock Mode - sets the clock polarity and phase. Note: These values are a direct register mapping....
Definition Spi.h:520
Spi_DataLineTransmitType
Spi_DataLineTransmitType defines the lines selected for transmission.
Definition Spi.h:611
Std_ReturnType Spi_SetAsyncMode(Spi_AsyncModeType Mode)
Service to set the asynchronous mechanism mode for SPI busses handled asynchronously.
Std_ReturnType Spi_DeInit(void)
Service for SPI de-initialization.
Std_ReturnType Spi_GetDmaHandle(struct Udma_DrvObj *udmaObjPtr)
Service for getting DMA handle in SPI.
Spi_CsPinType
SPI Chip Select Pin.
Definition Spi.h:504
Spi_TxRxMode
SPI TX/RX Mode.
Definition Spi.h:544
Spi_TransferType
Word transfer order - MSB first or LSB first.
Definition Spi.h:482
Std_ReturnType Spi_SyncTransmit(Spi_SequenceType Sequence)
Service to transmit data on the SPI bus.
void(* Spi_CacheWbInv)(uint8 *BufPtr, uint16 LenByte)
Cache write-back invalidate function.
Definition Spi.h:642
uint8 Spi_HWUnitType
Specifies the identification (ID) for a SPI Hardware micro controller peripheral (unit)
Definition Spi.h:242
Spi_JobPriorityType
SPI Job Priority.
Definition Spi.h:558
Spi_StatusType Spi_GetStatus(void)
Service returns the SPI Handler/Driver software module status.
Mcspi_IrqStatusType
Irq status and std return type.
Definition Spi.h:626
Mcspi_IrqStatusType Spi_dataOverflowUnderflowIntrGetStatus(Spi_HWUnitType HWUnit, uint32 intFlags)
This function status Under/Overflow Interupts of the hardware unit and returns the status.
Std_ReturnType Spi_AsyncTransmit(Spi_SequenceType Sequence)
Service to transmit data on the SPI bus.
Spi_SeqResultType
This type defines a range of specific Sequences status for SPI Handler/Driver.
Definition Spi.h:434
void Spi_GetVersionInfo(Std_VersionInfoType *versioninfo)
This service returns the version information of this module.
Spi_StatusType
This type defines a range of specific status for SPI Handler/Driver.
Definition Spi.h:396
uint8 Spi_DataBufferType
Type of application data buffer elements.
Definition Spi.h:211
void Spi_MainFunction_Handling(void)
This function polls the SPI interrupts linked to HW Units allocated to the transmission of SPI sequen...
Std_ReturnType Spi_ReadIB(Spi_ChannelType Channel, Spi_DataBufferType *DataBufferPointer)
Service for reading synchronously one or more data from an IB SPI Handler/Driver Channel specified by...
Std_ReturnType Spi_dataOverflowUnderflowIntrEnable(Spi_HWUnitType HWUnit, uint32 intFlags)
This function Enable Under/Overflow Interupts of the hardware unit and returns the status.
void(* Spi_CacheInv)(uint8 *BufPtr, uint16 LenByte)
Cache invalidate function.
Definition Spi.h:662
uint8 Spi_ChannelType
Specifies the identification (ID) for a Channel.
Definition Spi.h:224
void Spi_Init(const Spi_ConfigType *CfgPtr)
Service for SPI initialization.
Spi_AsyncModeType
Specifies the asynchronous mechanism mode for SPI busses handled asynchronously in LEVEL 2.
Definition Spi.h:468
Spi_NumberOfDataType maxBufLength
Definition Spi.h:680
uint32 mcspiHlHwInfo
Definition Spi.h:895
#define SPI_MAX_CHANNELS
Maximum channels across all jobs/sequence/hwunit.
Definition Spi_Cfg.h:197
uint32 dmaTxChIntrNum
Definition Spi.h:795
uint32 mcspiSyst
Definition Spi.h:903
uint32 mcspiSysConfig
Definition Spi.h:907
uint32 mcspiCh1config
Definition Spi.h:910
#define SPI_MAX_JOBS_PER_SEQ
Maximum jobs allowed per sequence.
Definition Spi_Cfg.h:194
uint32 mcspiSysStatus
Definition Spi.h:901
uint32 mcspiRev
Definition Spi.h:899
#define SPI_MAX_EXT_DEV
Maximum external device cfg.
Definition Spi_Cfg.h:214
#define SPI_MAX_JOBS
Maximum jobs across all sequence/hwunit.
Definition Spi_Cfg.h:200
Spi_DataLineTransmitType transmissionLineEnable
Definition Spi.h:732
uint32 defaultTxData
Definition Spi.h:678
uint8 maxExtDevCfg
Definition Spi.h:821
uint8 seqInterruptible
Definition Spi.h:775
Spi_JobType jobId
Definition Spi.h:865
Spi_DataDelayType csIdleTime
Definition Spi.h:707
uint32 mcspiCh0config
Definition Spi.h:909
uint8 maxJobs
Definition Spi.h:812
#define SPI_MAX_HW_UNIT
Maximum HW unit - This should match the sum for the below units ISR which are ON.
Definition Spi_Cfg.h:209
Spi_TxRxMode txRxMode
Definition Spi.h:723
uint8 maxSeq
Definition Spi.h:815
Spi_TransferType transferType
Definition Spi.h:690
Spi_CacheWbInv cacheWbInv
Definition Spi.h:830
#define SPI_MAX_CHANNELS_PER_JOB
Maximum channels allowed per job.
Definition Spi_Cfg.h:191
boolean enabledmaMode
Definition Spi.h:793
Spi_HWUnitType hwUnitId
Definition Spi.h:791
uint32 mcspiCh3config
Definition Spi.h:912
Spi_JobPriorityType jobPriority
Definition Spi.h:754
uint32 clkDivider
Definition Spi.h:715
uint32 udmaInstId
Definition Spi.h:824
uint32 mcspiHlSysConfig
Definition Spi.h:897
Spi_DataLineReceiveType receptionLineEnable
Definition Spi.h:730
uint32 jobPerSeq
Definition Spi.h:779
uint8 externalDeviceCfgId
Definition Spi.h:869
uint32 mcspiCh2config
Definition Spi.h:911
Spi_McspiExternalDeviceConfigType mcspi
Definition Spi.h:741
uint8 dataWidth
Definition Spi.h:675
uint16 startBitEnable
Definition Spi.h:725
uint8 maxHwUnit
Definition Spi.h:818
uint32 channelPerJob
Definition Spi.h:760
Spi_CsPinType csPin
Definition Spi.h:867
uint16 csEnable
Definition Spi.h:700
Spi_CacheWb cacheWb
Definition Spi.h:832
uint8 maxChannels
Definition Spi.h:809
Spi_ChannelType channelId
Definition Spi.h:853
Spi_ClkMode clkMode
Definition Spi.h:721
Spi_SeqEndNotifyType Spi_SequenceEndNotification
Definition Spi.h:777
uint32 mcspiHlRev
Definition Spi.h:893
Spi_JobEndNotifyType Spi_JobEndNotification
Definition Spi.h:758
uint32 mcspiIrqenable
Definition Spi.h:914
Spi_LevelType csPolarity
Definition Spi.h:705
Spi_CsModeType csMode
Definition Spi.h:702
uint8 channelBufType
Definition Spi.h:673
#define SPI_MAX_SEQ
Maximum sequence across all hwunit.
Definition Spi_Cfg.h:203
uint32 mcspiModulctrl
Definition Spi.h:905
Spi_LevelType startBitLevel
Definition Spi.h:728
Spi_CacheInv cacheInv
Definition Spi.h:834
uint32 dmaRxChIntrNum
Definition Spi.h:797
Spi_SequenceType seqId
Definition Spi.h:879
Spi_HWUnitType hwUnitId
Definition Spi.h:756
@ SPI_CONTINUOUS
Definition Spi.h:576
@ SPI_SINGLE
Definition Spi.h:574
@ SPI_DATADELAY_0
Definition Spi.h:586
@ SPI_DATADELAY_2
Definition Spi.h:590
@ SPI_DATADELAY_1
Definition Spi.h:588
@ SPI_DATADELAY_3
Definition Spi.h:592
@ SPI_HW_UNIT_FAILED
Definition Spi.h:456
@ SPI_HW_UNIT_OK
Definition Spi.h:452
@ SPI_HW_UNIT_PENDING
Definition Spi.h:454
@ SPI_LOW
Definition Spi.h:494
@ SPI_HIGH
Definition Spi.h:496
@ SPI_JOB_PENDING
Definition Spi.h:416
@ SPI_JOB_FAILED
Definition Spi.h:419
@ SPI_JOB_OK
Definition Spi.h:414
@ SPI_JOB_QUEUED
Definition Spi.h:421
@ DATA_LINE_1_RECEPTION
Definition Spi.h:603
@ DATA_LINE_0_RECEPTION
Definition Spi.h:601
@ SPI_CLK_MODE_2
Definition Spi.h:525
@ SPI_CLK_MODE_3
Definition Spi.h:527
@ SPI_CLK_MODE_0
Definition Spi.h:521
@ SPI_CLK_MODE_1
Definition Spi.h:523
@ DATA_LINE_BOTH_TRANSMISSION
Definition Spi.h:618
@ DATA_LINE_1_TRANSMISSION
Definition Spi.h:616
@ DATA_LINE_0_TRANSMISSION
Definition Spi.h:614
@ DATA_LINE_NO_TRANSMISSION
Definition Spi.h:612
@ SPI_CS1
Definition Spi.h:507
@ SPI_CS0
Definition Spi.h:505
@ SPI_CS3
Definition Spi.h:511
@ SPI_CS2
Definition Spi.h:509
@ SPI_TX_RX_MODE_BOTH
Definition Spi.h:545
@ SPI_TX_RX_MODE_TX_ONLY
Definition Spi.h:547
@ SPI_MSB
Definition Spi.h:483
@ SPI_LSB
Definition Spi.h:485
@ SPI_JOB_PRIORITY_1
Definition Spi.h:561
@ SPI_JOB_PRIORITY_2
Definition Spi.h:563
@ SPI_JOB_PRIORITY_0
Definition Spi.h:559
@ SPI_JOB_PRIORITY_3
Definition Spi.h:565
@ SPI_EVENT_PENDING
Definition Spi.h:629
@ SPI_STATUS_READ_FAIL
Definition Spi.h:631
@ SPI_NO_EVENT
Definition Spi.h:627
@ SPI_SEQ_CANCELLED
Definition Spi.h:442
@ SPI_SEQ_OK
Definition Spi.h:435
@ SPI_SEQ_FAILED
Definition Spi.h:440
@ SPI_SEQ_PENDING
Definition Spi.h:437
@ SPI_UNINIT
Definition Spi.h:397
@ SPI_IDLE
Definition Spi.h:399
@ SPI_BUSY
Definition Spi.h:401
@ SPI_INTERRUPT_MODE
Definition Spi.h:472
@ SPI_POLLING_MODE
Definition Spi.h:469
SPI channel config structure parameters Pre-Compile only.
Definition Spi.h:852
SPI Channel configuration structure.
Definition Spi.h:672
SPI config structure.
Definition Spi.h:808
SPI external device specific configuration structure .
Definition Spi.h:740
SPI Hardware unit configuration structure.
Definition Spi.h:790
SPI job config structure parameters Pre-Compile only.
Definition Spi.h:864
SPI Job configuration structure.
Definition Spi.h:753
SPI Job configuration structure specific to McSPI peripheral.
Definition Spi.h:699
SPI register readback structure.
Definition Spi.h:889
SPI sequence config structure parameters Pre-Compile only.
Definition Spi.h:878
SPI Sequence configuration structure.
Definition Spi.h:774