Introduction

This file contains generated pre compile configurations for CDD IPC MCAL driver.

Communication Channel ID & Configured Buffer sizes
#define	CddIpcConf_IpcComChanId_Cdd_IpcMcu20 (0U)

#define	CDD_IPC_RPMSG_OBJ_SIZE (256U)

#define	CDD_IPC_CH_0_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)

#define	CDD_IPC_MAX_CHANNEL_CFG (2U)

#define	IPC_VRING_BUFFER_SIZE (0x1C00000U)
	VRing Buffer Size required for all core combinations.

#define	IPC_MPU1_0 (0U)
	Core definitions.

#define	IPC_MCU1_0 (1U)

#define	IPC_MCU1_1 (2U)

#define	IPC_MCU2_0 (3U)

#define	IPC_MCU2_1 (4U)

#define	IPC_MCU3_0 (5U)

#define	IPC_MCU3_1 (6U)

#define	IPC_C66X_1 (7U)

#define	IPC_C66X_2 (8U)

#define	IPC_C7X_1 (9U)

#define	IPC_MPU1_1 (10U)

#define	IPC_MAX_PROCS (11U)

#define	CDD_IPC_CORE_ID_MAX (11U)
	IPC maximum possible core ID.

#define	IPC_MAILBOX_CLUSTER_CNT (12U)

#define	CDD_IPC_NEW_MSG_NTFY_FXN Cdd_IpcNewMessageNotify

#define	CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify

const uint32	IPC_Mailbox_BasePhyAddr [IPC_MAILBOX_CLUSTER_CNT]

Ipc_ProcInfo	g_Ipc_mp_procInfo [IPC_MAX_PROCS]
	Processor IDs to name mapping for all processor in Jacinto7.

Ipc_MailboxInfo	g_IPC_MailboxInfo [IPC_MAX_PROCS][IPC_MAX_PROCS]

const struct Cdd_IpcConfigType_s	CddIpcConfiguraions_PC

uint8	Cdd_IpcDrvVertIoObj [CDD_IPC_VERTIO_OBJECT_SIZE]
	Communication Channels configured.

void	Cdd_IpcNewMessageNotify (void)
	New Message notification function.

void	Cdd_IpcNewCtrlMessageNotify (uint32 remoteProcId)
	New Control Message notification function.

void	Cdd_IpcIrqMbxFromMcu_20 (void)
	A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is used determine presence of data from the remote core in the vring.

Macros
#define	CDD_IPC_PRE_COMPILE_VARIANT (STD_ON)
	Pre-Compile Build Variant flag. STD_ON for VariantPreCompile / STD_OFF for VariantPostBuild.

CDD Driver ISR category level
Defines for CDD Driver ISR ISR category level
#define	CDD_IPC_ISR_VOID (0x00U)
	void ISR type

#define	CDD_IPC_ISR_CAT1 (0x01U)
	Category 1 ISR type.

#define	CDD_IPC_ISR_CAT2 (0x02U)
	Category 2 ISR type.

#define	CDD_IPC_DEV_ERROR_DETECT (STD_ON)
	Enable/disable CDD Ipc dev detect error.

#define	CDD_IPC_ISR_TYPE (CDD_IPC_ISR_CAT1)
	ISR type.

Pre-Compile Switches for API Services
#define	CDD_IPC_VERSION_INFO_API (STD_ON)
	Enable/disable version info API.

#define	CDD_IPC_DEINIT_API (STD_ON)
	Enable/disable De Initialization API.

#define	CDD_IPC_ANNOUNCE_API (STD_ON)
	Enable/disable Service Announcement API.

#define	CDD_IPC_REGISTER_READBACK_API (STD_ON)
	Enable/disable Critical Register read back API.

#define	CDD_IPC_SAFETY_DIAGNOSTIC_API (STD_ON)
	Enable/disable safety diagnostics API.

#define	CDD_IPC_IS_INIT_DONE_API (STD_ON)
	Enable/disable Cdd_IpcIsInitDone API.

#define	CDD_IPC_GET_MAX_MSG_SIZE_API (STD_ON)
	Enable/disable Cdd_IpcGetMaxMsgSize API.

Dependency configurations
#define	CDD_IPC_OS_COUNTER_ID ((CounterType)OsCounter_0)
	Counter ID for counter used to count wait ticks.

Cdd Ipc DEM Error codes to report
Pre-compile switches for enabling/disabling DEM events
#define	CDD_IPC_E_HARDWARE_ERROR (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
	Hardware failed.

CORE Names
#define	CDD_IPC_CORE_MCU1_0 (1U)

#define	CDD_IPC_CORE_MCU1_1 (2U)

#define	CDD_IPC_CORE_MCU2_0 (3U)

#define	CDD_IPC_CORE_MCU2_1 (4U)

#define	CDD_IPC_CORE_MCU3_0 (5U)

#define	CDD_IPC_CORE_MCU3_1 (6U)

#define	CDD_IPC_CORE_C66X_1 (7U)

#define	CDD_IPC_CORE_C66X_2 (8U)

#define	CDD_IPC_CORE_C7X_1 (9U)

#define	CDD_IPC_CORE_MAX_PROCS (11U)

#define	CDD_IPC_OWN_CORE_ID (CDD_IPC_CORE_MCU1_0)
	Used core identifiers.

#define	CDD_IPC_REMOTE_CORE_MCU2_0_USED

VirtIO Object
#define	CDD_IPC_VERTIO_OBJECT_SIZE (0x1000U)

Introduction

Communication Channel ID & Configured Buffer sizes

Macros