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Spi.h
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1/*
2*
3* Copyright (c) 2024 Texas Instruments Incorporated
4*
5* All rights reserved not granted herein.
6*
7* Limited License.
8*
9* Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
10* license under copyrights and patents it now or hereafter owns or controls to make,
11* have made, use, import, offer to sell and sell ("Utilize") this software subject to the
12* terms herein. With respect to the foregoing patent license, such license is granted
13* solely to the extent that any such patent is necessary to Utilize the software alone.
14* The patent license shall not apply to any combinations which include this software,
15* other than combinations with devices manufactured by or for TI ("TI Devices").
16* No hardware patent is licensed hereunder.
17*
18* Redistributions must preserve existing copyright notices and reproduce this license
19* (including the above copyright notice and the disclaimer and (if applicable) source
20* code license limitations below) in the documentation and/or other materials provided
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22*
23* Redistribution and use in binary form, without modification, are permitted provided
24* that the following conditions are met:
25*
26* * No reverse engineering, decompilation, or disassembly of this software is
27* permitted with respect to any software provided in binary form.
28*
29* * any redistribution and use are licensed by TI for use only with TI Devices.
30*
31* * Nothing shall obligate TI to provide you with source code for the software
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33*
34* If software source code is provided to you, modification and redistribution of the
35* source code are permitted provided that the following conditions are met:
36*
37* * any redistribution and use of the source code, including any resulting derivative
38* works, are licensed by TI for use only with TI Devices.
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40* * any redistribution and use of any object code compiled from the source code
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43* Neither the name of Texas Instruments Incorporated nor the names of its suppliers
44*
45* may be used to endorse or promote products derived from this software without
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47*
48* DISCLAIMER.
49*
50* THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
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60*
61*/
62
116/*
117 * Below are the global design requirements which are met by this SPI handler
118 * driver which can't be mapped to a particular source ID
119 */
120/*
121 * Design: MCAL-6422,MCAL-6412,MCAL-6690,MCAL-6487,MCAL-6429,MCAL-6683,MCAL-6384,MCAL-6478,MCAL-6383,MCAL-6593,MCAL-6573,MCAL-6381,MCAL-6492,MCAL-6610,MCAL-6658,MCAL-6451,MCAL-6449,MCAL-6448,MCAL-6581,MCAL-6710,MCAL-6527,MCAL-6642,MCAL-6458,MCAL-6544
122 */
123
124/*
125 * Below are the SPI's module environment design requirements which can't be mapped
126 * to this driver.
127 */
128/*
129 * Design: MCAL-6719,MCAL-6486,MCAL-6415,MCAL-6685,MCAL-6421,MCAL-6390,MCAL-6608,MCAL-6670,MCAL-6643
130 */
131
132#ifndef SPI_H_
133#define SPI_H_
134
135/* ========================================================================== */
136/* Include Files */
137/* ========================================================================== */
138#include "Std_Types.h"
139#include "Spi_Cfg.h"
140#if defined (SOC_J721E) || defined (SOC_J7200) || defined (SOC_J721S2) || defined (SOC_J784S4) || defined (SOC_J742S2)
141#include <ti/drv/udma/udma.h>
142#endif
143#include "Spi/mcspi_hw/V0/mcspi.h"
144
145#ifdef __cplusplus
146extern "C"
147{
148#endif
149
150/* ========================================================================== */
151/* Macros & Typedefs */
152/* ========================================================================== */
153
161#define SPI_SW_MAJOR_VERSION (9U)
163#define SPI_SW_MINOR_VERSION (1U)
165#define SPI_SW_PATCH_VERSION (0U)
166/* @} */
167
175#define SPI_AR_RELEASE_MAJOR_VERSION (4U)
177#define SPI_AR_RELEASE_MINOR_VERSION (3U)
179#define SPI_AR_RELEASE_REVISION_VERSION (1U)
180/* @} */
181
187#define SPI_VENDOR_ID ((uint16) 44U)
189#define SPI_MODULE_ID ((uint16) 83U)
191#define SPI_INSTANCE_ID ((uint8) 0U)
192/* @} */
193
199#define SPI_IB (0U)
201#define SPI_EB (1U)
203#define SPI_IB_EB (2U)
204/* @} */
205
206
208/*
209 * Design: MCAL-6691,MCAL-6394,MCAL-6615
210 */
211typedef uint8 Spi_DataBufferType;
216/*
217 * Design: MCAL-6625,MCAL-6669
218 */
219typedef uint16 Spi_NumberOfDataType;
221/*
222 * Design: MCAL-6528,MCAL-6493,MCAL-6687
223 */
224typedef uint8 Spi_ChannelType;
226/*
227 * Design: MCAL-6457,MCAL-6689,MCAL-6728
228 */
229typedef uint16 Spi_JobType;
231/*
232 * Design: MCAL-6639,MCAL-6505,MCAL-6729
233 */
234typedef uint8 Spi_SequenceType;
239/*
240 * Design: MCAL-6655,MCAL-6682,MCAL-6707
241 */
242typedef uint8 Spi_HWUnitType;
243
250#ifndef SPI_E_PARAM_CHANNEL
252#define SPI_E_PARAM_CHANNEL ((uint8) 0x0AU)
253#endif
254#ifndef SPI_E_PARAM_JOB
256#define SPI_E_PARAM_JOB ((uint8) 0x0BU)
257#endif
258#ifndef SPI_E_PARAM_SEQ
260#define SPI_E_PARAM_SEQ ((uint8) 0x0CU)
261#endif
262#ifndef SPI_E_PARAM_LENGTH
264#define SPI_E_PARAM_LENGTH ((uint8) 0x0DU)
265#endif
266#ifndef SPI_E_PARAM_UNIT
268#define SPI_E_PARAM_UNIT ((uint8) 0x0EU)
269#endif
270#ifndef SPI_E_PARAM_POINTER
272#define SPI_E_PARAM_POINTER ((uint8) 0x10U)
273#endif
274#ifndef SPI_E_UNINIT
276#define SPI_E_UNINIT ((uint8) 0x1AU)
277#endif
278#ifndef SPI_E_SEQ_PENDING
280#define SPI_E_SEQ_PENDING ((uint8) 0x2AU)
281#endif
282#ifndef SPI_E_SEQ_IN_PROCESS
284#define SPI_E_SEQ_IN_PROCESS ((uint8) 0x3AU)
285#endif
286#ifndef SPI_E_ALREADY_INITIALIZED
291#define SPI_E_ALREADY_INITIALIZED ((uint8) 0x4AU)
292#endif
293#ifndef SPI_E_SEQUENCE_NOT_OK
295#define SPI_E_SEQUENCE_NOT_OK ((uint8) 0x5AU)
296#endif
297
298/* @} */
299
308#define SPI_SID_INIT ((uint8) 0x00U)
310#define SPI_SID_DEINIT ((uint8) 0x01U)
312#define SPI_SID_WRITE_IB ((uint8) 0x02U)
314#define SPI_SID_ASYNC_TRANSMIT ((uint8) 0x03U)
316#define SPI_SID_READ_IB ((uint8) 0x04U)
318#define SPI_SID_SETUP_EB ((uint8) 0x05U)
320#define SPI_SID_GET_STATUS ((uint8) 0x06U)
322#define SPI_SID_GET_JOB_RESULT ((uint8) 0x07U)
324#define SPI_SID_GET_SEQ_RESULT ((uint8) 0x08U)
326#define SPI_SID_GET_VERSION_INFO ((uint8) 0x09U)
328#define SPI_SID_SYNC_TRANSMIT ((uint8) 0x0AU)
330#define SPI_SID_GET_HW_UNIT_STATUS ((uint8) 0x0BU)
332#define SPI_SID_CANCEL ((uint8) 0x0CU)
334#define SPI_SID_SET_ASYNC_MODE ((uint8) 0x0DU)
336#define SPI_SID_MAINFUNCTION_HANDLING ((uint8) 0x10U)
337/* @} */
338
345/*
346 * Design: MCAL-6699
347 */
348#define SPI_MCSPI_FCLK (48000000U)
349
358#define SPI_CFG_ID_0 (0x01U)
361#define SPI_CFG_ID_1 (0x02U)
363#define SPI_CFG_ID_2 (0x04U)
365#define SPI_CFG_ID_3 (0x08U)
367#define SPI_CFG_ID_4 (0x10U)
369#define SPI_CFG_ID_5 (0x20U)
371#define SPI_CFG_ID_6 (0x40U)
373#define SPI_CFG_ID_7 (0x80U)
374/* @} */
375
376/* ========================================================================== */
377/* Structures and Enums */
378/* ========================================================================== */
379
388/*
389 * Design: MCAL-6531,MCAL-6648,MCAL-6537,MCAL-6574
390 */
391typedef enum
392{
393 SPI_UNINIT = 0U,
395 SPI_IDLE = 1U,
397 SPI_BUSY = 2U
400
405/*
406 * Design: MCAL-6703,MCAL-6425,MCAL-6430
407 */
408typedef enum
409{
410 SPI_JOB_OK = 0U,
412 SPI_JOB_PENDING = 1U,
415 SPI_JOB_FAILED = 2U,
417 SPI_JOB_QUEUED = 3U
421
426/*
427 * Design: MCAL-6512,MCAL-6607,MCAL-6686
428 */
429typedef enum
430{
431 SPI_SEQ_OK = 0U,
433 SPI_SEQ_PENDING = 1U,
436 SPI_SEQ_FAILED = 2U,
441
446typedef enum
447{
448 SPI_HW_UNIT_OK = 0U,
455
460/*
461 * Design: MCAL-6502,MCAL-6659,MCAL-6420,MCAL-6475,MCAL-6419,MCAL-6517,MCAL-6641
462 */
463typedef enum
464{
465 SPI_POLLING_MODE = 0U,
473
477typedef enum
478{
479 SPI_MSB = 0U,
481 SPI_LSB = 1U
484
488typedef enum
489{
490 SPI_LOW = STD_LOW,
495
499typedef enum
500{
501 SPI_CS0 = 0U,
503 SPI_CS1,
505 SPI_CS2,
507 SPI_CS3
510
515typedef enum
516{
517 SPI_CLK_MODE_0 = 0x00U,
519 SPI_CLK_MODE_1 = 0x01U,
521 SPI_CLK_MODE_2 = 0x02U,
523 SPI_CLK_MODE_3 = 0x03U,
526
539typedef enum
540{
541 SPI_TX_RX_MODE_BOTH = 0x00U,
546
550/*
551 * Design: MCAL-6597
552 */
564
568typedef enum
569{
570 SPI_SINGLE = 0U,
572 SPI_CONTINUOUS = 1U
575
580typedef enum
581{
582 SPI_DATADELAY_0 = 0U,
584 SPI_DATADELAY_1 = 1U,
586 SPI_DATADELAY_2 = 2U,
588 SPI_DATADELAY_3 = 3U,
591
595typedef enum
596{
602
617
621typedef enum
622{
623 SPI_NO_EVENT = 0U,
630
638typedef void (*Spi_CacheWbInv)(uint8 *BufPtr,
639 uint16 LenByte);
640
648typedef void (*Spi_CacheWb)(uint8 *BufPtr,
649 uint16 LenByte);
650
658typedef void (*Spi_CacheInv)(uint8 *BufPtr,
659 uint16 LenByte);
660
664/*
665 * Design: MCAL-6529,MCAL-6519,MCAL-6649,MCAL-6716,MCAL-6619
666 */
690
731
741
745/*
746 * Design: MCAL-6692,MCAL-6437,MCAL-6684,MCAL-6522,MCAL-6572,MCAL-6406,MCAL-6632,MCAL-6476
747 */
762
766/*
767 * Design: MCAL-6496,MCAL-6536,MCAL-6742,MCAL-6413
768 */
781
796
800/*
801 * Design: MCAL-6570,MCAL-6423,MCAL-6588,MCAL-6485,MCAL-6733
802 */
843
847typedef struct Spi_ChannelConfigType_PC_s
848{
852
853/*
854 * Design: MCAL-6717,MCAL-6650
855 */
859typedef struct Spi_JobConfigType_PC_s
860{
869
873typedef struct Spi_SeqConfigType_PC_s
874{
878
879#if (STD_ON == SPI_REGISTER_READBACK_API)
884typedef struct
885{
886 /*
887 * McSPI related registers
888 */
895 uint32 mcspiRev;
899 uint32 mcspiSyst;
913#endif /* #if (STD_ON == SPI_REGISTER_READBACK_API) */
914/* @} */
915/* @} */
916/* ========================================================================== */
917/* Function Declarations */
918/* ========================================================================== */
919
937FUNC(void, SPI_CODE) Spi_Init(
938 P2CONST(Spi_ConfigType, AUTOMATIC, SPI_CONFIG_DATA) CfgPtr);
939
960FUNC(Std_ReturnType, SPI_CODE) Spi_DeInit(void);
961
979FUNC(Spi_StatusType, SPI_CODE) Spi_GetStatus(void);
980
1001
1024 Spi_SequenceType Sequence);
1025
1026#if (STD_ON == SPI_VERSION_INFO_API)
1047FUNC(void, SPI_CODE) Spi_GetVersionInfo(
1048 P2VAR(Std_VersionInfoType, AUTOMATIC, SPI_APPL_DATA) versioninfo);
1049#endif /* #if (STD_ON == SPI_VERSION_INFO_API) */
1050
1051#if (STD_ON == SPI_HW_STATUS_API)
1074#endif /* #if (STD_ON == SPI_HW_STATUS_API) */
1075
1076#if ((SPI_CHANNELBUFFERS == SPI_IB) || (SPI_CHANNELBUFFERS == SPI_IB_EB))
1105FUNC(Std_ReturnType, SPI_CODE) Spi_WriteIB(
1106 Spi_ChannelType Channel,
1107 P2CONST(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) DataBufferPtr);
1108
1134FUNC(Std_ReturnType, SPI_CODE) Spi_ReadIB(
1135 Spi_ChannelType Channel,
1136 P2VAR(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) DataBufferPointer);
1137#endif /* #if SPI_IB || SPI_IB_EB */
1138
1139#if ((SPI_CHANNELBUFFERS == SPI_EB) || (SPI_CHANNELBUFFERS == SPI_IB_EB))
1172FUNC(Std_ReturnType, SPI_CODE) Spi_SetupEB(
1173 Spi_ChannelType Channel,
1174 P2CONST(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) SrcDataBufferPtr,
1175 P2VAR(Spi_DataBufferType, AUTOMATIC, SPI_APPL_DATA) DesDataBufferPtr,
1176 Spi_NumberOfDataType Length);
1177#endif /* #if ((SPI_CHANNELBUFFERS == SPI_EB) || (SPI_CHANNELBUFFERS ==
1178 *SPI_IB_EB)) */
1179
1180#if ((SPI_SCALEABILITY == SPI_LEVEL_1) || (SPI_SCALEABILITY == \
1181 SPI_LEVEL_2))
1202FUNC(Std_ReturnType, SPI_CODE) Spi_AsyncTransmit(Spi_SequenceType Sequence);
1203#endif /* #if ((SPI_SCALEABILITY == SPI_LEVEL_1) ||
1204 *(SPI_SCALEABILITY == SPI_LEVEL_2)) */
1205
1206#if (STD_ON == SPI_CANCEL_API)
1225FUNC(void, SPI_CODE) Spi_Cancel(Spi_SequenceType Sequence);
1226#endif /* #if (STD_ON == SPI_CANCEL_API) */
1227
1228#if ((SPI_SCALEABILITY == SPI_LEVEL_0) || (SPI_SCALEABILITY == \
1229 SPI_LEVEL_2))
1250FUNC(Std_ReturnType, SPI_CODE) Spi_SyncTransmit(Spi_SequenceType Sequence);
1251#endif /* #if ((SPI_SCALEABILITY == SPI_LEVEL_0) ||
1252 *(SPI_SCALEABILITY == SPI_LEVEL_2)) */
1253
1254#if (SPI_SCALEABILITY == SPI_LEVEL_2)
1277FUNC(Std_ReturnType, SPI_CODE) Spi_SetAsyncMode(Spi_AsyncModeType Mode);
1278#endif /* #if (SPI_SCALEABILITY == SPI_LEVEL_2) */
1279
1302FUNC(void, SPI_CODE) Spi_MainFunction_Handling(void);
1303
1304#if (STD_ON == SPI_REGISTER_READBACK_API)
1334FUNC(Std_ReturnType, SPI_CODE) Spi_RegisterReadback(
1335 Spi_HWUnitType HWUnit,
1336 P2VAR(Spi_RegisterReadbackType, AUTOMATIC, SPI_APPL_DATA) RegRbPtr);
1337#endif /* #if (STD_ON == SPI_REGISTER_READBACK_API) */
1338
1339#if (STD_ON == SPI_SAFETY_API)
1358FUNC(Std_ReturnType, SPI_CODE) Spi_dataOverflowUnderflowIntrEnable(
1359 Spi_HWUnitType HWUnit, uint32 intFlags );
1360
1380FUNC(Std_ReturnType, SPI_CODE) Spi_dataOverflowUnderflowIntrDisable(
1381 Spi_HWUnitType HWUnit, uint32 intFlags);
1382
1403 Spi_HWUnitType HWUnit, uint32 intFlags);
1404
1424FUNC(Std_ReturnType, SPI_CODE) Spi_dataOverflowUnderflowIntrStatusClear(
1425 Spi_HWUnitType HWUnit, uint32 intFlags);
1426
1427#endif /* #if (STD_ON == SPI_SAFETY_API) */
1428
1429#ifdef __cplusplus
1430}
1431#endif
1432
1433#endif /* #ifndef SPI_H_ */
1434
1435/* @} */
This file contains generated pre compile configuration file for SPI MCAL driver.
Spi_CsModeType
SPI Chip Select Mode.
Definition Spi.h:569
uint8 Spi_SequenceType
Specifies the identification (ID) for a sequence of jobs.
Definition Spi.h:234
Spi_DataDelayType
Spi_DataDelayType defines the number of interface clock cycles between CS toggling and first or last ...
Definition Spi.h:581
uint16 Spi_NumberOfDataType
Type for defining the number of data elements of the type Spi_DataBufferType to send and / or receive...
Definition Spi.h:219
Spi_HwUnitResultType
This type defines a range of specific HW unit status for SPI Handler/Driver.
Definition Spi.h:447
Spi_StatusType Spi_GetHWUnitStatus(Spi_HWUnitType HWUnit)
This service returns the status of the specified SPI Hardware microcontroller peripheral.
Std_ReturnType Spi_WriteIB(Spi_ChannelType Channel, const Spi_DataBufferType *DataBufferPtr)
Service for writing one or more data to an IB SPI Handler/Driver Channel specified by parameter.
Spi_SeqResultType Spi_GetSequenceResult(Spi_SequenceType Sequence)
This service returns the last transmission result of the specified Sequence.
Std_ReturnType Spi_dataOverflowUnderflowIntrStatusClear(Spi_HWUnitType HWUnit, uint32 intFlags)
This function status clear Under/Overflow Interupts of the hardware unit and returns the status.
uint16 Spi_JobType
Specifies the identification (ID) for a Job.
Definition Spi.h:229
Spi_LevelType
Type for SPI Chip Select Polarity and Clock Idle Level.
Definition Spi.h:489
void Spi_Cancel(Spi_SequenceType Sequence)
Service cancels the specified on-going sequence transmission.
Spi_JobResultType Spi_GetJobResult(Spi_JobType Job)
This service returns the last transmission result of the specified Job.
Spi_JobResultType
This type defines a range of specific Jobs status for SPI Handler/Driver.
Definition Spi.h:409
Std_ReturnType Spi_dataOverflowUnderflowIntrDisable(Spi_HWUnitType HWUnit, uint32 intFlags)
This function Disable Under/Overflow Interupts of the hardware unit and returns the status.
Std_ReturnType Spi_SetupEB(Spi_ChannelType Channel, const Spi_DataBufferType *SrcDataBufferPtr, Spi_DataBufferType *DesDataBufferPtr, Spi_NumberOfDataType Length)
Service to setup the buffers and the length of data for the EB SPI Handler/Driver Channel specified.
Std_ReturnType Spi_RegisterReadback(Spi_HWUnitType HWUnit, Spi_RegisterReadbackType *RegRbPtr)
This function reads the important registers of the hardware unit and returns the value in the structu...
Spi_DataLineReceiveType
Spi_DataLineReceiveType defines the lines selected for reception.
Definition Spi.h:596
void(* Spi_CacheWb)(uint8 *BufPtr, uint16 LenByte)
Cache write-back function.
Definition Spi.h:648
Spi_ClkMode
SPI Clock Mode - sets the clock polarity and phase. Note: These values are a direct register mapping....
Definition Spi.h:516
Spi_DataLineTransmitType
Spi_DataLineTransmitType defines the lines selected for transmission.
Definition Spi.h:607
Std_ReturnType Spi_SetAsyncMode(Spi_AsyncModeType Mode)
Service to set the asynchronous mechanism mode for SPI busses handled asynchronously.
Std_ReturnType Spi_DeInit(void)
Service for SPI de-initialization.
Spi_CsPinType
SPI Chip Select Pin.
Definition Spi.h:500
Spi_TxRxMode
SPI TX/RX Mode.
Definition Spi.h:540
Spi_TransferType
Word transfer order - MSB first or LSB first.
Definition Spi.h:478
Std_ReturnType Spi_SyncTransmit(Spi_SequenceType Sequence)
Service to transmit data on the SPI bus.
void(* Spi_CacheWbInv)(uint8 *BufPtr, uint16 LenByte)
Cache write-back invalidate function.
Definition Spi.h:638
uint8 Spi_HWUnitType
Specifies the identification (ID) for a SPI Hardware micro controller peripheral (unit)
Definition Spi.h:242
Spi_JobPriorityType
SPI Job Priority.
Definition Spi.h:554
Spi_StatusType Spi_GetStatus(void)
Service returns the SPI Handler/Driver software module status.
Mcspi_IrqStatusType
Irq status and std return type.
Definition Spi.h:622
Mcspi_IrqStatusType Spi_dataOverflowUnderflowIntrGetStatus(Spi_HWUnitType HWUnit, uint32 intFlags)
This function status Under/Overflow Interupts of the hardware unit and returns the status.
Std_ReturnType Spi_AsyncTransmit(Spi_SequenceType Sequence)
Service to transmit data on the SPI bus.
Spi_SeqResultType
This type defines a range of specific Sequences status for SPI Handler/Driver.
Definition Spi.h:430
void Spi_GetVersionInfo(Std_VersionInfoType *versioninfo)
This service returns the version information of this module.
Spi_StatusType
This type defines a range of specific status for SPI Handler/Driver.
Definition Spi.h:392
uint8 Spi_DataBufferType
Type of application data buffer elements.
Definition Spi.h:211
void Spi_MainFunction_Handling(void)
This function polls the SPI interrupts linked to HW Units allocated to the transmission of SPI sequen...
Std_ReturnType Spi_ReadIB(Spi_ChannelType Channel, Spi_DataBufferType *DataBufferPointer)
Service for reading synchronously one or more data from an IB SPI Handler/Driver Channel specified by...
Std_ReturnType Spi_dataOverflowUnderflowIntrEnable(Spi_HWUnitType HWUnit, uint32 intFlags)
This function Enable Under/Overflow Interupts of the hardware unit and returns the status.
void(* Spi_CacheInv)(uint8 *BufPtr, uint16 LenByte)
Cache invalidate function.
Definition Spi.h:658
uint8 Spi_ChannelType
Specifies the identification (ID) for a Channel.
Definition Spi.h:224
void Spi_Init(const Spi_ConfigType *CfgPtr)
Service for SPI initialization.
Spi_AsyncModeType
Specifies the asynchronous mechanism mode for SPI busses handled asynchronously in LEVEL 2.
Definition Spi.h:464
Spi_NumberOfDataType maxBufLength
Definition Spi.h:676
uint32 mcspiHlHwInfo
Definition Spi.h:891
#define SPI_MAX_CHANNELS
Maximum channels across all jobs/sequence/hwunit.
Definition Spi_Cfg.h:197
uint32 dmaTxChIntrNum
Definition Spi.h:791
uint32 mcspiSyst
Definition Spi.h:899
uint32 mcspiSysConfig
Definition Spi.h:903
uint32 mcspiCh1config
Definition Spi.h:906
#define SPI_MAX_JOBS_PER_SEQ
Maximum jobs allowed per sequence.
Definition Spi_Cfg.h:194
uint32 mcspiSysStatus
Definition Spi.h:897
uint32 mcspiRev
Definition Spi.h:895
#define SPI_MAX_EXT_DEV
Maximum external device cfg.
Definition Spi_Cfg.h:214
#define SPI_MAX_JOBS
Maximum jobs across all sequence/hwunit.
Definition Spi_Cfg.h:200
Spi_DataLineTransmitType transmissionLineEnable
Definition Spi.h:728
uint32 defaultTxData
Definition Spi.h:674
uint8 maxExtDevCfg
Definition Spi.h:817
uint8 seqInterruptible
Definition Spi.h:771
Spi_JobType jobId
Definition Spi.h:861
Spi_DataDelayType csIdleTime
Definition Spi.h:703
uint32 mcspiCh0config
Definition Spi.h:905
uint8 maxJobs
Definition Spi.h:808
#define SPI_MAX_HW_UNIT
Maximum HW unit - This should match the sum for the below units ISR which are ON.
Definition Spi_Cfg.h:209
Spi_TxRxMode txRxMode
Definition Spi.h:719
uint8 maxSeq
Definition Spi.h:811
Spi_TransferType transferType
Definition Spi.h:686
Spi_CacheWbInv cacheWbInv
Definition Spi.h:826
#define SPI_MAX_CHANNELS_PER_JOB
Maximum channels allowed per job.
Definition Spi_Cfg.h:191
boolean enabledmaMode
Definition Spi.h:789
Spi_HWUnitType hwUnitId
Definition Spi.h:787
uint32 mcspiCh3config
Definition Spi.h:908
Spi_JobPriorityType jobPriority
Definition Spi.h:750
uint32 clkDivider
Definition Spi.h:711
uint32 udmaInstId
Definition Spi.h:820
uint32 mcspiHlSysConfig
Definition Spi.h:893
Spi_DataLineReceiveType receptionLineEnable
Definition Spi.h:726
uint32 jobPerSeq
Definition Spi.h:775
uint8 externalDeviceCfgId
Definition Spi.h:865
uint32 mcspiCh2config
Definition Spi.h:907
Spi_McspiExternalDeviceConfigType mcspi
Definition Spi.h:737
uint8 dataWidth
Definition Spi.h:671
uint16 startBitEnable
Definition Spi.h:721
uint8 maxHwUnit
Definition Spi.h:814
uint32 channelPerJob
Definition Spi.h:756
Spi_CsPinType csPin
Definition Spi.h:863
uint16 csEnable
Definition Spi.h:696
Spi_CacheWb cacheWb
Definition Spi.h:828
uint8 maxChannels
Definition Spi.h:805
Spi_ChannelType channelId
Definition Spi.h:849
Spi_ClkMode clkMode
Definition Spi.h:717
Spi_SeqEndNotifyType Spi_SequenceEndNotification
Definition Spi.h:773
uint32 mcspiHlRev
Definition Spi.h:889
Spi_JobEndNotifyType Spi_JobEndNotification
Definition Spi.h:754
uint32 mcspiIrqenable
Definition Spi.h:910
Spi_LevelType csPolarity
Definition Spi.h:701
Spi_CsModeType csMode
Definition Spi.h:698
uint8 channelBufType
Definition Spi.h:669
#define SPI_MAX_SEQ
Maximum sequence across all hwunit.
Definition Spi_Cfg.h:203
uint32 mcspiModulctrl
Definition Spi.h:901
Spi_LevelType startBitLevel
Definition Spi.h:724
Spi_CacheInv cacheInv
Definition Spi.h:830
uint32 dmaRxChIntrNum
Definition Spi.h:793
Spi_SequenceType seqId
Definition Spi.h:875
Spi_HWUnitType hwUnitId
Definition Spi.h:752
@ SPI_CONTINUOUS
Definition Spi.h:572
@ SPI_SINGLE
Definition Spi.h:570
@ SPI_DATADELAY_0
Definition Spi.h:582
@ SPI_DATADELAY_2
Definition Spi.h:586
@ SPI_DATADELAY_1
Definition Spi.h:584
@ SPI_DATADELAY_3
Definition Spi.h:588
@ SPI_HW_UNIT_FAILED
Definition Spi.h:452
@ SPI_HW_UNIT_OK
Definition Spi.h:448
@ SPI_HW_UNIT_PENDING
Definition Spi.h:450
@ SPI_LOW
Definition Spi.h:490
@ SPI_HIGH
Definition Spi.h:492
@ SPI_JOB_PENDING
Definition Spi.h:412
@ SPI_JOB_FAILED
Definition Spi.h:415
@ SPI_JOB_OK
Definition Spi.h:410
@ SPI_JOB_QUEUED
Definition Spi.h:417
@ DATA_LINE_1_RECEPTION
Definition Spi.h:599
@ DATA_LINE_0_RECEPTION
Definition Spi.h:597
@ SPI_CLK_MODE_2
Definition Spi.h:521
@ SPI_CLK_MODE_3
Definition Spi.h:523
@ SPI_CLK_MODE_0
Definition Spi.h:517
@ SPI_CLK_MODE_1
Definition Spi.h:519
@ DATA_LINE_BOTH_TRANSMISSION
Definition Spi.h:614
@ DATA_LINE_1_TRANSMISSION
Definition Spi.h:612
@ DATA_LINE_0_TRANSMISSION
Definition Spi.h:610
@ DATA_LINE_NO_TRANSMISSION
Definition Spi.h:608
@ SPI_CS1
Definition Spi.h:503
@ SPI_CS0
Definition Spi.h:501
@ SPI_CS3
Definition Spi.h:507
@ SPI_CS2
Definition Spi.h:505
@ SPI_TX_RX_MODE_BOTH
Definition Spi.h:541
@ SPI_TX_RX_MODE_TX_ONLY
Definition Spi.h:543
@ SPI_MSB
Definition Spi.h:479
@ SPI_LSB
Definition Spi.h:481
@ SPI_JOB_PRIORITY_1
Definition Spi.h:557
@ SPI_JOB_PRIORITY_2
Definition Spi.h:559
@ SPI_JOB_PRIORITY_0
Definition Spi.h:555
@ SPI_JOB_PRIORITY_3
Definition Spi.h:561
@ SPI_EVENT_PENDING
Definition Spi.h:625
@ SPI_STATUS_READ_FAIL
Definition Spi.h:627
@ SPI_NO_EVENT
Definition Spi.h:623
@ SPI_SEQ_CANCELLED
Definition Spi.h:438
@ SPI_SEQ_OK
Definition Spi.h:431
@ SPI_SEQ_FAILED
Definition Spi.h:436
@ SPI_SEQ_PENDING
Definition Spi.h:433
@ SPI_UNINIT
Definition Spi.h:393
@ SPI_IDLE
Definition Spi.h:395
@ SPI_BUSY
Definition Spi.h:397
@ SPI_INTERRUPT_MODE
Definition Spi.h:468
@ SPI_POLLING_MODE
Definition Spi.h:465
SPI channel config structure parameters Pre-Compile only.
Definition Spi.h:848
SPI Channel configuration structure.
Definition Spi.h:668
SPI config structure.
Definition Spi.h:804
SPI external device specific configuration structure .
Definition Spi.h:736
SPI Hardware unit configuration structure.
Definition Spi.h:786
SPI job config structure parameters Pre-Compile only.
Definition Spi.h:860
SPI Job configuration structure.
Definition Spi.h:749
SPI Job configuration structure specific to McSPI peripheral.
Definition Spi.h:695
SPI register readback structure.
Definition Spi.h:885
SPI sequence config structure parameters Pre-Compile only.
Definition Spi.h:874
SPI Sequence configuration structure.
Definition Spi.h:770