94 #include "Eth_LL_Types.h" 95 #include "Udma_Types.h" 105 #define ETH_VERSION_INFO_API (STD_ON) 108 #define ETH_GLOBALTIMESUPPORT_API (STD_ON) 111 #define ETH_DEV_ERROR_DETECT (STD_ON) 114 #define ETH_GET_COUNTER_VALUES_API (STD_ON) 117 #define ETH_GET_RX_STATS_API (STD_ON) 120 #define ETH_GET_TX_STATS_API (STD_ON) 123 #define ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON) 126 #define ETH_ZERO_COPY_API (STD_OFF) 129 #define ETH_HEADER_ACCESS_API (STD_OFF) 132 #define ETH_TRAFFIC_SHAPING_API (STD_OFF) 135 #define ETH_GET_COUNTER_STATE_API (STD_OFF) 139 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF) 142 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF) 145 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF) 148 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF) 151 #define ETH_REGISTER_READBACK_API (STD_ON) 154 #define ETH_ENABLE_MII_API (STD_ON) 157 #define ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON) 160 #define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF) 163 #define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF) 166 #define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF) 169 #define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF) 172 #define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF) 175 #define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF) 178 #define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF) 181 #define ETH_VIRTUALMAC_ADD_UNICAST_MACADDR_API (STD_OFF) 184 #define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF) 187 #define ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF) 190 #define ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF) 193 #define ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF) 197 #define ETH_ETHIF_CBK_HEADER "EthIf_Cbk.h" 200 #define ETH_ISR_TYPE (ETH_ISR_CAT2) 202 #define ETH_OS_COUNTER_ID ((CounterType)OsCounter_0) 204 #define ETH_OS_COUNTER_FREQ (1000000000U) 207 #define ETH_INVALID_RING_ID (0xFFFFU) 209 #define ETH_INVALID_EVENT_ID (0xFFFFU) 211 #define ETH_INVALID_CHAN_ID (0xFFFFU) 213 #define ETH_INVALID_FLOW_ID (0xFFFFU) 215 #define ETH_INVALID_IRQ_ID (0xFFFFU) 217 #define ETH_DEM_NO_EVENT (0xFFFFU) 220 #define ETH_VIRTUALMAC_SUPPORT (STD_OFF) 222 #define ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U) 230 #define EthConf_EthCtrlConfig_EthConfig_0 (0U) 231 #define ETH_CTRL_ID_0 (0U) 238 #define ETH_PRE_COMPILE_VARIANT (STD_ON) 239 #define ETH_LINK_TIME_VARIANT (STD_OFF) 240 #define ETH_POST_BUILD_VARIANT (STD_OFF) 246 #define ETH_CTRL_ID_MAX (1U) 255 #define NOP1 asm (" NOP ") 256 #define NOP5 NOP1; NOP1; NOP1; NOP1; NOP1 257 #define NOP10 NOP5; NOP5 258 #define NOP20 NOP10; NOP10 259 #define NOP30 NOP20; NOP10 260 #define NOP40 NOP30; NOP10 261 #define NOP50 NOP40; NOP10 262 #define NOP100 NOP50; NOP50 263 #define NOP200 NOP100; NOP100 264 #define NOP300 NOP200; NOP100 265 #define NOP400 NOP300; NOP100 266 #define NOP500 NOP400; NOP100 273 #define ETH_DMA_IR_SUPPORT (STD_ON) 274 #define ETH_DMA_CQ_RING_SUPPORT (STD_ON) 275 #define ETH_DMA_TEARDOWN_SUPPORT (STD_ON) 276 #define ETH_DMA_PROXY_SUPPORT (STD_ON) 277 #define ETH_DMA_RX_CH_SPERATE (STD_OFF) 284 #define UDMA_DEVICE_ID_RING (235U) 285 #define UDMA_DEVICE_ID_UDMA (236U) 286 #define UDMA_DEVICE_ID_PSIL (232U) 287 #define UDMA_DEVICE_ID_IA (233U) 288 #define UDMA_DEVICE_ID_IR (237U) 289 #define UDMA_DEVICE_ID_CORE (250U) 290 #define UDMA_DEVICE_ID_PROXY (234U) 297 #define UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U) 298 #define UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U) 299 #define UDMA_SOURCE_THREAD_OFFSET (0x6000U) 300 #define UDMA_DEST_THREAD_OFFSET (0xe000U) 307 #define ETH_DMA_TX_BASE_REG (0x2aa00000U) 308 #define ETH_DMA_RX_BASE_REG (0x2a800000U) 309 #define ETH_DMA_RINGRT_BASE (0x2b800000U) 310 #define ETH_DMA_RINGCFG_BASE (0x28440000U) 311 #define ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U) 318 #define ETH_DMA_TXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) 319 #define ETH_DMA_TXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) 320 #define ETH_DMA_RXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U)) 321 #define ETH_DMA_RXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U)) 323 #define ETH_DMA_RINGRT_RING_FDB(RING) (0x00000010U + ((RING) * 0x1000U)) 324 #define ETH_DMA_RINGRT_RING_FOCC(RING) (0x00000018U + ((RING) * 0x1000U)) 325 #define ETH_DMA_RINGRT_RING_RDB(RING) (0x00000010U + ((RING) * 0x1000U)) 326 #define ETH_DMA_RINGRT_RING_ROCC(RING) (0x00000018U + ((RING) * 0x1000U)) 327 #define ETH_DMA_RINGRT_RING_HWOCC(RING) (0x00000020U + ((RING) * 0x1000U)) 328 #define ETH_DMA_RINGCFG_RING_SIZE(RING) (0x00000048U + ((RING) * 0x100U)) 330 #define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U)) 331 #define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U)) 332 #define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U)) 333 #define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U)) 334 #define ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U)) 336 #define Eth_GetRingFDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum))) 337 #define Eth_GetRingFOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum))) 338 #define Eth_GetRingRDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum))) 339 #define Eth_GetRingROCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum))) 340 #define Eth_GetRingHWOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_HWOCC((RingNum))) 341 #define Eth_GetRingSizeReg(RingNum) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum))) 343 #define Eth_GetTxChannelCtlRegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId))) 344 #define Eth_GetTxChannelPeer8RegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId))) 345 #define Eth_GetRxChannelCtlRegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId))) 346 #define Eth_GetRxChannelPeer8RegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId))) 348 #define CSL_PROXY0_TARGET0_DATA_BASE (0x2a500000U) 349 #define CSL_PROXY_TARGET0_PROXY_CTL(PROXY) (CSL_PROXY0_TARGET0_DATA_BASE + 0x00000000U + ((PROXY)*0x1000U)) 350 #define CSL_PROXY_TARGET0_PROXY_DATA_FIELD(PROXY) (CSL_PROXY0_TARGET0_DATA_BASE + 0x00000200U + ((PROXY)*0x1000U)) 356 #define UDMA_WAIT_TEARDOWN_COUNTER (10000u) 362 #define ETH_RX_MTU_HOST_PORT_LENGTH (1522U) 370 #define Eth_Cpsw_GetPhyMacRegAddr() ( 0x40f00200U ) 371 #define Eth_Cpsw_GetAleRegAddr() ( 0x4603e000U ) 372 #define Eth_Cpsw_GetCptsRegAddr() ( 0x4603d000U ) 373 #define Eth_Cpsw_GetMdioRegAddr() ( 0x46000f00U ) 374 #define Eth_Cpsw_GetCtrlRegAddr() ( 0x46020000U ) 375 #define Eth_Cpsw_GetCppiClockFreq() ( 333333333U ) 377 #define Eth_Cpsw_GetCptsRefClockFreq() ( 1U ) 378 #define Eth_Cpsw_GetMdioBusClockFreq() ( 2200000U ) 379 #define Eth_Cpsw_GetMdioOpMode() ( ETH_MDIO_OPMODE_MANUAL ) 380 #define Eth_Cpsw_GetMdioEnableInterrupt() ( TRUE ) 387 #define Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex) ( ETH_DEM_NO_EVENT ) 388 #define Eth_GetDem_E_LATECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) 389 #define Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) 390 #define Eth_GetDem_E_SINGLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT ) 391 #define Eth_GetDem_E_ALIGNMENT(CtrlIndex) ( ETH_DEM_NO_EVENT ) 392 #define Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) 393 #define Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT ) 394 #define Eth_GetDem_E_CRC(CtrlIndex) ( ETH_DEM_NO_EVENT ) 395 #define Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex) ( ETH_DEM_NO_EVENT ) 396 #define Eth_GetDem_E_ACCESS(CtrlIndex) ( ETH_DEM_NO_EVENT ) 397 #define Eth_GetDem_E_TX_INTERNAL(CtrlIndex) ( ETH_DEM_NO_EVENT ) 404 #define Eth_IsVirtualMacModeEnable(CtrlIndex) ( FALSE ) 405 #define Eth_GetTxChannelThreadOffset(CtrlIndex) ( 0xf000U ) 406 #define Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex) ( 0xFFFFU ) 407 #define Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex) ( FALSE ) 408 #define Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex) ( (Eth_RpcCmdComplete)NULL_PTR ) 409 #define Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex) ( (Eth_RpcFwRegistered)NULL_PTR ) 410 #define Eth_VirtMacGetRemoteVirtPort(CtrlIndex) ( ETHREMOTECFG_SWITCH_PORT_1 ) 412 #define Eth_VirtMacGetDmaTxChannelPairAll(CtrlIdx) ( (EthVirtMacDmaTxChannelPair)NULL_PTR ) 413 #define Eth_VirtMacGetDmaTxChannelUnpairAll(CtrlIdx) ( (EthVirtMacDmaTxChannelUnpair)NULL_PTR ) 414 #define Eth_VirtMacGetDmaFlowCfgAll(CtrlIdx) ( (EthVirtMacDmaFLowCfg)NULL_PTR ) 415 #define Eth_VirtMacGetDmaFlowResetAll(CtrlIdx) ( (EthVirtMacDmaFLowReset)NULL_PTR ) 417 #define Eth_GetTxEnableInterrupt(CtrlIndex) ( TRUE ) 418 #define Eth_GetRxEnableInterrupt(CtrlIndex) ( TRUE ) 419 #define Eth_GetEnetType(CtrlIndex) ( ETH_ENETTYPE_CPSW2G ) 420 #define Eth_GetMacPortNum(CtrlIndex) ( ETH_PORT_MAC_PORT_1 ) 421 #define Eth_GetMacAddressHigh(CtrlIndex) ( 0xaabbccddU ) 422 #define Eth_GetMacAddressLow(CtrlIndex) ( 0xeeffU ) 423 #define Eth_UseDefaultMacAddress(CtrlIndex) ( TRUE ) 424 #define Eth_GetMiiConnectionType(CtrlIndex) ( ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND ) 425 #define Eth_GetLoopBackMode(CtrlIndex) ( FALSE ) 426 #define Eth_GetHardwareLoopTimeout(CtrlIndex) ( 32000U ) 427 #define Eth_IsPacketMemCacheable(CtrlIndex) ( TRUE ) 428 #define Eth_IsRingMemCacheable(CtrlIndex) ( TRUE ) 429 #define Eth_IsDescMemCacheable(CtrlIndex) ( TRUE ) 431 #define Eth_GetRxMtuLength(CtrlIndex) ( 1522U ) 432 #define Eth_GetTxChanStartNum(CtrlIndex) ( 30U ) 433 #define Eth_GetRxChanStartNum(CtrlIndex) ( 30U ) 434 #define Eth_GetEgressFifoTotalNum(CtrlIndex) ( 1U ) 435 #define Eth_GetIngressFifoTotalNum(CtrlIndex) ( 1U ) 436 #define Eth_GetRingTotalNum(CtrlIndex) ( 6U ) 437 #define Eth_GetTxChanTotalNum(CtrlIndex) ( 1U ) 438 #define Eth_GetRxChanTotalNum(CtrlIndex) ( 1U ) 439 #define Eth_GetFlowTotalNumber(CtrlIndex) ( 1U ) 440 #define Eth_GetEventTotalNum(CtrlIndex) ( 2U ) 441 #define Eth_GetRingEventTotalNum(CtrlIndex) ( 2U ) 442 #define Eth_GetTxDmaThresholdNum(CtrlIndex) ( 1U ) 443 #define Eth_GetRxDmaThresholdNum(CtrlIndex) ( 1U ) 445 #define Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx) ( 16U ) 446 #define Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) 448 #define Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx) ( 16U ) 449 #define Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U ) 451 #define Eth_GetEgressFifoPriorityAsignment(CtrlIndex, Prio) ( 0U ) 452 #define Eth_GetIngressFifoPriorirtyAsignment(CtrlIndex, Prio) ( 0U ) 454 #define Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] ) 455 #define Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo ) 456 #define Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] ) 457 #define Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Egress_Queue_0 ) 458 #define Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] ) 459 #define Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val ) 461 #define Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] ) 462 #define Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo ) 463 #define Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] ) 464 #define Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Ingress_Queue_0 ) 465 #define Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] ) 466 #define Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val ) 468 #define Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx) ( 0U ) 469 #define Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx) ( 2U ) 470 #define Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx) ( 1U ) 471 #define Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx) ( 3U ) 473 #define Eth_GetTxChanId(CtrlIndex, ChIdx) ( 30U ) 474 #define Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 4U ) 475 #define Eth_GetTxChanDepth(CtrlIndex, ChIdx) ( 128U ) 477 #define Eth_GetRxChanId(CtrlIndex, ChIdx) ( 30U ) 478 #define Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 5U ) 479 #define Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx) ( 1U ) 480 #define Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx) ( 60U ) 482 #define Eth_GetFlowId(CtrlIndex, FlowIdx) ( 60U ) 483 #define Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx) ( 1U ) 484 #define Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx) ( 3U ) 486 #define Eth_GetDynRingElemAddress(CtrlIndex, RingIdx) ( &Eth_RingDyn_Ctrl_0[(RingIdx)] ) 488 #define Eth_GetRingHwId(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].hwId ) 489 #define Eth_GetRingTotalElemNum(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].size ) 490 #define Eth_GetRingPriority(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].priority ) 491 #define Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr ) 493 #define Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx ) 494 #define Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent ) 495 #define Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum ) 496 #define Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx ) 497 #define Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset ) 499 #define Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum ) 500 #define Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum ) 501 #define Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum ) 502 #define Eth_GetTxEventCoreIntrNum(CtrlIndex) ( 80U ) 503 #define Eth_GetRxEventCoreIntrNum(CtrlIndex) ( 81U ) 505 #define Eth_GetHwTimerTotalNum(CtrlIndex) ( 0U ) 506 #define Eth_GetHwTimerId(CtrlIndex, Index) ( 0xFFU ) 507 #define Eth_GetHwTimerCounter(CtrlIndex, Index) ( 0xFFU ) 508 #define Eth_GetHwTimerBaseAddr(CtrlIndex, Index) ( 0xFFFFFFFFU ) 510 #define Eth_GetHwTimerDynRunningState(CtrlIndex, Index) ( FALSE ) 511 #define Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val) ( (void)(CtrlIndex) ) 513 #define Eth_GetRxIrqPacingEnable(CtrlIndex) ( FALSE ) 514 #define Eth_GetTxIrqPacingEnable(CtrlIndex) ( FALSE ) 516 #define Eth_GetRxHwTimerIdx(CtrlIndex) ( 255U ) 517 #define Eth_GetTxHwTimerIdx(CtrlIndex) ( 255U ) 518 #define Eth_GetIrqPacingEnable(CtrlIndex) ( (Eth_GetTxIrqPacingEnable(CtrlIndex) == TRUE) || (Eth_GetRxIrqPacingEnable(CtrlIndex) == TRUE) ) 520 #define Eth_GetProxyTotalNum(CtrlIndex) ( 1U ) 521 #define Eth_GetProxyThreadNum(CtrlIndex, ProxyIdx) ( 9U ) 522 #define Eth_GetProxyTargetRingNum(CtrlIndex, ProxyIdx) ( 0U ) 523 #define Eth_GetRingProxyIdx(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].proxyIdx ) 524 #define Eth_GetRingMode(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].ringMode ) 526 #define Eth_GetDmaRingCfg(CtrlIdx) ( (Eth_DmaRingCfg)&AppUtils_EthRingCfg ) 604 typedef enum EthRemoteCfg_VirtPort_e
708 typedef struct Eth_CpswConfigType_s
736 typedef struct Eth_Udma_RingCfgType_s
756 typedef struct Eth_Udma_ProxyCfgType_s
768 typedef struct Eth_Udma_EventCfgType_s
782 typedef struct Eth_Udma_RingEventCfgType_s
800 typedef struct Eth_FifoRingMapCfgType_s
812 typedef struct Eth_ChannelCfgType_s
824 typedef struct Eth_FlowCfgType_s
838 typedef struct Eth_ChannelFlowCfgType_s
850 typedef struct Eth_FifoHandleType_s
872 typedef struct Eth_Udma_CfgType_s
944 typedef struct Eth_VirtualMacConfigType_s
970 typedef struct Eth_HwTimerConfigType_s
982 typedef struct Eth_ControlerConfigType_s
1052 typedef struct Eth_ConfigType_s
1062 #define ETH_START_SEC_CONST_UNSPECIFIED 1063 #include "Eth_MemMap.h" 1070 #define ETH_STOP_SEC_CONST_UNSPECIFIED 1071 #include "Eth_MemMap.h" 1073 #define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128 1074 #include "Eth_MemMap.h" 1076 extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U];
1077 extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[16U];
1079 extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_BufferMem_0[24576U];
1080 extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_Descriptor_0[16U];
1082 #define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128 1083 #include "Eth_MemMap.h" 1085 #define ETH_START_SEC_VAR_NO_INIT_8 1086 #include "Eth_MemMap.h" 1088 extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[16U];
1089 extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_BufferState_0[16U];
1091 #define ETH_STOP_SEC_VAR_NO_INIT_8 1092 #include "Eth_MemMap.h" 1094 #define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED 1095 #include "Eth_MemMap.h" 1097 extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U];
1098 extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_Queue_0[1U];
1100 extern VAR(Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U];
1101 #define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED 1102 #include "Eth_MemMap.h" 1111 #define ETH_START_SEC_CODE 1112 #include "Eth_MemMap.h" 1119 #define ETH_STOP_SEC_CODE 1120 #include "Eth_MemMap.h" 1132 #define Eth_GetMdioWriteLowBaseNsec() do { \ 1136 #define Eth_GetMdioWriteHighBaseNsec() do { \ 1139 #define Eth_GetMdioReadLowBaseNsec() do { \ 1143 #define Eth_GetMdioReadHighBaseNsec() do { \ 1154 #define Eth_GetMdioWriteLowDelayNsec(CtrlIdx) do { \ 1159 #define Eth_GetMdioWriteHighDelayNsec(CtrlIdx) do { \ 1163 #define Eth_GetMdioReadLowDelayNsec(CtrlIdx) do { \ 1168 #define Eth_GetMdioReadHighDelayNsec(CtrlIdx) do { \ uint32 IrIntrNum
Definition: Eth_Cfg.h:774
Definition: Eth_Cfg.h:597
Eth_PortType macPort
Definition: Eth_Cfg.h:988
uint32 size
Definition: Eth_Cfg.h:742
boolean loopback
Definition: Eth_Cfg.h:998
Eth_MdioOperModeType mdioOpMode
Definition: Eth_Cfg.h:726
Eth controller configuration type Configuration related to Eth controller configuration.
Definition: Eth_Cfg.h:982
uint64 * memPtr
Definition: Eth_Cfg.h:738
Definition: Eth_Cfg.h:679
Std_ReturnType(* EthVirtMacDmaFLowReset)(uint8 ctrlIdx)
Definition: Eth_Cfg.h:567
void(* Eth_MdioDelayNsecFunc)(void)
Pair PSIL TX channel function pointer.
Definition: Eth_Cfg.h:555
Eth_FifoHandleType * ingressFifoCfgPtr
Definition: Eth_Cfg.h:884
uint8 totalTxChanNum
Definition: Eth_Cfg.h:922
uint8 virtBitNum
Definition: Eth_Cfg.h:788
Definition: Eth_Cfg.h:665
Definition: Eth_Cfg.h:622
Eth_ChannelCfgType * rxChanCfgPtr
Definition: Eth_Cfg.h:896
Definition: Eth_Cfg.h:610
Eth_Udma_CfgType * dmaCfgPtr
Definition: Eth_Cfg.h:1032
boolean enableRxIrq
Definition: Eth_Cfg.h:1004
Eth_FifoRingMapCfgType * ingressFifoRingMapCfgPtr
Definition: Eth_Cfg.h:888
boolean * hwTimerDynPtr
Definition: Eth_Cfg.h:1036
Eth_Udma_EventCfgType * eventCfgPtr
Definition: Eth_Cfg.h:874
Eth_Udma_ProxyCfgType * proxyCfgPtr
Definition: Eth_Cfg.h:902
uint32 ringMode
Definition: Eth_Cfg.h:748
Definition: Eth_Cfg.h:591
Eth_CpswConfigType * cpswCfg
Definition: Eth_Cfg.h:1030
boolean pollRecvMsgInEthMain
Definition: Eth_Cfg.h:952
Definition: Eth_Cfg.h:581
void(* Eth_RpcCmdComplete)(uint8 CtrlIdx, uint8 sid, sint32 status)
Application callback to indicate Rpc dispatch command completion.
Definition: Eth_Cfg.h:541
uint32 coreIntrNum
Definition: Eth_Cfg.h:770
uint32 ctrlIdx
Definition: Eth_Cfg.h:984
Eth_VirtualMacConfigType * virtualMacCfg
Definition: Eth_Cfg.h:1026
Definition: Eth_Cfg.h:628
Definition: Eth_Cfg.h:585
uint32 hwId
Definition: Eth_Cfg.h:740
const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U]
uint8 * ingressFifoPrioAssignCfgPtr
Definition: Eth_Cfg.h:892
Std_ReturnType(* EthVirtMacDmaFLowCfg)(uint8 ctrlIdx)
Flow reset function pointer.
Definition: Eth_Cfg.h:564
Std_ReturnType(* EthVirtMacDmaTxChannelUnPair)(uint8 ctrlIdx)
Flow config function pointer.
Definition: Eth_Cfg.h:561
Eth flow configuration type Configuration related to flow.
Definition: Eth_Cfg.h:824
Definition: Eth_Cfg.h:640
Definition: Eth_Cfg.h:634
Eth_EnetType enetType
Definition: Eth_Cfg.h:986
Eth configuration type Configuration data of all controller.
Definition: Eth_Cfg.h:1052
Definition: Eth_Cfg.h:613
Eth_PortType
Port identifier.
Definition: Eth_Cfg.h:575
uint8 cqRingIdx
Definition: Eth_Cfg.h:802
Definition: Eth_Cfg.h:681
uint32 hwTimerCounter
Definition: Eth_Cfg.h:974
uint16 txCoreIrq
Definition: Eth_Cfg.h:930
Eth_MdioDelayNsecFunc mdioWriteLowDelayNsec
Definition: Eth_Cfg.h:1038
uint8 * bufferState
Definition: Eth_Cfg.h:858
boolean useDefaultMac
Definition: Eth_Cfg.h:994
Eth driver hardware timer configuration data Configuration related to hardware timer.
Definition: Eth_Cfg.h:970
Definition: Eth_Cfg.h:643
Eth_DescType * descPtr
Definition: Eth_Cfg.h:854
Definition: Eth_Cfg.h:583
uint8 txHwTimerIdx
Definition: Eth_Cfg.h:1024
Eth driver virtual mac configuration data Configuration related to virtual MAC configuration.
Definition: Eth_Cfg.h:944
uint16 demEventNum
Definition: Eth_Cfg.h:1014
Definition: Eth_Cfg.h:685
Eth_FifoRingMapCfgType * egressFifoRingMapCfgPtr
Definition: Eth_Cfg.h:886
Definition: Eth_Cfg.h:661
uint32 ctrlAddr
Definition: Eth_Cfg.h:718
uint16 rxCoreIrq
Definition: Eth_Cfg.h:932
const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U]
uint16 * demEventCfg
Definition: Eth_Cfg.h:1028
uint16 totalProxyNum
Definition: Eth_Cfg.h:928
#define ETH_CTRL_ID_MAX
Eth max controller ID.
Definition: Eth_Cfg.h:246
uint16 startTxNum
Definition: Eth_Cfg.h:904
uint8 totalRingEventNum
Definition: Eth_Cfg.h:912
Eth_Udma_RingCfgType * ringCfgPtr
Definition: Eth_Cfg.h:876
Eth_QueueType * queuePtr
Definition: Eth_Cfg.h:856
Eth_RpcFwRegistered fwRegisteredCb
Definition: Eth_Cfg.h:954
Eth_MacConnectionType
Type/Speed/Duplex connection type.
Definition: Eth_Cfg.h:655
uint32 cptsAddr
Definition: Eth_Cfg.h:714
Std_ReturnType(* Eth_DmaRingCfg)(uint8 ctrlIdx, uint8 ringIdx)
Mdio delay in nsec function pointer.
Definition: Eth_Cfg.h:552
uint8 cqRingIdx
Definition: Eth_Cfg.h:826
uint8 totalHwTimerNum
Definition: Eth_Cfg.h:1020
uint16 rxMtuLength
Definition: Eth_Cfg.h:934
boolean isDescMemCacheable
Definition: Eth_Cfg.h:1010
Eth_ChannelFlowCfgType * rxChanFlowCfgPtr
Definition: Eth_Cfg.h:898
Eth Udma event Configurations type Configuration related to Udma event.
Definition: Eth_Cfg.h:768
boolean isRingMemCacheable
Definition: Eth_Cfg.h:1008
Eth_Udma_RingDynType * ringDynPtr
Definition: Eth_Cfg.h:878
Definition: Eth_Cfg.h:589
uint16 startRxNum
Definition: Eth_Cfg.h:906
uint8 * fifoBufferPtr
Definition: Eth_Cfg.h:852
Eth_HwTimerConfigType * hwTimerCfgPtr
Definition: Eth_Cfg.h:1034
uint32 srcOffset
Definition: Eth_Cfg.h:792
uint32 proxyId
Definition: Eth_Cfg.h:758
Eth_MdioOperModeType
MDIO operating mode.
Definition: Eth_Cfg.h:696
uint16 elemSize
Definition: Eth_Cfg.h:862
boolean isPacketMemCacheable
Definition: Eth_Cfg.h:1006
Eth_ChannelCfgType * txChanCfgPtr
Definition: Eth_Cfg.h:894
uint32 targetNumRingId
Definition: Eth_Cfg.h:760
boolean enableRxIrqPacing
Definition: Eth_Cfg.h:1016
uint32 ethfwRpcComChId
Definition: Eth_Cfg.h:946
Eth Fifo ring map configuration type Configuration related to fifo map to ring.
Definition: Eth_Cfg.h:800
uint16 flowId
Definition: Eth_Cfg.h:830
Definition: Eth_Cfg.h:607
Definition: Eth_Cfg.h:577
Eth_MdioDelayNsecFunc mdioWriteHighDelayNsec
Definition: Eth_Cfg.h:1040
Definition: Eth_Cfg.h:700
uint8 totalFlowNum
Definition: Eth_Cfg.h:926
const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U]
Definition: Eth_Cfg.h:646
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U]
Definition: Eth_Cfg.h:663
Std_ReturnType AppUtils_EthRingCfg(uint8 ctrlIdx, uint8 Id)
Definition: Eth_Cfg.h:637
Eth channel flow configuration type Configuration related to channel flow.
Definition: Eth_Cfg.h:838
boolean enableVirtualMac
Definition: Eth_Cfg.h:1012
Std_ReturnType(* EthVirtMacDmaTxChannelPair)(uint8 ctrlIdx)
Unpair PSIL TX channel function pointer.
Definition: Eth_Cfg.h:558
uint32 globalEvent
Definition: Eth_Cfg.h:790
uint8 rxHwTimerIdx
Definition: Eth_Cfg.h:1022
Definition: Eth_Cfg.h:657
uint32 cptsRefClockFreq
Definition: Eth_Cfg.h:728
uint8 rxThresholdNum
Definition: Eth_Cfg.h:916
uint32 macAddrLow
Definition: Eth_Cfg.h:992
Eth Fifo configuration type Configuration related to Fifo.
Definition: Eth_Cfg.h:850
Definition: Eth_Cfg.h:616
uint8 ringIdx
Definition: Eth_Cfg.h:784
boolean enableMdioIrq
Definition: Eth_Cfg.h:722
Definition: Eth_Cfg.h:631
Eth_MacConnectionType connType
Definition: Eth_Cfg.h:996
Eth_EnetType
Enet Cpsw Type identifier.
Definition: Eth_Cfg.h:677
Eth Cpsw Configurations type Configuration related to Cpsw data.
Definition: Eth_Cfg.h:708
uint32 cppiClockFreqHz
Definition: Eth_Cfg.h:720
uint8 totalRxChanNum
Definition: Eth_Cfg.h:924
Eth ring event configuration type Configuration related to ring event.
Definition: Eth_Cfg.h:782
uint8 totalEgressFifoNum
Definition: Eth_Cfg.h:918
boolean enableTxIrq
Definition: Eth_Cfg.h:1002
uint16 fifoNum
Definition: Eth_Cfg.h:860
Definition: Eth_Cfg.h:683
uint32 virtIntrNum
Definition: Eth_Cfg.h:772
Eth_DmaRingCfg EthDmaRingCfgOps
Definition: Eth_Cfg.h:936
Definition: Eth_Cfg.h:667
EthRemoteCfg_VirtPort
Virtual port id.
Definition: Eth_Cfg.h:604
uint8 fqRingIdx
Definition: Eth_Cfg.h:804
EthVirtMacDmaFLowCfg dmaFLowCfg
Definition: Eth_Cfg.h:960
Eth channel configuration type Configuration related to channel.
Definition: Eth_Cfg.h:812
uint8 hwTimerId
Definition: Eth_Cfg.h:972
uint32 macAddrHigh
Definition: Eth_Cfg.h:990
Definition: Eth_Cfg.h:687
Eth_FlowCfgType * flowCfgPtr
Definition: Eth_Cfg.h:900
Definition: Eth_Cfg.h:698
uint8 eventIdx
Definition: Eth_Cfg.h:786
Definition: Eth_Cfg.h:625
uint8 totalIngressFifoNum
Definition: Eth_Cfg.h:920
Eth_FifoHandleType * egressFifoCfgPtr
Definition: Eth_Cfg.h:882
uint32 totalSize
Definition: Eth_Cfg.h:864
EthVirtMacDmaTxChannelPair txChannelPair
Definition: Eth_Cfg.h:956
Eth_Udma_RingEventCfgType * ringEvenCfgPtr
Definition: Eth_Cfg.h:880
uint32 mdioAddr
Definition: Eth_Cfg.h:716
uint8 txThresholdNum
Definition: Eth_Cfg.h:914
uint32 phyMacAddr
Definition: Eth_Cfg.h:710
Definition: Eth_Cfg.h:587
uint8 totalRingNum
Definition: Eth_Cfg.h:910
Eth_RpcCmdComplete rpcCmdComplete
Definition: Eth_Cfg.h:950
uint8 totalEventNum
Definition: Eth_Cfg.h:908
uint8 * egressFifoPrioAssignCfgPtr
Definition: Eth_Cfg.h:890
uint8 flowNum
Definition: Eth_Cfg.h:840
boolean enableTxIrqPacing
Definition: Eth_Cfg.h:1018
uint16 chId
Definition: Eth_Cfg.h:816
Definition: Eth_Cfg.h:659
uint8 tdCqRingIdx
Definition: Eth_Cfg.h:814
uint32 mdioBusFreqHz
Definition: Eth_Cfg.h:724
Definition: Eth_Cfg.h:579
uint8 fqRingIdx
Definition: Eth_Cfg.h:828
EthRemoteCfg_VirtPort remoteVirtPort
Definition: Eth_Cfg.h:948
Eth_MdioDelayNsecFunc mdioReadHighDelayNsec
Definition: Eth_Cfg.h:1044
EthVirtMacDmaFLowReset dmaFLowReset
Definition: Eth_Cfg.h:962
Eth_MdioDelayNsecFunc mdioReadLowDelayNsec
Definition: Eth_Cfg.h:1042
uint32 proxyIdx
Definition: Eth_Cfg.h:746
Definition: Eth_Cfg.h:619
uint32 aleAddr
Definition: Eth_Cfg.h:712
Eth Udma Proxy Configurations type Configuration related to Udma proxy.
Definition: Eth_Cfg.h:756
uint16 startFlowId
Definition: Eth_Cfg.h:842
Definition: Eth_Cfg.h:595
EthVirtMacDmaTxChannelUnPair txChannelUnPair
Definition: Eth_Cfg.h:958
Eth Udma ring Configurations type Configuration related to Udma ring.
Definition: Eth_Cfg.h:736
Eth Udma configuration type Configuration related to Udma.
Definition: Eth_Cfg.h:872
uint32 hwLoopTimeout
Definition: Eth_Cfg.h:1000
uint32 priority
Definition: Eth_Cfg.h:744
void(* Eth_RpcFwRegistered)(uint8 CtrlIdx)
Application callback to indicate Ethernet firmware registered with the Eth RPC client.
Definition: Eth_Cfg.h:549
Definition: Eth_Cfg.h:593