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MCUSW
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MCUSW
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This document details AUTOSAR BSW ETH & ETHTRCV module implementations
The ETH module initializes, configures and controls the Gigabit Ethernet Switch (CPSW) in the J7xx device families as well as SITARA AM6xx device families as detailed in the AUTOSAR BSW ETH Driver Specification.
The ETHTRCV module initializes and configures the Ethernet transceiver (PHY) as detailed in the AUTOSAR BSW ETHTRCV Driver Specification.
Following section highlights key aspects of this implementation, which would be of interest to an integrator.
Currently, the MCAL Ethernet driver only depends on SciClient module in SDK
Please refer the ETH design page, which is included as part of release [3].
This ETH driver implementation supports the Gigabit Ethernet Switch (CPSW) peripheral present in the J7xx and AM6xx devices.
The CPSW peripheral in J7xx devices has an Ethernet port (port 1) which supports RGMII and RMII interfaces, and a host port (port 0) which supports the internal Communications Port Programming Interface (CPPI). The ETH driver uses UDMA to setup data transfers to/from the CPPI port.
In CPSW peripheral in AM6xx devices has 2 Ethernet ports (port 1 and port 2) which support RGMII and RMII interfaces, and a host port (port 0). However, the driver supports only one port. The port selection can be done via configurator.
The ETH driver uses DMSS to setup data transfers to/from the CPPI port.
The ETH driver implements single UDMA channel for data transmission and single channel (flow) for data reception. Only the CPSW default thread ID is enabled and configured according to the DMA receive channel's default flow. Interrupts can be enabled for DMA transmit and receive completion events.
The DMA transfers are based on descriptors called Host Mode Packet Descriptors (HMPD). The descriptors are given to and retrieved from the UDMA via Ring Accelerators. There are three rings used per data direction in this implementation:
The depth of each ring as well as its associated memory is configurable. The ring memories can be any memory in the system, but it's recommended that they are placed in a fast memory (i.e. OCMRAM or MSMC3). The depth of these rings is determined by the number of TX and RX buffers set in the driver configuration (EthTxBufTotal and EthRxBufTotal).
Similarly, the HMPDs can be placed in any memory of the system, but it's recommended that they are placed in OCMRAM or MSMC3 as well.
The Management Data I/O interface (MDIO) of the CPSW peripheral is used by the ETH driver to implement the MII register read and write APIs which are ultimately used by the ETHTRCV driver to configure the Ethernet transceiver (PHY). The ETH driver handles the MDIO interrupt which indicates the completion event of the Ethernet transceiver register accesses.
The Address Lookup Engine (ALE) of the CPSW peripheral is used by the ETH driver to implement the receive filter API. The ALE provides 64 entries that can be used to set filter rules.
The Statistics submodule of the CPSW peripheral is used by the ETH driver to implement the statistics and drop count APIs.
The following table lists the mapping between Ethernet interrupts and the corresponding interrupt service routines.
| Interrupt Number | Description | Associated ISR |
|---|---|---|
| Configurable | DMA RX Completion | Eth_RxIrqHdlr_0 |
| Configurable | DMA TX Completion | Eth_TxIrqHdlr_0 |
| 135 | MDIO Access Completion | Eth_MdioIrqHdlr_0 |
The DMA interrupt numbers can be set via the Ethernet driver configuration parameters EthDmaTxChIntrNum and EthDmaRxChIntrNum.
The table below summarizes the interrupt ranges allocated by default in TI SDK for the SoCs and the processing cores where the MCAL ETH driver is supported.
| SOC | Starting Resource (Value) | Range -----— |
|---|---|---|
| J7xx Devices | MCU0_INTR_NAVSS0_R5_0_PEND_0 (74) | 9 |
| AM62x | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_44 (66) | 36 |
| AM62Ax | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_168 (64) | 16 |
The interrupt numbers passed to the Ethernet driver configuration must be within the range stated above for each device, otherwise the interrupt allocation will fail while enabling the Ethernet controller.
Please refer to the UDMA Driver Resource Manager allocation for further details.
There are no interrupts in the ETHTRCV module.
The Eth Driver implementation in this release supports the Pre-Compile/LinkTime/ PostBuild configuration variant.
The driver expects generated: Eth_Cfg.h, Eth_Cfg.c, Eth_Lcfg.c and Eth_PBcfg.c to be present at the locations specified in the Eth File Structure section.
The EthTrcv Driver implementation only supports the Pre-Compile variant.
The driver expects generated EthTrcv_Cfg.h and EthTrcv_Cfg.c to be present at the locations specified in the EthTrcv File Structure section.
Use sysconfig tools to open am62a-evm.syscfg sysconfig file to get all DMA information
Please enable Resource Allocation Markdown.
In the Resource Sharing tab in sysconfig, you can see that MCU_0_R5_0 is sharing the following resource with A53_2 core.
For these resources, use the A53_2 column, instead of MCU_0_R5_0 column, to get DMA information.
For the Global Event Resource, since MCU_0_R5_0 don't share this with any other cores, use the MCU_0_R5_0 column to get the DMA information
Look at the column MCU_0_R5_0 to get DMA information for Global Event
The current implementation doesn't support QoS feature in transmission and reception:
Priority pamareter should be set to 0 when requesting a buffer via Eth_ProvideTxBuffer().FifoIdx parameter should be set to 0 when receiving a buffer via Eth_Receive().The driver doesn't call Ethernet Switch Interface APIs.
The wake-up related APIs are not implemented in this release:
The wake-up related functionality of other non wake-up specific APIs (i.e. EthTrcv_TransceiverInit(), EthTrcv_SetTransceiverMode(), etc) are not implemented in this release either.
The current EthTrcv driver implementation only supports auto-negotiation mode. The following APIs are impacted and partial functionality of the API is implemented:
The following EthTrcv ECUC APIs are not implemented in this release:
None.
The Ethernet driver doesn't register any interrupt handlers (ISR), it is expected that consumer of this driver registers the required interrupt handler.
The Ethernet interrupts are:
Other CPSW interrupts (like the Statistics Pending interrupt) are not handled by the driver.
Please refer to the EthApp_InterruptConfig() function in Eth demo application for the implementation details of the interrupt registration.
The driver doesn't configure the functional clock and power for the Ethernet module. It is expected that a Secondary Bootloader (SBL) or a Secondary Program loadeder (SPL) powers up and initialized the required modules.
When running the Ethernet driver MCAL example test application in AM62x, it is recommened to use the SBL for SOC Initialization instead of SPL, since running the linux and side loading the Eth MCAL may have some conflict in resource usage.
Please follow steps detailed in section (Build) to build library or example.
The GCC compiler is required to build the host-side application.
The steps to build the host-side application in Linux are listed below:
$ cd mcal_drv/mcal/examples/Eth/eth_app/host/ $ make
The Eth example application follows the same makefile base build system mentioned in the general mcal build user guide.
e.g.
$ cd build $ make -s eth_app BOARD=am62x_evm SOC=am62x CORE=mcu0_0 BUILD_PROFILE=debug BUILD_OS_TYPE=baremetal
The Eth example application can run an internal loopback test when configured accordingly in the driver's configuration parameters.
The example application per se doesn't need any change for loopback, but the loopback parameter must be set to TRUE as shown below. The example application can then be rebuilt following the regular steps listed in Build.
diff --git a/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/src/Eth_Cfg.c b/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/src/Eth_Cfg.c
index 24c046a..21cf137 100755
--- a/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/src/Eth_Cfg.c
+++ b/mcal_drv/mcal/examples_config/Eth_Demo_Cfg/output/generated/src/Eth_Cfg.c
@@ -75,7 +75,7 @@ ETH_CONFIG_DATA_SECTION CONST(Eth_ConfigType, ETH_CONFIG_SECTION)
/**< MDIO bus clock (MDCLK) frequency (in Hz) */
.connType = ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL,
/**< MII connection type */
- .loopback = FALSE,
+ .loopback = TRUE,
/**< Loopback enable */
.enableCacheOps = (uint32)TRUE,
/**< Packet memory is cacheable */
In order to run the loopback test, it's required to set the Ethernet driver's 'loopback' configuration parameter to TRUE as described in Building the target-side example application in loopback mode. In loopback mode, CPSW is configured with ALE in bypass mode and loopback is enabled in the MAC port (port 1).
This test doesn't require any additional external setup and the example can run standalone on the device. The example application will transmit and receive 1000 frames, and will verify the frame content.
This test consists of two applications: host-side application that runs on a Linux machine, and a target-side application that is loaded to the device (DUT).
Please refer to the Building the host-side example application section for instructions to build the host-side application.
$ ifconfig -s
$ cd mcal_drv/mcal/examples/Eth/eth_app/host/ $ sudo ./EthHostApp -i eth2
The example applications on either side (host or target) will report a fail status if any test Ethernet frames is lost. So even frames which are lost due to physical link will cause the example application to report as a failure.
Note: The test steps listed above have been tested in Ubuntu 16.04. Test errors have been found when running the test in Ubuntu 18.04.
Various objects of this implementation (e.g. variables, functions, constants) are defined under different sections. The linker command file at (Examples Linker File (Select memory location to hold example binary)) defines separate section for these objects. When the driver is integrated, it is expected that these sections are created and placed in appropriate memory locations. (Locations of these objects depend on the system design and performance needs)
| Section | ETH_CODE | ETH_VAR | ETH_VAR_NOINIT | ETH_CONST | ETH_CONFIG | ETH_UDMA_RING | ETH_UDMA_DESC | ETH_TX_DATA | ETH_RX_DATA |
| ETH_TEXT_SECTION | USED | ||||||||
| ETH_ISR_TEXT_SECTION | USED | ||||||||
| ETH_CONST_32_SECTION | USED | ||||||||
| ETH_CONFIG_SECTION | USED | ||||||||
| ETH_DATA_INIT_UNSPECIFIED_SECTION | USED | ||||||||
| ETH_DATA_NO_INIT_UNSPECIFIED_SECTION | USED | ||||||||
| ETH_UDMA_RING_SECTION | USED | ||||||||
| ETH_UDMA_DESC_SECTION | USED | ||||||||
| ETH_TX_DATA_SECTION | USED | ||||||||
| ETH_RX_DATA_SECTION | USED |
| Section | ETHTRCV_CODE | ETHTRCV_VAR | ETHTRCV_VAR_NOINIT | ETHTRCV_CONST | ETHTRCV_CONFIG |
| ETHTRCV_TEXT_SECTION | USED | ||||
| ETHTRCV_CONST_32_SECTION | USED | ||||
| ETHTRCV_CONFIG_SECTION | USED | ||||
| ETHTRCV_DATA_INIT_UNSPECIFIED_SECTION | USED | ||||
| ETHTRCV_DATA_INIT_32_SECTION | USED | ||||
| ETHTRCV_DATA_NO_INIT_UNSPECIFIED_SECTION | USED | ||||
| ETHTRCV_DATA_NO_INIT_16_SECTION | USED |
This driver implementation has been validated with cache enabled. For optimal performance it's recommended to place (Memory Mapping) sections in cache enabled memory area.
The Ethernet driver supports ring and descriptor memory placement in non-cached memory. It's configurable through the following parameters:
EthRingInCachedMem - Cache management operations will be performed in ring memory only if this parameter is set.EthDescInCachedMem - Cache management operations will be performed in descriptor memory only if this parameter is set.Cache management operations refer to invalidate, write-back and write-back invalidate calls.
This implementation depends on the DET in order to report development errors and can be turned OFF. Refer to the Development Error Reporting section for detailed error codes.
This implementation requires 1 level of exclusive access to guard critical sections. Invokes SchM_Enter_Eth_ETH_EXCLUSIVE_AREA_0(), SchM_Exit_Eth_ETH_EXCLUSIVE_AREA_0() to enter critical section and exit.
In the example implementation (SchM_Eth.c), all the interrupts on CPU are disabled. However, disabling of the enabled Ethernet related interrupts should suffice.
1.8.14