Introduction

UDMA configuration parameters.

Macros
#define	UDMA_DEFAULT_RM_PROXY_THREAD_START (4U)
	Default proxy thread number to start the allocation per core. More...

#define	UDMA_DEFAULT_RING_ORDER_ID (0U)
	Default ring order ID. More...

#define	UDMA_DEFAULT_TX_CH_DMA_PRIORITY (TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH)
	Default TX channel DMA priority. More...

#define	UDMA_DEFAULT_RX_CH_DMA_PRIORITY (TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH)
	Default RX channel DMA priority. More...

#define	UDMA_DEFAULT_UTC_CH_DMA_PRIORITY (TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH)
	Default RX channel DMA priority. More...

#define	UDMA_DEFAULT_TX_CH_BUS_PRIORITY (4U)
	Default TX channel bus priority. More...

#define	UDMA_DEFAULT_RX_CH_BUS_PRIORITY (4U)
	Default RX channel bus priority. More...

#define	UDMA_DEFAULT_UTC_CH_BUS_PRIORITY (4U)
	Default RX channel bus priority. More...

#define	UDMA_DEFAULT_TX_CH_BUS_QOS (4U)
	Default TX channel bus QOS. More...

#define	UDMA_DEFAULT_RX_CH_BUS_QOS (4U)
	Default RX channel bus QOS. More...

#define	UDMA_DEFAULT_UTC_CH_BUS_QOS (4U)
	Default RX channel bus QOS. More...

#define	UDMA_DEFAULT_TX_CH_BUS_ORDERID (0U)
	Default TX channel bus order ID. More...

#define	UDMA_DEFAULT_RX_CH_BUS_ORDERID (0U)
	Default RX channel bus order ID. More...

#define	UDMA_DEFAULT_UTC_CH_BUS_ORDERID (0U)
	Default RX channel bus order ID. More...

#define	UDMA_CFG_PRINT_BUF_LEN ((uint32_t) 1024U)
	UDMA print buffer length. More...

#define	UDMA_DEFAULT_CH_DISABLE_TIMEOUT (100U)
	Default UDMA channel disable timeout. More...


#define	UDMA_RM_MAX_BLK_COPY_CH (32U)

#define	UDMA_RM_MAX_BLK_COPY_HC_CH (32U)

#define	UDMA_RM_MAX_BLK_COPY_UHC_CH (32U)

#define	UDMA_RM_MAX_TX_CH (256U)

#define	UDMA_RM_MAX_TX_HC_CH (32U)

#define	UDMA_RM_MAX_TX_UHC_CH (32U)

#define	UDMA_RM_MAX_RX_CH (256U)

#define	UDMA_RM_MAX_RX_HC_CH (32U)

#define	UDMA_RM_MAX_RX_UHC_CH (32U)

#define	UDMA_RM_MAX_UTC_CH_PER_INST (64U)

#define	UDMA_RM_MAX_MAPPED_TX_CH_PER_GROUP (32U)

#define	UDMA_RM_MAX_MAPPED_RX_CH_PER_GROUP (32U)

#define	UDMA_RM_MAX_MAPPED_RING_PER_GROUP (64U)

#define	UDMA_RM_MAX_FREE_RING (1024U)

#define	UDMA_RM_MAX_FREE_FLOW (256U)

#define	UDMA_RM_MAX_GLOBAL_EVENT (1024U)

#define	UDMA_RM_MAX_VINTR (512U)

#define	UDMA_RM_MAX_IR_INTR (128U)

#define	UDMA_RM_MAX_PROXY (32U)

#define	UDMA_RM_MAX_RING_MON (32U)

#define	UDMA_RM_BLK_COPY_CH_ARR_SIZE (UDMA_RM_MAX_BLK_COPY_CH >> 5U)

#define	UDMA_RM_BLK_COPY_HC_CH_ARR_SIZE (UDMA_RM_MAX_BLK_COPY_HC_CH >> 5U)

#define	UDMA_RM_BLK_COPY_UHC_CH_ARR_SIZE (UDMA_RM_MAX_BLK_COPY_UHC_CH >> 5U)

#define	UDMA_RM_TX_CH_ARR_SIZE (UDMA_RM_MAX_TX_CH >> 5U)

#define	UDMA_RM_TX_HC_CH_ARR_SIZE (UDMA_RM_MAX_TX_HC_CH >> 5U)

#define	UDMA_RM_TX_UHC_CH_ARR_SIZE (UDMA_RM_MAX_TX_UHC_CH >> 5U)

#define	UDMA_RM_RX_CH_ARR_SIZE (UDMA_RM_MAX_RX_CH >> 5U)

#define	UDMA_RM_RX_HC_CH_ARR_SIZE (UDMA_RM_MAX_RX_HC_CH >> 5U)

#define	UDMA_RM_RX_UHC_CH_ARR_SIZE (UDMA_RM_MAX_RX_UHC_CH >> 5U)

#define	UDMA_RM_UTC_CH_ARR_SIZE (UDMA_RM_MAX_UTC_CH_PER_INST >> 5U)

#define	UDMA_RM_MAPPED_TX_CH_ARR_SIZE (UDMA_RM_MAX_MAPPED_TX_CH_PER_GROUP >> 5U)

#define	UDMA_RM_MAPPED_RX_CH_ARR_SIZE (UDMA_RM_MAX_MAPPED_RX_CH_PER_GROUP >> 5U)

#define	UDMA_RM_MAPPED_RING_ARR_SIZE (UDMA_RM_MAX_MAPPED_RING_PER_GROUP >> 5U)

#define	UDMA_RM_FREE_RING_ARR_SIZE (UDMA_RM_MAX_FREE_RING >> 5U)

#define	UDMA_RM_FREE_FLOW_ARR_SIZE (UDMA_RM_MAX_FREE_FLOW >> 5U)

#define	UDMA_RM_GLOBAL_EVENT_ARR_SIZE (UDMA_RM_MAX_GLOBAL_EVENT >> 5U)

#define	UDMA_RM_VINTR_ARR_SIZE (UDMA_RM_MAX_VINTR >> 5U)

#define	UDMA_RM_IR_INTR_ARR_SIZE (UDMA_RM_MAX_IR_INTR >> 5U)

#define	UDMA_RM_PROXY_ARR_SIZE (UDMA_RM_MAX_PROXY >> 5U)

#define	UDMA_RM_RING_MON_ARR_SIZE (UDMA_RM_MAX_RING_MON >> 5U)

Introduction

Macros