Udma_ChTxPrms Struct Reference

Detailed Description

UDMA TX channel parameters.

Data Fields
uint8_t	pauseOnError
uint8_t	filterEinfo
uint8_t	filterPsWords
uint8_t	addrType
uint8_t	chanType
uint16_t	fetchWordSize
uint8_t	busPriority
uint8_t	busQos
uint8_t	busOrderId
uint8_t	dmaPriority
uint8_t	txCredit
uint16_t	fifoDepth
uint8_t	burstSize
uint8_t	supressTdCqPkt

Field Documentation

pauseOnError

uint8_t Udma_ChTxPrms::pauseOnError

[IN] Bool: When set (TRUE), pause channel on error

filterEinfo

uint8_t Udma_ChTxPrms::filterEinfo

[IN] Bool: When set (TRUE), filter out extended info

filterPsWords

uint8_t Udma_ChTxPrms::filterPsWords

[IN] Bool: When set (TRUE), filter out protocl specific words

addrType

uint8_t Udma_ChTxPrms::addrType

[IN] Address type for this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype

chanType

uint8_t Udma_ChTxPrms::chanType

[IN] Channel type. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type

fetchWordSize

uint16_t Udma_ChTxPrms::fetchWordSize

[IN] Descriptor/TR Size in 32-bit words

busPriority

uint8_t Udma_ChTxPrms::busPriority

[IN] 3-bit priority value (0=highest, 7=lowest)

busQos

uint8_t Udma_ChTxPrms::busQos

[IN] 3-bit qos value (0=highest, 7=lowest)

busOrderId

uint8_t Udma_ChTxPrms::busOrderId

[IN] 4-bit orderid value

dmaPriority

uint8_t Udma_ChTxPrms::dmaPriority

[IN] This field selects which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority

txCredit

uint8_t Udma_ChTxPrms::txCredit

[IN] TX credit for external channels

fifoDepth

uint16_t Udma_ChTxPrms::fifoDepth

[IN] The fifo depth is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time, the FIFO depth can be artificially reduced in order to control the maximum latency which can be introduced due to buffering effects.

The maximum FIFO depth suppported depends on the channel type as given below: Normal Capacity Channel - CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH (128 bytes) High Capacity Channel - CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH (1024 bytes) Ultra High Capacity Channel - CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH (4096 bytes)

The default init API will set this paramater as per the channel type.

burstSize

uint8_t Udma_ChTxPrms::burstSize

[IN] Specifies the nominal burst size and alignment for data transfers on this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size. Note1: This parameter should be set less than or equal to the FIFO depth parameter set for UTC channel i.e. fifoDepth >= burstSize Note2: In case of packet mode TX channels, the Tx fifoDepth must be at least 2 PSI-L data phases (32 bytes) larger than the burst size given in this field in order to hold the packet info and extended packet info header which is placed at the front of the data packet in addition to the payload i.e. fifoDepth >= (burstSize + 32 bytes)

Below are the supported burst sizes for various channel types Normal Capacity Channel - 64 bytes High Capacity Channel - 64, 128 or 256 bytes Ultra High Capacity Channel - 64, 128 or 256 bytes

supressTdCqPkt

uint8_t Udma_ChTxPrms::supressTdCqPkt

[IN] Bool: Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. FALSE = TD packet is sent TRUE = Suppress sending TD packet