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    AM64x MCU+ SDK
    11.01.00
    
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   54 #ifndef TISCI_PROTOCOL_H 
   55 #define TISCI_PROTOCOL_H 
   67 #define TISCI_MSG_FLAG_RESERVED0    TISCI_BIT(0) 
   75 #define TISCI_MSG_FLAG_AOP    TISCI_BIT(1) 
   78 #define TISCI_MSG_FLAG_SEC    TISCI_BIT(2) 
   84 #define TISCI_MSG_FLAG_ACK    TISCI_BIT(1) 
  129 #define TISCI_MSG_VERSION                       (0x0002U) 
  130 #define TISCI_MSG_DM_VERSION                    (0x000FU) 
  131 #define TISCI_MSG_BOOT_NOTIFICATION             (0x000AU) 
  132 #define TISCI_MSG_BOARD_CONFIG                  (0x000BU) 
  133 #define TISCI_MSG_BOARD_CONFIG_RM               (0x000CU) 
  134 #define TISCI_MSG_BOARD_CONFIG_SECURITY         (0x000DU) 
  135 #define TISCI_MSG_BOARD_CONFIG_PM               (0x000EU) 
  137 #define TISCI_MSG_ENABLE_WDT                    (0x0000U) 
  138 #define TISCI_MSG_WAKE_RESET                    (0x0001U) 
  139 #define TISCI_MSG_WAKE_REASON                   (0x0003U) 
  140 #define TISCI_MSG_GOODBYE                       (0x0004U) 
  141 #define TISCI_MSG_SYS_RESET                     (0x0005U) 
  143 #define TISCI_MSG_QUERY_MSMC                    (0x0020U) 
  144 #define TISCI_MSG_GET_TRACE_CONFIG              (0x0021U) 
  145 #define TISCI_MSG_QUERY_FW_CAPS                 (0x0022U) 
  147 #define TISCI_MSG_SET_CLOCK                     (0x0100U) 
  148 #define TISCI_MSG_GET_CLOCK                     (0x0101U) 
  149 #define TISCI_MSG_SET_CLOCK_PARENT              (0x0102U) 
  150 #define TISCI_MSG_GET_CLOCK_PARENT              (0x0103U) 
  151 #define TISCI_MSG_GET_NUM_CLOCK_PARENTS         (0x0104U) 
  152 #define TISCI_MSG_SET_FREQ                      (0x010cU) 
  153 #define TISCI_MSG_QUERY_FREQ                    (0x010dU) 
  154 #define TISCI_MSG_GET_FREQ                      (0x010eU) 
  156 #define TISCI_MSG_SET_DEVICE                    (0x0200U) 
  157 #define TISCI_MSG_GET_DEVICE                    (0x0201U) 
  158 #define TISCI_MSG_SET_DEVICE_RESETS             (0x0202U) 
  159 #define TISCI_MSG_DEVICE_DROP_POWERUP_REF       (0x0203U) 
  161 #define TISCI_MSG_PREPARE_SLEEP                 (0x0300U) 
  162 #define TISCI_MSG_ENTER_SLEEP                   (0x0301U) 
  168 #define TISCI_MSG_SYNC_RESUME                   (0x0302U) 
  169 #define TISCI_MSG_CONTINUE_RESUME               (0x0303U) 
  170 #define TISCI_MSG_CORE_RESUME                   (0x0304U) 
  171 #define TISCI_MSG_ABORT_ENTER_SLEEP             (0x0305U) 
  172 #define TISCI_MSG_LPM_WAKE_REASON               (0x0306U) 
  173 #define TISCI_MSG_SET_IO_ISOLATION              (0x0307U) 
  174 #define TISCI_MSG_MIN_CONTEXT_RESTORE           (0x0308U) 
  175 #define TISCI_MSG_LPM_SET_DEVICE_CONSTRAINT     (0x0309U) 
  176 #define TISCI_MSG_LPM_SET_LATENCY_CONSTRAINT    (0x030AU) 
  177 #define TISCI_MSG_LPM_GET_DEVICE_CONSTRAINT     (0x030BU) 
  178 #define TISCI_MSG_LPM_GET_LATENCY_CONSTRAINT    (0x030CU) 
  179 #define TISCI_MSG_LPM_GET_NEXT_SYS_MODE         (0x030DU) 
  180 #define TISCI_MSG_LPM_GET_NEXT_HOST_STATE       (0x030EU) 
  183 #define TISCI_MSG_LPM_ENCRYPT                   (0x030FU) 
  185 #define TISCI_MSG_LPM_DECRYPT                   (0x0310U) 
  186 #define TISCI_MSG_LPM_ABORT                     (0x0311U) 
  188 #define TISCI_MSG_FIRMWARE_LOAD                 (0x8105U) 
  189 #define MSG_FIRMWARE_LOAD_RESULT                (0x8805U) 
  192 #define TISCI_MSG_SET_FWL_REGION                (0x9000U) 
  194 #define TISCI_MSG_GET_FWL_REGION                (0x9001U) 
  196 #define TISCI_MSG_CHANGE_FWL_OWNER              (0x9002U) 
  198 #define TISCI_MSG_CRYPTO_SET_DKEK               (0x9003U) 
  200 #define TISCI_MSG_SA2UL_SET_DKEK                TISCI_MSG_CRYPTO_SET_DKEK 
  202 #define TISCI_MSG_CRYPTO_RELEASE_DKEK           (0x9004U) 
  204 #define TISCI_MSG_SA2UL_RELEASE_DKEK            TISCI_MSG_CRYPTO_RELEASE_DKEK 
  206 #define TISCI_MSG_KEYSTORE_IMPORT_SKEY          (0x9005U) 
  208 #define TISCI_MSG_KEYSTORE_ERASE_SKEY           (0x9006U) 
  210 #define TISCI_MSG_SEC_RESERVED_9007             (0x9007U) 
  212 #define TISCI_MSG_SEC_RESERVED_9008             (0x9008U) 
  214 #define TISCI_MSG_SET_ISC_REGION                (0x9009U) 
  216 #define TISCI_MSG_GET_ISC_REGION                (0x900AU) 
  218 #define TISCI_MSG_FWL_EXCP_NOTIFICATION         (0x900BU) 
  220 #define TISCI_MSG_OPEN_DEBUG_FWLS               (0x900CU) 
  225 #define TISCI_MSG_KEYSTORE_WRITE                (0x900DU) 
  230 #define TISCI_MSG_KEYSTORE_EXPORT_ALL           (0x900EU) 
  232 #define TISCI_MSG_KEYSTORE_IMPORT_ALL           (0x900FU) 
  234 #define TISCI_MSG_SEC_RESERVED_9010             (0x9010U) 
  236 #define TISCI_MSG_SEC_RESERVED_9011             (0x9011U) 
  238 #define TISCI_MSG_SEC_RESERVED_9012             (0x9012U) 
  240 #define TISCI_MSG_SEC_RESERVED_9013             (0x9013U) 
  242 #define TISCI_MSG_SEC_RESERVED_9014             (0x9014U) 
  244 #define TISCI_MSG_SEC_RESERVED_9015             (0x9015U) 
  247 #define TISCI_MSG_SEC_RESERVED_9016             (0x9016U) 
  250 #define TISCI_MSG_SA2UL_AUTH_RES_ACQUIRE        (0x9017U) 
  253 #define TISCI_MSG_SA2UL_AUTH_RES_RELEASE        (0x9018U) 
  256 #define TISCI_MSG_SEC_RESERVED_9020             (0x9020U) 
  259 #define TISCI_MSG_GET_SOC_UID                   (0x9021U) 
  265 #define TISCI_MSG_READ_OTP_MMR                  (0x9022U) 
  268 #define TISCI_MSG_WRITE_OTP_ROW                 (0x9023U) 
  271 #define TISCI_MSG_LOCK_OTP_ROW                  (0x9024U) 
  274 #define TISCI_MSG_SOFT_LOCK_OTP_WRITE_GLOBAL    (0x9025U) 
  277 #define TISCI_MSG_GET_OTP_ROW_LOCK_STATUS       (0x9026U) 
  280 #define TISCI_MSG_RSVD_OTP_1                    (0x9027U) 
  283 #define TISCI_MSG_RSVD_OTP_2                    (0x9028U) 
  286 #define TISCI_MSG_CRYPTO_GET_DKEK               (0x9029U) 
  288 #define TISCI_MSG_SA2UL_GET_DKEK                TISCI_MSG_CRYPTO_GET_DKEK 
  291 #define TISCI_MSG_ALLOW_FWL_CTRL_READ           (0x902CU) 
  294 #define TISCI_MSG_FORBID_FWL_CTRL_READ          (0x902DU) 
  299 #define TISCI_MSG_SEC_HANDOVER                  (0x9030U) 
  304 #define TISCI_MSG_KEY_WRITER                    (0x9031U) 
  307 #define TISCI_MSG_WRITE_SWREV                   (0x9032U) 
  310 #define TISCI_MSG_READ_SWREV                    (0x9033U) 
  313 #define TISCI_MSG_READ_KEYCNT_KEYREV            (0x9034U) 
  316 #define TISCI_MSG_WRITE_KEYREV                  (0x9035U) 
  319 #define TISCI_MSG_CRYPTO_GET_DSMEK              (0x9036U) 
  321 #define TISCI_MSG_SA2UL_GET_DSMEK               TISCI_MSG_CRYPTO_GET_DSMEK 
  324 #define TISCI_MSG_CRYPTO_SET_DSMEK              (0x9037U) 
  326 #define TISCI_MSG_SA2UL_SET_DSMEK               TISCI_MSG_CRYPTO_SET_DSMEK 
  329 #define TISCI_MSG_CRYPTO_RELEASE_DSMEK          (0x9038U) 
  331 #define TISCI_MSG_SA2UL_RELEASE_DSMEK           TISCI_MSG_CRYPTO_RELEASE_DSMEK 
  334 #define TISCI_MSG_KEYRING_IMPORT                (0X9039U) 
  337 #define TISCI_MSG_CRYPTO_SET_DKEK_CONST         (0x902AU) 
  339 #define TISCI_MSG_SA2UL_SET_DKEK_CONST          TISCI_MSG_CRYPTO_SET_DKEK_CONST 
  342 #define TISCI_MSG_CRYPTO_GET_DKEK_CONST         (0x902BU) 
  344 #define TISCI_MSG_SA2UL_GET_DKEK_CONST          TISCI_MSG_CRYPTO_GET_DKEK_CONST 
  347 #define TISCI_MSG_CRYPTO_AES_ENCRYPT            (0x9040U) 
  349 #define TISCI_MSG_SA2UL_AES_ENCRYPT             TISCI_MSG_CRYPTO_AES_ENCRYPT 
  352 #define TISCI_MSG_CRYPTO_AES_DECRYPT            (0x9041U) 
  354 #define TISCI_MSG_SA2UL_AES_DECRYPT             TISCI_MSG_CRYPTO_AES_DECRYPT 
  357 #define TISCI_MSG_DISABLE_JTAG_UNLOCK           (0x9042U) 
  360 #define TISCI_MSG_DISABLE_JTAG_UNLOCK_CHECK     (0x9043U) 
  363 #define TISCI_MSG_SET_OTP_BOOT_MODE             (0x9044U) 
  368 #define TISCI_MSG_PROC_REQUEST          (0xC000U) 
  370 #define TISCI_MSG_PROC_RELEASE          (0xC001U) 
  372 #define TISCI_MSG_PROC_HANDOVER         (0xC005U) 
  375 #define TISCI_MSG_PROC_SET_CONFIG       (0xC100U) 
  377 #define TISCI_MSG_PROC_SET_CONTROL      (0xC101U) 
  380 #define TISCI_MSG_PROC_GET_STATUS       (0xC400U) 
  383 #define TISCI_MSG_PROC_WAIT_STATUS      (0xC401U) 
  386 #define TISCI_MSG_PROC_AUTH_BOOT        (0xC120U) 
  389 #define TISCI_MSG_MCELF_PROC_AUTH_BOOT_INIT        (0xC122U) 
  392 #define TISCI_MSG_MCELF_PROC_AUTH_BOOT_UPDATE        (0xC123U) 
  398 #define TISCI_MSG_MCELF_PROC_AUTH_BOOT_FINISH        (0xC124U) 
  405 #define TISCI_MSG_RM_GET_RESOURCE_RANGE         (0x1500U) 
  409 #define TISCI_MSG_RM_IRQ_SET                    (0x1000U) 
  413 #define TISCI_MSG_RM_IRQ_RELEASE                (0x1001U) 
  415 #define TISCI_MSG_RM_RESERVED_1100              (0x1100U) 
  417 #define TISCI_MSG_RM_RESERVED_1101              (0x1101U) 
  419 #define TISCI_MSG_RM_RESERVED_1102              (0x1102U) 
  421 #define TISCI_MSG_RM_RESERVED_1103              (0x1103U) 
  425 #define TISCI_MSG_RM_RING_CFG                   (0x1110U) 
  427 #define TISCI_MSG_RM_RESERVED_1111              (0x1111U) 
  431 #define TISCI_MSG_RM_RING_MON_CFG               (0x1120U) 
  433 #define TISCI_MSG_RM_RESERVED_1200              (0x1200U) 
  435 #define TISCI_MSG_RM_RESERVED_1201              (0x1201U) 
  439 #define TISCI_MSG_RM_UDMAP_TX_CH_CFG            (0x1205U) 
  441 #define TISCI_MSG_RM_RESERVED_1206              (0x1206U) 
  443 #define TISCI_MSG_RM_RESERVED_1210              (0x1210U) 
  445 #define TISCI_MSG_RM_RESERVED_1211              (0x1211U) 
  449 #define TISCI_MSG_RM_UDMAP_RX_CH_CFG            (0x1215U) 
  450 #define TISCI_MSG_RM_RESERVED_1216              (0x1216U) 
  452 #define TISCI_MSG_RM_RESERVED_1220              (0x1220U) 
  454 #define TISCI_MSG_RM_RESERVED_1221              (0x1221U) 
  458 #define TISCI_MSG_RM_UDMAP_FLOW_CFG             (0x1230U) 
  463 #define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG (0x1231U) 
  465 #define TISCI_MSG_RM_RESERVED_1232              (0x1232U) 
  467 #define TISCI_MSG_RM_RESERVED_1233              (0x1233U) 
  471 #define TISCI_MSG_RM_UDMAP_FLOW_DELEGATE        (0x1234U) 
  476 #define TISCI_MSG_RM_UDMAP_GCFG_CFG             (0x1240U) 
  478 #define TISCI_MSG_RM_RESERVED_1241              (0x1241U) 
  482 #define TISCI_MSG_RM_PSIL_PAIR                  (0x1280U) 
  486 #define TISCI_MSG_RM_PSIL_UNPAIR                (0x1281U) 
  490 #define TISCI_MSG_RM_PSIL_READ                  (0x1282U) 
  494 #define TISCI_MSG_RM_PSIL_WRITE                 (0x1283U) 
  499 #define TISCI_MSG_RM_PROXY_CFG                  (0x1300U)