UDMA event related parameters.
Requirement: DOX_REQ_TAG(PDK-2628), DOX_REQ_TAG(PDK-2627) DOX_REQ_TAG(PDK-2626), DOX_REQ_TAG(PDK-2625)
Data Fields | |
uint32_t | eventType |
uint32_t | eventMode |
Udma_ChHandle | chHandle |
Udma_RingHandle | ringHandle |
Udma_EventHandle | controllerEventHandle |
Udma_EventCallback | eventCb |
uint32_t | intrPriority |
void * | appData |
uint32_t | preferredCoreIntrNum |
volatile uint64_t * | intrStatusReg |
volatile uint64_t * | intrClearReg |
uint64_t | intrMask |
uint32_t | vintrNum |
uint32_t | coreIntrNum |
uint32_t Udma_EventPrms::eventType |
[IN] Event type to register. Refer Udma_EventType
uint32_t Udma_EventPrms::eventMode |
[IN] Event mode - exclusive or shared. Refer Udma_EventMode. This parameter should be set to UDMA_EVENT_MODE_SHARED for UDMA_EVENT_TYPE_MASTER event type.
Udma_ChHandle Udma_EventPrms::chHandle |
[IN] Channel handle when the event type is one of below
Udma_RingHandle Udma_EventPrms::ringHandle |
[IN] Ring handle when the event type is one of below
Udma_EventHandle Udma_EventPrms::controllerEventHandle |
[IN] Master event handle used to share the IA register when the event mode is set to UDMA_EVENT_MODE_SHARED. This is typically used to share multiple events from same source like same peripheral to one IA register which eventually routes to a single core interrupt. For the first(or master) event this should be set to NULL. The driver will allocate the required resources (IA/IR) for the first event. For the subsequent shared event registration, the master event handle should be passed as reference and the driver will allocate only the IA status bits. At a maximum UDMA_MAX_EVENTS_PER_VINTR number of events can be shared. Beyond that the driver will return error. This parameter should be set to NULL for UDMA_EVENT_TYPE_MASTER event type.
Udma_EventCallback Udma_EventPrms::eventCb |
[IN] When callback function is set (non-NULL), the driver will allocate core level interrupt through Interrupt Router and the function will be called when the registered event occurs. When set to NULL, the API will only allocate event and no interrupt routing is performed. Note: In case of shared events (multiple events mapped to same interrupt), the driver will call the callbacks in the order of event registration. This parameter should be set to NULL for UDMA_EVENT_TYPE_MASTER event type.
uint32_t Udma_EventPrms::intrPriority |
[IN] Priority of interrupt to register with OSAL. The interpretation depends on the OSAL implementation
void* Udma_EventPrms::appData |
[IN] Application/caller context pointer passed back in the event callback function. This could be used by the caller to identify the channel/event for which the callback is called. This can be set to NULL, if not required by caller.
uint32_t Udma_EventPrms::preferredCoreIntrNum |
[IN] Preferred core interrupt number which goes to a core.
If set to UDMA_CORE_INTR_ANY, will allocate from free pool. Else will try to allocate the mentioned interrupt itself.
volatile uint64_t* Udma_EventPrms::intrStatusReg |
[OUT] Interrupt status register address of the allocated IA VINT register. This is used to check if interrupt occurred
volatile uint64_t* Udma_EventPrms::intrClearReg |
[OUT] Interrupt clear register address of the allocated IA VINT register. This is used to clear if interrupt occurred
uint64_t Udma_EventPrms::intrMask |
[OUT] Interrupt mask to check and clear
uint32_t Udma_EventPrms::vintrNum |
[OUT] IA Virtual interrupt number allocated.
uint32_t Udma_EventPrms::coreIntrNum |
[OUT] Core interrupt number allocated. This number can be used to register with the OSAL
Note: Incase of C7x, this represents the GIC SPI events to the CLEC. For routing this event, the driver further uses the Udma_RmInitPrms - 'startC7xCoreIntr' parameter as the start C7x interrupt and assumes that numIrIntr C7x interrupt are used by UDMA driver for one to one mapping. The UDMA driver directly programs the CLEC for this routing
Example: startIrIntr = 700, numIrIntr = 3, startC7xCoreIntr = 32
First Event registration: CLEC input : 700+1024-32 CLEC output : 32 OSAL registration : 32
Second Event registration: CLEC input : 701+1024-32 CLEC output : 33 OSAL registration : 33