AM64x MCU+ SDK  11.01.00
sdl_ecc.h
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1 /*
2  * SDL ECC
3  *
4  * Software Diagnostics Library module for ECC
5  *
6  * Copyright (c) Texas Instruments Incorporated 2022-2025
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  *
12  * Redistributions of source code must retain the above copyright
13  * notice, this list of conditions and the following disclaimer.
14  *
15  * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in the
17  * documentation and/or other materials provided with the
18  * distribution.
19  *
20  * Neither the name of Texas Instruments Incorporated nor the names of
21  * its contributors may be used to endorse or promote products derived
22  * from this software without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35  *
36  */
56 #ifndef INCLUDE_SDL_ECC_H_
57 #define INCLUDE_SDL_ECC_H_
58 
59 #include <stdint.h>
60 #include <stdbool.h>
61 
62 #include "sdl_common.h"
63 #include <sdl/include/soc_config.h>
64 #include <sdl/ecc/sdl_ip_ecc.h>
65 #if defined(SOC_AM263X)
66 #include <sdl/esm/v0/sdl_esm.h>
67 #endif
68 #if defined(SOC_AM263PX) || defined(SOC_AM261X)
69 #include <sdl/esm/v2/sdl_esm.h>
70 #endif
71 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
72 #include <sdl/esm/v1/sdl_esm.h>
73 #endif
74 #if defined(SOC_AM64X) || defined(SOC_AM243X)
75 #include <sdl/esm/v0/sdl_esm.h>
76 #endif
77 
78 #ifdef __cplusplus
79 extern "C" {
80 #endif
81 
87 #if defined(SOC_AM263X) || defined(SOC_AM263PX)
88 
89 #define SDL_SOC_ECC_AGGR (0U)
90 #define SDL_R5FSS0_CORE0_ECC_AGGR (1U)
91 #define SDL_R5FSS0_CORE1_ECC_AGGR (2U)
92 #define SDL_R5FSS1_CORE0_ECC_AGGR (3U)
93 #define SDL_R5FSS1_CORE1_ECC_AGGR (4U)
94 #define SDL_HSM_ECC_AGGR (5U)
95 #define SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR (6U)
96 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (7U)
97 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (8U)
98 #if defined(SOC_AM263X) || defined(SOC_AM263PX)
99 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (9U)
100 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (10U)
101 #endif
102 #if defined(SOC_AM263PX)
103 #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (11U)
104 #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (12U)
105 #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (13U)
106 #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (14U)
107 #define SDL_FSS_OSPI_RAM_ECC_AGGR (15U)
108 #define SDL_FSS_FOTA_8051_RAM_ECC_AGGR (16U)
109 #define SDL_CPSW3GCSS_ECC_AGGR (17U)
110 #else
111 #define SDL_CPSW3GCSS_ECC_AGGR (11U)
112 #endif
113 #define SDL_ECC_MEMTYPE_MAX (SDL_CPSW3GCSS_ECC_AGGR + 1U)
114 
115 /* Parity */
116 #define SDL_R5SS0_CPU0_TCM (0U)
117 #define SDL_R5SS1_CPU0_TCM (1U)
118 /* SDL_R5SS0_CPU0_TCM */
119 #define SDL_R5FSS0_CORE0_ATCM0 (1U)
120 #define SDL_R5FSS0_CORE0_B0TCM0 (3U)
121 #define SDL_R5FSS0_CORE0_B1TCM0 (5U)
122 /* SDL_R5SS0_CPU10_TCM */
123 #define SDL_R5FSS0_CORE1_ATCM1 (2U)
124 #define SDL_R5FSS0_CORE1_B0TCM1 (4U)
125 #define SDL_R5FSS0_CORE1_B1TCM1 (6U)
126 /* SDL_R5SS1_CPU0_TCM */
127 #define SDL_R5FSS1_CORE0_ATCM0 (7U)
128 #define SDL_R5FSS1_CORE0_B0TCM0 (9U)
129 #define SDL_R5FSS1_CORE0_B1TCM0 (11U)
130 /* SDL_R5SS1_CPU1_TCM */
131 #define SDL_R5FSS1_CORE1_ATCM1 (8U)
132 #define SDL_R5FSS1_CORE1_B0TCM1 (10U)
133 #define SDL_R5FSS1_CORE1_B1TCM1 (12U)
134 /* TPCC */
135 #define SDL_TPCC0 (2)
136 #endif
137 
138 #if defined(SOC_AM261X)
139 #define SDL_SOC_ECC_AGGR (0U)
140 #define SDL_R5FSS0_CORE0_ECC_AGGR (1U)
141 #define SDL_R5FSS0_CORE1_ECC_AGGR (2U)
142 #define SDL_HSM_ECC_AGGR (3U)
143 #define SDL_ICSSM0_ICSS_G_CORE_BORG_ECC_AGGR (4U)
144 #define SDL_ICSSM1_ICSS_G_CORE_BORG_ECC_AGGR (5U)
145 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (6U)
146 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (7U)
147 #define SDL_CPSW3GCSS_ECC_AGGR (8U)
148 #define SDL_FSS_OSPI_RAM_ECC_AGGR (9U)
149 #define SDL_FSS_FOTA_8051_RAM_ECC_AGGR (10U)
150 #define SDL_OSPI1_RAM_ECC_AGGR (11U)
151 
152 #define SDL_ECC_MEMTYPE_MAX (SDL_OSPI1_RAM_ECC_AGGR + 1U)
153 
154 /* Parity */
155 #define SDL_R5SS0_CPU0_TCM (0U)
156 /* SDL_R5SS0_CPU0_TCM */
157 #define SDL_R5FSS0_CORE0_ATCM0 (1U)
158 #define SDL_R5FSS0_CORE0_B0TCM0 (3U)
159 #define SDL_R5FSS0_CORE0_B1TCM0 (5U)
160 /* SDL_R5SS0_CPU10_TCM */
161 #define SDL_R5FSS0_CORE1_ATCM1 (2U)
162 #define SDL_R5FSS0_CORE1_B0TCM1 (4U)
163 #define SDL_R5FSS0_CORE1_B1TCM1 (6U)
164 /* TPCC */
165 #define SDL_TPCC0 (2)
166 
167 #endif
168 
169 #if defined(SOC_AM273X) || defined(SOC_AWR294X)
170 #define SDL_R5FSS0_CORE0_ECC_AGGR (0U)
171 #define SDL_R5FSS0_CORE1_ECC_AGGR (1U)
172 #define SDL_MSS_ECC_AGG_MSS (2U)
173 #define SDL_DSS_ECC_AGG (3U)
174 #define SDL_MSS_MCANA_ECC (4U)
175 #define SDL_MSS_MCANB_ECC (5U)
176 #define SDL_CPSW3GCSS_ECC_AGGR (6U)
177 #define SDL_ECC_MEMTYPE_MAX (SDL_CPSW3GCSS_ECC_AGGR + 1U)
178 /* TCM PARITY */
179 #define SDL_TCM_PARITY_ATCM0 (1U)
180 #define SDL_TCM_PARITY_ATCM1 (2U)
181 #define SDL_TCM_PARITY_B0TCM0 (3U)
182 #define SDL_TCM_PARITY_B0TCM1 (4U)
183 #define SDL_TCM_PARITY_B1TCM0 (5U)
184 #define SDL_TCM_PARITY_B1TCM1 (6U)
185 
186 /* TPCC */
187 #define SDL_TPCC0A (2U)
188 #define SDL_TPCC0B (3U)
189 #define SDL_DSS_TPCCA (4U)
190 #define SDL_DSS_TPCCB (5U)
191 #define SDL_DSS_TPCCC (6U)
192 #endif
193 
194 #if defined(SOC_AM64X) || defined(SOC_AM243X)
195 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR (0u)
196 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM (1u)
197 #define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR (2u)
198 #define SDL_ECC_AGGR1 (3u)
199 #define SDL_ECC_AGGR0 (4u)
200 #define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR (5u)
201 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (6u)
202 #define SDL_DMASS0_DMSS_AM64_ECCAGGR (7u)
203 #define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM (8u)
204 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (9u)
205 #define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR (10u)
206 #define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR (11u)
207 #define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR (12u)
208 #define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR (13u)
209 #define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR (14u)
210 #define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR (15u)
211 #define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR (16u)
212 #define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR (17u)
213 #define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A__ECC_AGGR (18u)
214 #define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR (19u)
215 #define SDL_DMSC0_DMSC_LITE_ECC_AGGR_TXMEM (20u)
216 #define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_TXMEM (21u)
217 #define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR (22u)
218 #define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR (23u)
219 #define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR (24u)
220 #define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR (25u)
221 #define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR (26u)
222 #define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR (27u)
223 #define SDL_MCU_M4FSS0_BLAZAR_ECCAGGR (28u)
224 #define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR (29u)
225 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM (30u)
226 #define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM (31u)
227 #define SDL_VTM0_K3VTM_N16FFC_ECCAGGR (32u)
228 #define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR (33u)
229 #define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR (34u)
230 #define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR (35u)
231 #define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR (36u)
232 #if defined(SOC_AM64X)
233 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0 (37u)
234 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC (38u)
235 #define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 (39u)
236 #define SDL_ECC_MEMTYPE_MAX (SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1 + 1U)
237 #endif
238 #if defined(SOC_AM243X)
239 #define SDL_ECC_MEMTYPE_MAX (SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR + 1U)
240 #endif
241 #endif
242 
243 /* The following are the memory sub type for Memory type
244  SDL_ECC_MEMTYPE_MCU_R5F0_CORE & SDL_ECC_MEMTYPE_MCU_R5F1_CORE */
245 /* Keeping for backward-compatibility. Recommend to use RAM_ID directly from sdlr_soc_ecc_aggr.h file */
246 #if defined(SOC_AM273X) || defined(SOC_AWR294X) || defined(SOC_AM263X) || defined(SOC_AM263PX) || defined(SOC_AM261X)
247 
248 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID)
249 
250 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID)
251 
252 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID)
253 
254 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID)
255 
256 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID)
257 
258 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID)
259 
260 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
261 #endif
262 
263 #if defined(SOC_AM64X) || defined(SOC_AM243X)
264 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK0_RAM_ID)
265 
266 #define SDL_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_ATCM0_BANK1_RAM_ID)
267 
268 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK0_RAM_ID)
269 
270 #define SDL_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B0TCM0_BANK1_RAM_ID)
271 
272 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK0_RAM_ID)
273 
274 #define SDL_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_PULSAR_LITE_B1TCM0_BANK1_RAM_ID)
275 
276 #define SDL_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID (SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID)
277 #endif
278 
290 typedef enum {
291  SDL_ECC_AGGR_TYPE_INJECT_ONLY = 1,
293  SDL_ECC_AGGR_TYPE_FULL_FUNCTION = 2,
295 } SDL_ECC_AggregatorType;
296 
297 
303 typedef enum {
305  SDL_INJECT_ECC_NO_ERROR = 0,
307  SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1,
309  SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2,
311  SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE = 3,
313  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE = 4,
315  SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT = 5,
317  SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT = 6,
319  SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT = 7,
321  SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
322 } SDL_ECC_InjectErrorType;
323 
324 
329 typedef enum {
330  SDL_ECC_RAM_ID_TYPE_WRAPPER = 0,
332  SDL_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
334 } SDL_ECC_RamIdType;
335 
341 typedef uint32_t SDL_ECC_MemSubType;
342 
348 typedef uint32_t SDL_ECC_MemType;
349 
353 typedef void (*SDL_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
354 
356 typedef void (*SDL_ECC_VIMDEDVector_t) (void);
357 
367 typedef struct SDL_ECC_InitConfig_s
368 {
369  uint32_t numRams;
372  SDL_ECC_MemSubType *pMemSubTypeList;
374 } SDL_ECC_InitConfig_t;
375 
380 typedef struct SDL_ECC_InjectErrorConfig_s
381 {
382  uint32_t *pErrMem;
384  uint32_t flipBitMask;
386  uint32_t chkGrp;
388 } SDL_ECC_InjectErrorConfig_t;
389 
394 typedef struct SDL_ECC_ErrorInfo_s
395 {
396  SDL_ECC_MemType eccMemType;
398  SDL_ECC_MemSubType memSubType;
400  SDL_Ecc_AggrIntrSrc intrSrc;
402  uint32_t bitErrCnt;
404  uint32_t injectBitErrCnt;
406  uint32_t bitErrorGroup;
408  uint64_t bitErrorOffset;
410 } SDL_ECC_ErrorInfo_t;
411 
427 int32_t SDL_ECC_initEsm (const SDL_ESM_Inst esmInstType);
428 
438 int32_t SDL_ECC_init (SDL_ECC_MemType eccMemType,
439  const SDL_ECC_InitConfig_t *pECCInitConfig);
440 
451 int32_t SDL_ECC_initMemory (SDL_ECC_MemType eccMemType,
452  SDL_ECC_MemSubType memSubType);
453 
467 int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType,
468  SDL_ECC_MemSubType memSubType,
469  SDL_ECC_InjectErrorType errorType,
470  const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig,
471  uint32_t selfTestTimeOut);
472 
485 int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType,
486  SDL_ECC_MemSubType memSubType,
487  SDL_ECC_InjectErrorType errorType,
488  const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig);
489 
499 int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType,
500  SDL_ECC_staticRegs *pStaticRegs);
501 
513 int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType,
514  SDL_Ecc_AggrIntrSrc intrSrc,
515  SDL_ECC_ErrorInfo_t *pErrorInfo);
516 
526 int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType,
527  SDL_Ecc_AggrIntrSrc intrSrc);
528 
542 int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc,
543  SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType);
544 
558 int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType,
559  SDL_Ecc_AggrIntrSrc intrSrc,
560  SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents);
561 
578 void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType,
579  uint32_t errorSrc,
580  uint32_t address,
581  uint32_t ramId,
582  uint64_t bitErrorOffset,
583  uint32_t bitErrorGroup);
584 #if defined(SOC_AM263X) || defined(SOC_AM263PX) || defined(SOC_AM261X)
585 
595 int32_t SDL_ECC_tcmParity(SDL_ECC_MemType eccMemType,
596  SDL_ECC_MemSubType memSubType,
597  uint32_t bitValue);
605 int32_t SDL_cleartcmStatusRegs(uint32_t clearVal);
606 #endif
607 #if defined(SOC_AM273X)|| defined(SOC_AWR294X)
608 
617 int32_t SDL_ECC_tcmParity(SDL_ECC_MemSubType memSubType,
618  uint32_t bitValue);
619 
620 /***********************************************************************
621  *
622  * \brief DSS L2 parity init
623  *
624  * \param1 void
625  * @return void
626  **********************************************************************/
627 void SDL_ECC_dss_l2_parity_init(void);
628 
629 /***********************************************************************
630  *
631  * \brief DSS L2 parity error inject
632  *
633  * \param1 injectError : single bit inject for parity error
634  * \param2 injectErrAdd: Inject memory address
635  * \param3 value : Initial value before injecting
636  * @return void
637  **********************************************************************/
638 void SDL_ECC_dss_l2_parity_errorInject(uint32_t injectError, uint32_t injectErrAdd, uint32_t value);
639 
640 /***********************************************************************
641  *
642  * \brief The single-bit error correction and double-bit error
643  * detection errors from the memories of L1 and L2 using EDC
644  * Mask and FLG registers
645  *
646  * \param1 exception_mask_flag : Register value used to enable
647  * propagation of particular exceptions
648  * @return void
649  **********************************************************************/
650 void SDL_ECC_DSP_Aggregated_EDC_Errors(uint32_t exception_mask_flag);
651 
652 /***********************************************************************
653  *
654  * \brief EDC Command Enable for L1P memory
655  *
656  * \param1 void
657  * @return SDL_PASS or SDL_EFAIL
658  **********************************************************************/
659 int32_t SDL_ECC_dss_l1p_edc_CMD_EN(void);
660 
661 /***********************************************************************
662  *
663  * \brief EDC Command Suspend for L1P memory
664  *
665  * \param1 void
666  * @return SDL_PASS or SDL_EFAIL
667  **********************************************************************/
668 int32_t SDL_ECC_dss_l1p_CMD_SUSP(void);
669 
670 /***********************************************************************
671  *
672  * \brief EDC Command Enable for L2 memory
673  *
674  * \param1 void
675  * @return SDL_PASS or SDL_EFAIL
676  **********************************************************************/
677 int32_t SDL_ECC_dss_l2_edc_CMD_EN(void);
678 
679 /***********************************************************************
680  *
681  * \brief EDC Command Suspend for L2 memory
682  *
683  * \param1 void
684  * @return SDL_PASS or SDL_EFAIL
685  **********************************************************************/
686 int32_t SDL_ECC_dss_l2_CMD_SUSP(void);
687 
688 /***********************************************************************
689  *
690  * \brief IDMA 1 Transfer function
691  *
692  * \param1 srcAddr : Source address of the IDMA 1 transfer
693  * \param2 destAddr: Destination address of the IDMA 1 transfer
694  *
695  * @return void
696  **********************************************************************/
697 void SDL_ECC_IDMA1_transfer(uint32_t srcAddr, uint32_t destAddr);
698 
699 #endif
700 
701 
712 int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType,
713  uint32_t bitValue,
714  uint32_t paramregvalue,
715  uint32_t regval);
716 
717 #if defined(SOC_AM263PX) || defined(SOC_AM261X)
718 
723 void SDL_ECC_enableTMUROMParity(void);
724 
731 void SDL_ECC_enableTMUROMParityForceError(void);
732 
739 void SDL_ECC_disableTMUROMParity(void);
740 
747 void SDL_ECC_disableTMUROMParityErrorForce(void);
748 
755 void SDL_ECC_clearTMUROMParityError(void);
756 
757 #endif
758 
762 #ifdef __cplusplus
763 }
764 #endif /* extern "C" */
765 
766 #endif /* SDL_ECC_H_ */
SDL_ESM_Inst
SDL_ESM_Inst
Definition: sdl_esm_soc.h:53
SDL_ECC_InitConfig_t
Definition: sdl_ecc.h:368
SDL_ECC_initMemory
int32_t SDL_ECC_initMemory(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType)
Initializes Memory to be ready for ECC error detection. Assumes ECC is already enabled.
SDL_ECC_ErrorInfo_t::memSubType
SDL_ECC_MemSubType memSubType
Definition: sdl_ecc.h:398
SDL_ECC_InitConfig_t::numRams
uint32_t numRams
Definition: sdl_ecc.h:369
SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_ONCE
Definition: sdl_ecc.h:309
SDL_ECC_injectError
int32_t SDL_ECC_injectError(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig)
Injects ECC error at specified location Assumes ECC is already enabled.
SDL_ECC_ackIntr
int32_t SDL_ECC_ackIntr(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc)
Acknowledge the ECC interrupt.
SDL_ECC_InjectErrorConfig_t::chkGrp
uint32_t chkGrp
Definition: sdl_ecc.h:386
SDL_Ecc_AggrEDCErrorSubType
uint32_t SDL_Ecc_AggrEDCErrorSubType
This enumerator defines the types of possible EDC errors.
Definition: V1/sdl_ip_ecc.h:190
instance
uint8_t instance
Definition: tisci_dkek.h:1
SDL_ECC_getStaticRegisters
int32_t SDL_ECC_getStaticRegisters(SDL_ECC_MemType eccMemType, SDL_ECC_staticRegs *pStaticRegs)
Gets the static registers for the specified ECC instance.
SDL_ECC_AGGR_TYPE_INJECT_ONLY
@ SDL_ECC_AGGR_TYPE_INJECT_ONLY
Definition: sdl_ecc.h:291
SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE
Definition: sdl_ecc.h:311
SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_ONCE
Definition: sdl_ecc.h:307
SDL_ECC_selfTest
int32_t SDL_ECC_selfTest(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_ECC_InjectErrorType errorType, const SDL_ECC_InjectErrorConfig_t *pECCErrorConfig, uint32_t selfTestTimeOut)
Runs self test by injecting and error and monitor response Assumes ECC is already enabled.
SDL_ECC_ErrorInfo_t::bitErrorGroup
uint32_t bitErrorGroup
Definition: sdl_ecc.h:406
SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE
Definition: sdl_ecc.h:313
SDL_ECC_ErrorInfo_t::intrSrc
SDL_Ecc_AggrIntrSrc intrSrc
Definition: sdl_ecc.h:400
SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT
Definition: sdl_ecc.h:315
sdl_common.h
Header file contains enumerations, structure definitions and function declarations for SDL COMMON int...
SDL_ECC_InjectErrorConfig_t
Definition: sdl_ecc.h:381
SDL_INJECT_ECC_NO_ERROR
@ SDL_INJECT_ECC_NO_ERROR
Definition: sdl_ecc.h:305
value
uint32_t value
Definition: tisci_otp_revision.h:2
sdl_ip_ecc.h
SDL_ECC_InjectErrorConfig_t::pErrMem
uint32_t * pErrMem
Definition: sdl_ecc.h:382
SDL_ECC_staticRegs
This structure contains the static register group for Ecc aggregator used by the SDL_ecc_aggrReadStat...
Definition: V1/sdl_ip_ecc.h:310
SDL_ECC_AGGR_TYPE_FULL_FUNCTION
@ SDL_ECC_AGGR_TYPE_FULL_FUNCTION
Definition: sdl_ecc.h:293
SDL_ECC_InjectErrorType
SDL_ECC_InjectErrorType
ECC Inject error types.
Definition: sdl_ecc.h:303
SDL_ECC_initEsm
int32_t SDL_ECC_initEsm(const SDL_ESM_Inst esmInstType)
Initializes an module for usage with ECC module.
SDL_ECC_ErrorInfo_t::bitErrorOffset
uint64_t bitErrorOffset
Definition: sdl_ecc.h:408
SDL_ECC_InjectErrorConfig_t::flipBitMask
uint32_t flipBitMask
Definition: sdl_ecc.h:384
SDL_ECC_AggregatorType
SDL_ECC_AggregatorType
Definition: sdl_ecc.h:290
SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT
Definition: sdl_ecc.h:317
SDL_ECC_RAM_ID_TYPE_INTERCONNECT
@ SDL_ECC_RAM_ID_TYPE_INTERCONNECT
Definition: sdl_ecc.h:332
SDL_ECC_VIMDEDVector_t
void(* SDL_ECC_VIMDEDVector_t)(void)
Definition: sdl_ecc.h:356
SDL_Ecc_AggrIntrSrc
uint32_t SDL_Ecc_AggrIntrSrc
This enumerator defines the types of possible ECC errors.
Definition: V1/sdl_ip_ecc.h:181
SDL_ECC_getESMErrorInfo
int32_t SDL_ECC_getESMErrorInfo(SDL_ESM_Inst instance, uint32_t intSrc, SDL_ECC_MemType *eccMemType, SDL_Ecc_AggrIntrSrc *intrSrcType)
Retrieves the ECC error information for the specified ESM error. If it isn't an ECC error or the ECC ...
SDL_ECC_ErrorInfo_t
Definition: sdl_ecc.h:395
SDL_ECC_InitConfig_t::pMemSubTypeList
SDL_ECC_MemSubType * pMemSubTypeList
Definition: sdl_ecc.h:372
SDL_ECC_MemSubType
uint32_t SDL_ECC_MemSubType
This enumerator indicate ECC memory Sub Type.
Definition: sdl_ecc.h:341
SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:319
SDL_ECC_clearNIntrPending
int32_t SDL_ECC_clearNIntrPending(SDL_ECC_MemType eccMemType, SDL_ECC_MemSubType memSubType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_Ecc_AggrEDCErrorSubType subType, uint32_t numEvents)
Clears N pending interrupts for the specified memtype, subtype and interrupt source.
SDL_ECC_ErrorInfo_t::injectBitErrCnt
uint32_t injectBitErrCnt
Definition: sdl_ecc.h:404
SDL_ECC_getErrorInfo
int32_t SDL_ECC_getErrorInfo(SDL_ECC_MemType eccMemType, SDL_Ecc_AggrIntrSrc intrSrc, SDL_ECC_ErrorInfo_t *pErrorInfo)
Retrieves the ECC error information for the specified memtype and interrupt source.
SDL_ECC_ErrorInfo_t::bitErrCnt
uint32_t bitErrCnt
Definition: sdl_ecc.h:402
SDL_ECC_ErrorInfo_t::eccMemType
SDL_ECC_MemType eccMemType
Definition: sdl_ecc.h:396
SDL_ECC_applicationCallbackFunction
void SDL_ECC_applicationCallbackFunction(SDL_ECC_MemType eccMemType, uint32_t errorSrc, uint32_t address, uint32_t ramId, uint64_t bitErrorOffset, uint32_t bitErrorGroup)
Application provided external callback function for ECC handling Called inside the reference function...
SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT
@ SDL_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT
Definition: sdl_ecc.h:321
SDL_ECC_RamIdType
SDL_ECC_RamIdType
Definition: sdl_ecc.h:329
SDL_ECC_RAM_ID_TYPE_WRAPPER
@ SDL_ECC_RAM_ID_TYPE_WRAPPER
Definition: sdl_ecc.h:330
SDL_ECC_MemType
uint32_t SDL_ECC_MemType
This enumerator indicate ECC memory type.
Definition: sdl_ecc.h:348
SDL_ECC_init
int32_t SDL_ECC_init(SDL_ECC_MemType eccMemType, const SDL_ECC_InitConfig_t *pECCInitConfig)
Initializes ECC module for ECC detection.
SDL_ECC_ErrorCallback_t
void(* SDL_ECC_ErrorCallback_t)(uint32_t errorSrc, uint32_t address)
Definition: sdl_ecc.h:353
SDL_ECC_tpccParity
int32_t SDL_ECC_tpccParity(SDL_ECC_MemType eccMemType, uint32_t bitValue, uint32_t paramregvalue, uint32_t regval)
Injects TPCC Parity error.