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AM64x MCU+ SDK
10.00.00
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Go to the documentation of this file.
41 #ifndef SCICLIENT_FMWMSGPARAMS_H_
42 #define SCICLIENT_FMWMSGPARAMS_H_
59 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
69 #define SCICLIENT_FIRMWARE_ABI_MAJOR (4U)
74 #define SCICLIENT_FIRMWARE_ABI_MINOR (0U)
84 #define SCICLIENT_CONTEXT_R5_0_SEC_0 (0U)
86 #define SCICLIENT_CONTEXT_R5_0_NONSEC_0 (1U)
88 #define SCICLIENT_CONTEXT_R5_0_SEC_1 (2U)
90 #define SCICLIENT_CONTEXT_R5_0_NONSEC_1 (3U)
92 #define SCICLIENT_CONTEXT_A53_SEC_0 (4U)
94 #define SCICLIENT_CONTEXT_A53_NONSEC_0 (5U)
96 #define SCICLIENT_CONTEXT_A53_NONSEC_1 (6U)
98 #define SCICLIENT_CONTEXT_A53_NONSEC_2 (7U)
100 #define SCICLIENT_CONTEXT_M4_NONSEC_0 (8U)
102 #define SCICLIENT_CONTEXT_R5_1_SEC_0 (9U)
104 #define SCICLIENT_CONTEXT_R5_1_NONSEC_0 (10U)
106 #define SCICLIENT_CONTEXT_R5_1_SEC_1 (11U)
108 #define SCICLIENT_CONTEXT_R5_1_NONSEC_1 (12U)
110 #define SCICLIENT_CONTEXT_ICSSG_NONSEC_0 (13U)
112 #define SCICLIENT_CONTEXT_M4_SEC_0 (14U)
115 #define SCICLIENT_CONTEXT_MAX_NUM (15U)
126 #define SCICLIENT_PROCID_A53_CL0_C0 (0x20U)
128 #define SCICLIENT_PROCID_A53_CL0_C1 (0x21U)
130 #define SCICLIENT_PROCID_R5_CL0_C0 (0x01U)
132 #define SCICLIENT_PROCID_R5_CL0_C1 (0x02U)
134 #define SCICLIENT_PROCID_R5_CL1_C0 (0x06U)
136 #define SCICLIENT_PROCID_R5_CL1_C1 (0x07U)
138 #define SCICLIENT_PROCID_MCU_M4FSS0_C0 (0x18U)
144 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
145 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
146 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
147 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
153 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
154 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
155 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
156 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
157 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
185 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (20U)
186 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (32U)
187 #define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START (0U)
188 #define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)
189 #define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)
190 #define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)
191 #define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)
192 #define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)
193 #define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)
194 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)
195 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)
196 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)
197 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)
198 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)
199 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)
200 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)
201 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)
202 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)