Introduction

Macros
#define	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)

#define	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)

#define	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)

#define	SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)

#define	SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)

#define	SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (27U)

#define	SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)

#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)

#define	SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)

#define	SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)

#define	SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)

#define	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)

#define	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)

#define	SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)

#define	SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES (4U)

#define	SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

#define	SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES (2U)

#define	SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

#define	SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

#define	SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

#define	SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

#define	SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (3U)

#define	SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)

#define	SDL_ECC_Base_Address_TOTAL_ENTRIES (40U)

Macro Definition Documentation

◆ SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES (27U)

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES (27U)

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES

#define SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES (24U)

◆ SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)

◆ SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)

◆ SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (27U)

◆ SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)

◆ SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (3U)

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (4U)

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)

◆ SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)

◆ SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)

◆ SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES

#define SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES (4U)

◆ SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES

#define SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

#define SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES

#define SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES (2U)

◆ SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

◆ SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

◆ SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

◆ SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)

◆ SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

#define SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES (3U)

◆ SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

#define SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)

◆ SDL_ECC_Base_Address_TOTAL_ENTRIES

#define SDL_ECC_Base_Address_TOTAL_ENTRIES (40U)

Variable Documentation

◆ SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x00000000u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries[SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries[SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries

const SDL_MemConfig_t SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries[SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC

◆ SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR

◆ SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU0_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_RTU1_PDSP_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX0_IRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_ID, 0u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_RAM_SIZE, 4u,
      SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP_TX1_IRAM_ECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR

◆ SDL_DMASS0_DMSS_AM64_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_DMASS0_DMSS_AM64_ECCAGGR_MemEntries[SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_DMASS0_DMSS_AM64_ECCAGGR

◆ SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70080000u,
      SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR

◆ SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR

◆ SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P0_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P1_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_RX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_P2_TX_FIFO_ROW_WIDTH, ((bool)false) },
    { SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
      SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR

◆ SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries[SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
    { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

◆ SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_MemEntries[SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_RAM_ID, 0u,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_RAM_SIZE, 4u,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_GICSS0_GIC500SS_1_2_ECC_AGGR

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_MemEntries[SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_MemEntries[SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_ROW_WIDTH, ((bool)false) },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID, 0u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_SIZE, 4u,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries[SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL RAM ID

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries[SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0 RAM ID

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries[SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0 RAM ID

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries[SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0 RAM ID

◆ SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

◆ SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_MemEntries[SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR

◆ SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_MemEntries[SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
      SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
      SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR

◆ SDL_DMSC0_DMSC_LITE_MemEntries

const SDL_MemConfig_t SDL_DMSC0_DMSC_LITE_MemEntries[SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_RAM_ID, 0u,
      SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_RAM_SIZE, 4u,
      SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_RAM_ID, 0u,
      SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_RAM_SIZE, 4u,
      SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_DMSC0_DMSC_LITE_IM_RAMECC_RAM_ID, 0u,
      SDL_DMSC0_DMSC_LITE_IM_RAMECC_RAM_SIZE, 4u,
      SDL_DMSC0_DMSC_LITE_IM_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_DMSC0_DMSC_LITE_SR_RAMECC_RAM_ID, 0u,
      SDL_DMSC0_DMSC_LITE_SR_RAMECC_RAM_SIZE, 4u,
      SDL_DMSC0_DMSC_LITE_SR_RAMECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_DMSC0_DMSC_LITE

◆ SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70040000u,
      SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70000000u,
      SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x700C0000u,
      SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70140000u,
      SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70100000u,
      SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x701C0000u,
      SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MemEntries[SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID, 0x70180000u,
      SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_SIZE, 4u,
      SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR

◆ SDL_ECC_AGGR1_MemEntries

const SDL_MemConfig_t SDL_ECC_AGGR1_MemEntries[SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR1_IMAILBOX8_MAIN_0__RAMECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_ECC_AGGR1

◆ SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_groupEntries[SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_10_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_11_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_GROUP_12_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC RAM ID

◆ SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

◆ SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries[SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC RAM ID

◆ SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries[SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC RAM ID

◆ SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries[SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
    { SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC RAM ID

◆ SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x020718000u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

◆ SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

◆ SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x020708000u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

◆ SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries

const SDL_GrpChkConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS RAM ID

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries

const SDL_MemConfig_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID, 0u,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_MemEntries

const SDL_MemConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_MemEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_ID, 0x05000000u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_ECC_ROW_WIDTH, ((bool)true) },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_ID, 0x05040000u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_RAM_SIZE, 4u,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_ECC_ROW_WIDTH, ((bool)true) },
}

This structure holds the memory config for each memory subtype SDL_MCU_M4FSS0_BLAZAR_ECC

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS]

static

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0 RAM ID

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries

const SDL_GrpChkConfig_t SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries[SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS]

static

Initial value:

=
{
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_0_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_1_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_2_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_3_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_4_WIDTH },
    { SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
      SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_GROUP_5_WIDTH },
}

This structure holds the ECC interconnect Group Checker information for

SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL RAM ID

◆ SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_MemEntries[SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR

◆ SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_MemEntries[SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR

◆ SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_MemEntries[SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR

◆ SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_MemEntries

const SDL_MemConfig_t SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_MemEntries[SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]

static

This structure holds the memory config for each memory subtype SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR

◆ SDL_ECC_AGGR0_MemEntries

const SDL_MemConfig_t SDL_ECC_AGGR0_MemEntries[SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ROW_WIDTH, ((bool)false) },
    { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_RAM_ID, 0u,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_RAM_SIZE, 4u,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_ECC_AGGR0

◆ SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_MemEntries

const SDL_MemConfig_t SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_MemEntries[SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]

static

Initial value:

=
{
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)false) },
}

This structure holds the memory config for each memory subtype SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR

◆ SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable[SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
      SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable

const SDL_RAMIdEntry_t SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable[SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC

◆ SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR

◆ SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR

◆ SDL_DMASS0_DMSS_AM64_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_DMASS0_DMSS_AM64_ECCAGGR_RamIdTable[SDL_DMASS0_DMSS_AM64_ECCAGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_DMASS0_DMSS_AM64_ECCAGGR

◆ SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR

◆ SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable[SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
      SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR

◆ SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable[SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR

◆ SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable[SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
      SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_EMMCSD4SS_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_EMMCSD4SS_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

◆ SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RamIdTable[SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ICB_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_ITE_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_RAM_ID,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_INJECT_TYPE,
      SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_LPI_RAMECC_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_GICSS0_GIC500SS_1_2_ECC_AGGR

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RamIdTable[SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXIMFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_DIBRAM_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_PCIE_G2X1_64_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RamIdTable[SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_PNPFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RXCPLFIFO_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_RPLYBUF_ECC_TYPE,
      0u,
      NULL },
    { SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_RAM_ID,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_INJECT_TYPE,
      SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_PCIE_G2X1_64_CORE_DBN_WRAP_RAMS_AXISRODR_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable[SDL_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries },
    { SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
      SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_VTM0_K3VTM_N16FFC_ECCAGGR

◆ SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable[SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR

◆ SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RamIdTable[SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_RAM_ID,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F0_TPRAM_60X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_RAM_ID,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_TF0_F1_TPRAM_60X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_PDMA_AM64_MAIN1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR

◆ SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RamIdTable[SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
      SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
      SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_USB3P0SS64_16FFC_USB3P0SS64_CORE_USB3P0_KSBUS_AXI2VBUSM_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR

◆ SDL_DMSC0_DMSC_LITE_RamIdTable

const SDL_RAMIdEntry_t SDL_DMSC0_DMSC_LITE_RamIdTable[SDL_DMSC0_DMSC_LITE_NUM_RAMS]

static

Initial value:

=
{
    { SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_RAM_ID,
      SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_INJECT_TYPE,
      SDL_DMSC0_DMSC_LITE_ISRAM1_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_RAM_ID,
      SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_INJECT_TYPE,
      SDL_DMSC0_DMSC_LITE_ISRAM0_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMSC0_DMSC_LITE_IM_RAMECC_RAM_ID,
      SDL_DMSC0_DMSC_LITE_IM_RAMECC_INJECT_TYPE,
      SDL_DMSC0_DMSC_LITE_IM_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_DMSC0_DMSC_LITE_SR_RAMECC_RAM_ID,
      SDL_DMSC0_DMSC_LITE_SR_RAMECC_INJECT_TYPE,
      SDL_DMSC0_DMSC_LITE_SR_RAMECC_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_DMSC0_DMSC_LITE

◆ SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR

◆ SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RamIdTable[SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_RAM_ID,
      SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_INJECT_TYPE,
      SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MSRAM32KX64E_MSRAM0_ECC0_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR

◆ SDL_ECC_AGGR1_RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_AGGR1_RamIdTable[SDL_ECC_AGGR1_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_ECC_AGGR1

◆ SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR

◆ SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
      SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_RAM_ID,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_EMMC8SS_16FFC_SDHC_WRAP_TXMEM_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable

const SDL_RAMIdEntry_t SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable[SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS]

static

Initial value:

=
{
    { SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_RAM_ID,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_INJECT_TYPE,
      SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_EMMC8SS_16FFC_SDHC_WRAP_RXMEM_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable

const SDL_RAMIdEntry_t SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable[SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_MCU_M4FSS0_BLAZAR_ECC

◆ SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RamIdTable[SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR

◆ SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RamIdTable[SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR

◆ SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RamIdTable[SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR

◆ SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RamIdTable[SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS]

static

This structure holds the list of Ram Ids for each memory subtype in SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR

◆ SDL_ECC_AGGR0_RamIdTable

const SDL_RAMIdEntry_t SDL_ECC_AGGR0_RamIdTable[SDL_ECC_AGGR0_NUM_RAMS]

static

Initial value:

=
{
    { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_RAM_ID,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_INJECT_TYPE,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__TIMER_FSM_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_RAM_ID,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_INJECT_TYPE,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__REPROG_FSM_RAMECC_ECC_TYPE,
      0u,
      NULL },
    { SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_RAM_ID,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_INJECT_TYPE,
      SDL_ECC_AGGR0_ITIMER_MGR1024_MAIN_0__EFIFO_RAMECC_ECC_TYPE,
      0u,
      NULL },
}

This structure holds the list of Ram Ids for each memory subtype in SDL_ECC_AGGR0

◆ SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RamIdTable

const SDL_RAMIdEntry_t SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RamIdTable[SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_NUM_RAMS]

static

Initial value:

=
{
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
    { SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_INJECT_TYPE,
      SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_PDMA_AM64_MAIN0_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ECC_TYPE,
      0u,
      NULL },
}

Introduction

Macros

Macro Definition Documentation

◆ SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES

◆ SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

◆ SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES

◆ SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES

◆ SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES

◆ SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES

◆ SDL_ECC_Base_Address_TOTAL_ENTRIES

Variable Documentation

◆ SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0

◆ SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries

This structure holds the memory config for each memory subtype SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC

◆ SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR

◆ SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR

◆ SDL_DMASS0_DMSS_AM64_ECCAGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_DMASS0_DMSS_AM64_ECCAGGR

◆ SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR

◆ SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR

◆ SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR

◆ SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM

◆ SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries

This structure holds the memory config for each memory subtype SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM

◆ SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_GICSS0_GIC500SS_1_2_ECC_AGGR

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR

◆ SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_MemEntries

This structure holds the memory config for each memory subtype SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries

SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL RAM ID

◆ SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries