Enet UDMA module APIs

Introduction

Sub Modules
	UDMA CPPI Protocol Specific Info

Typedefs
typedef struct EnetUdma_DmaDescQ_s *	EnetUdma_DmaDescQHandle
	Opaque handle to Enet UDMA descriptor queue. More...
typedef void(*	EnetDma_PktNotifyCb) (void *cbArg)
	Function pointer type for packet notify call back. More...

Enet UDMA instance configuration
Configuration macros for Enet UDMA module.
#define	ENET_UDMA_HPD_SIZE   (128U)
	Enet UDMA HPD packet size. More...
#define	ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE   (16U)
	Extended Packet Info Block size. More...
#define	ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE   (16U)
	Extended Packet Info Block size. More...
#define	ENET_UDMA_PKT_DESC_RESERVED_SIZE
	Extended Packet Info Block size. More...
#define	ENET_UDMA_RING_MEM_SIZE   (sizeof(uint64_t))
	UDMA ring single element size. More...
#define	ENET_UDMA_RXMTU_ALIGN   (1U << 5U)
	Enet UDMA RX MTU alignment. The RxFlow MTU must be aligned to this value. More...
#define	ENET_UDMA_CPSW_MAX_SG_LIST   (4U)
#define	ENET_UDMA_CPSW_HOSTPKTDESC_INDEX   (0U)
	Index of the Host Packet(first packet) descriptor. More...
#define	ENET_UDMA_CPSW_HOSTBUFDESC_INDEX   (1U)
	Index of the first Host Buffer descriptor. More...
#define	ENET_UDMA_CPSW_MAX_HOSTBUFDESC_COUNT   (ENET_UDMA_CPSW_MAX_SG_LIST - ENET_UDMA_CPSW_HOSTBUFDESC_INDEX)
#define	ENET_UDMA_HPD_SRC_TAG_LOW_MASK   (0xFF)
	Source tag low mask of descriptor (used to get packet's received port number) More...
#define	ENET_UDMA_DESC_ALIGNMENT   (64U)
	UDMA descriptor address alignment requirement. More...
#define	ENET_UDMA_ICSSG_LRE_TX_OFFLOAD_DISABLE   (0U)
	ICSSG Disable TX Offload for LRE Mode (HSR/PRP) More...
#define	ENET_UDMA_ICSSG_LRE_TX_OFFLOAD_ENABLE   (1U)
	ICSSG Enable TX Offload for LRE Mode (HSR/PRP) More...
#define	ENET_UDMA_ICSSG_LRE_RX_OFFLOAD_DISABLE   (0U)
	ICSSG Disable RX Offload for LRE Mode (HSR/PRP) More...
#define	ENET_UDMA_ICSSG_LRE_RX_OFFLOAD_ENABLE   (1U)
	ICSSG Enable RX Offload for LRE Mode (HSR/PRP) More...

Macro Definition Documentation

ENET_UDMA_HPD_SIZE

#define ENET_UDMA_HPD_SIZE   (128U)

Enet UDMA HPD packet size.

ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE

#define ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE   (16U)

Extended Packet Info Block size.

ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE

#define ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE   (16U)

Extended Packet Info Block size.

ENET_UDMA_PKT_DESC_RESERVED_SIZE

#define ENET_UDMA_PKT_DESC_RESERVED_SIZE

Value:

                                           ( ENET_UDMA_HPD_SIZE - \
                                           sizeof(CSL_UdmapCppi5HMPD) - \
                                           (ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE + \
                                           ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE))

Extended Packet Info Block size.

ENET_UDMA_RING_MEM_SIZE

#define ENET_UDMA_RING_MEM_SIZE   (sizeof(uint64_t))

UDMA ring single element size.

ENET_UDMA_RXMTU_ALIGN

#define ENET_UDMA_RXMTU_ALIGN   (1U << 5U)

Enet UDMA RX MTU alignment. The RxFlow MTU must be aligned to this value.

As per UDMAP spec: "RX Packet Size Threshold 0: This value is left shifted by 5 bits and compared against the packet size to determine which free descriptor queue should be used for the SOP buffer in the packet" The value programmed is hence supposed to be 32 bit aligned. Programming non aligned values will result in truncation and expected MTU size will not be programmed. For example setting MTU size of 1518 (required MTU size) results in actual value of 1504 getting programmed resulting in packet drop for frames of size 1504 - 1518 which the app expects to less than the programmed MTU based on the param passed. Refer ksdma_udmap spec section 4.4.2.6 for more details

ENET_UDMA_CPSW_MAX_SG_LIST

#define ENET_UDMA_CPSW_MAX_SG_LIST   (4U)

Maximum number of scatter gather segments supported in a packet

ENET_UDMA_CPSW_HOSTPKTDESC_INDEX

#define ENET_UDMA_CPSW_HOSTPKTDESC_INDEX   (0U)

Index of the Host Packet(first packet) descriptor.

ENET_UDMA_CPSW_HOSTBUFDESC_INDEX

#define ENET_UDMA_CPSW_HOSTBUFDESC_INDEX   (1U)

Index of the first Host Buffer descriptor.

ENET_UDMA_CPSW_MAX_HOSTBUFDESC_COUNT

#define ENET_UDMA_CPSW_MAX_HOSTBUFDESC_COUNT   (ENET_UDMA_CPSW_MAX_SG_LIST - ENET_UDMA_CPSW_HOSTBUFDESC_INDEX)

Count of Host Buffer Descriptor

ENET_UDMA_HPD_SRC_TAG_LOW_MASK

#define ENET_UDMA_HPD_SRC_TAG_LOW_MASK   (0xFF)

Source tag low mask of descriptor (used to get packet's received port number)

ENET_UDMA_DESC_ALIGNMENT

#define ENET_UDMA_DESC_ALIGNMENT   (64U)

UDMA descriptor address alignment requirement.

ENET_UDMA_ICSSG_LRE_TX_OFFLOAD_DISABLE

#define ENET_UDMA_ICSSG_LRE_TX_OFFLOAD_DISABLE   (0U)

ICSSG Disable TX Offload for LRE Mode (HSR/PRP)

ENET_UDMA_ICSSG_LRE_TX_OFFLOAD_ENABLE

#define ENET_UDMA_ICSSG_LRE_TX_OFFLOAD_ENABLE   (1U)

ICSSG Enable TX Offload for LRE Mode (HSR/PRP)

ENET_UDMA_ICSSG_LRE_RX_OFFLOAD_DISABLE

#define ENET_UDMA_ICSSG_LRE_RX_OFFLOAD_DISABLE   (0U)

ICSSG Disable RX Offload for LRE Mode (HSR/PRP)

ENET_UDMA_ICSSG_LRE_RX_OFFLOAD_ENABLE

#define ENET_UDMA_ICSSG_LRE_RX_OFFLOAD_ENABLE   (1U)

ICSSG Enable RX Offload for LRE Mode (HSR/PRP)

Typedef Documentation

EnetUdma_DmaDescQHandle

typedef struct EnetUdma_DmaDescQ_s* EnetUdma_DmaDescQHandle

Opaque handle to Enet UDMA descriptor queue.

EnetDma_PktNotifyCb

typedef void(* EnetDma_PktNotifyCb) (void *cbArg)

Function pointer type for packet notify call back.

This is called by driver when packet is received on the RX channel or transmission completed from TX channel.