The Windowed Watchdog Timer (WWDT) generates reset after a programmable period, if not serviced within that period. This time-out boundary is configurable, and the windowed feature allows the start time boundary to be configurable. The WWDT can generate an Interrupt, if not serviced within window (Open Window) defined by start time and time-out boundary. Also the WWDT can generate an Interrupt if serviced outside Open Window (within Closed Window). Generation of Interrupt depends on the WWDT Reaction configuration. SDL supports configuration of the watchdog timers. It also supports notification of the error via ESM interrupt. Additionally, APIs for checking the status of the watchdog timer is provided.
The RTI modules include the following main features:
There are 7 RTI Modules in the device – 1 in the MCU domain and 6 in the Main domain
Instances in MCU domain:
1) MCU_RTI0 is dedicated to the MCU cluster (MCU_M4FSS0) in lockstep and when unlocked serves as a Windowed Watchdog for the first M4F CPU core in the MCU domain (MCU_M4FSS0_CORE0).
Instances in Main domain:
1) RTI0 is dedicated to the first A53 CPU core in the A53 cluster (A53SS0_CORE0) 2) RTI1 is dedicated to the second A53 CPU core in the A53 cluster (A53SS0_CORE1) 3) RTI8 is dedicated to the first R5F CPU core in the Main domain (R5FSS0_CORE0) 4) RTI9 is dedicated to the second R5F CPU core in the Main domain (R5FSS0_CORE1) 5) RTI10 is dedicated to the third R5F CPU core in the Main domain (R5FSS1_CORE0) 6) RTI11 is dedicated to the fourth R5F CPU core in the Main domain (R5FSS1_CORE1)
All WWDT instances that are provisioned for a particular CPU core should not be used by any other CPU cores.
The following shows an example of SDL RTI API.
Include the below file to access the APIs
Config an RTI Instance
Verify the config
Read the static registers
Start an RTI Instance
Start an RTI Instance
Config an RTI Instance
Verify the config
Read the static registers
Start an RTI Instance
Start an RTI Instance