AM64x MCU+ SDK  10.00.00
sciclient_irq_rm.c File Reference

Introduction

File containing the AM64x specific interrupt management data for RM.

Variables

uint8_t vint_usage_count_DMASS0_INTAGGR_0 [184] = {0}
 
static struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0 [5U]
 
struct Sciclient_rmIaInst gRmIaInstances [SCICLIENT_RM_IA_NUM_INST]
 
struct Sciclient_rmIrInst gRmIrInstances [SCICLIENT_RM_IR_NUM_INST]
 
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
 
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
 
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
 
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
 
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
 
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
 
const struct Sciclient_rmIrqIf *const tisci_if_CMP_EVENT_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CMP_EVENT_INTROUTER0
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
 
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
 
const struct Sciclient_rmIrqIf *const tisci_if_MAIN_GPIOMUX_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
 
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_MCU_GPIOMUX_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
 
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_EVENT_INTROUTER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0
 
const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
 
const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
 
const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
 
const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
 
const struct Sciclient_rmIrqIf *const tisci_if_CPSW0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CPSW0
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
 
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
 
const struct Sciclient_rmIrqIf *const tisci_if_DMASS0_INTAGGR_0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0
 
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER0
 
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER1
 
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER2
 
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
 
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_TIMER3
 
const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
 
const struct Sciclient_rmIrqIf *const tisci_if_GTC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GTC0
 
const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
 
const struct Sciclient_rmIrqIf GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIO0
 
const struct Sciclient_rmIrqIf GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
 
const struct Sciclient_rmIrqIf GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
 
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPIO1
 
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
 
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
 
const struct Sciclient_rmIrqIf *const tisci_if_MCU_GPIO0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0
 
const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
 
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_GPMC0
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
 
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
 
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
 
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
 
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG1 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1
 
const struct Sciclient_rmIrqIf CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
 
const struct Sciclient_rmIrqIf CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
 
const struct Sciclient_rmIrqIf CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
 
const struct Sciclient_rmIrqIf CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
 
const struct Sciclient_rmIrqIf CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
 
const struct Sciclient_rmIrqIf CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
 
const struct Sciclient_rmIrqIf CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
 
const struct Sciclient_rmIrqIf CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
 
const struct Sciclient_rmIrqIf *const tisci_if_CPTS0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_CPTS0
 
const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
 
const struct Sciclient_rmIrqIf *const tisci_if_EPWM0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EPWM0
 
const struct Sciclient_rmIrqIf EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
 
const struct Sciclient_rmIrqIf *const tisci_if_EPWM3 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EPWM3
 
const struct Sciclient_rmIrqIf EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
 
const struct Sciclient_rmIrqIf *const tisci_if_EPWM6 []
 
static const struct Sciclient_rmIrqNode tisci_irq_EPWM6
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
 
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
 
const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
 
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0 []
 
static const struct Sciclient_rmIrqNode tisci_irq_PCIE0
 
const struct Sciclient_rmIrqNode *const gRmIrqTree []
 
const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])
 

Variable Documentation

◆ vint_usage_count_DMASS0_INTAGGR_0

uint8_t vint_usage_count_DMASS0_INTAGGR_0[184] = {0}

◆ rom_usage_DMASS0_INTAGGR_0

struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[5U]
static
Initial value:
= {
{
.event = 20U,
.cleared = false,
},
{
.event = 21U,
.cleared = false,
},
{
.event = 22U,
.cleared = false,
},
{
.event = 23U,
.cleared = false,
},
{
.event = 30U,
.cleared = false,
},
}

◆ gRmIaInstances

struct Sciclient_rmIaInst gRmIaInstances[SCICLIENT_RM_IA_NUM_INST]
Initial value:
=
{
{
.imap = 0x48100000,
.sevt_offset = 0u,
.n_sevt = 1536u,
.n_vint = 184,
.vint_usage_count = &vint_usage_count_DMASS0_INTAGGR_0[0],
.v0_b0_evt = SCICLIENT_RM_IA_GENERIC_EVT_RESETVAL,
.rom_usage = &rom_usage_DMASS0_INTAGGR_0[0U],
.n_rom_usage = 5,
},
}

◆ gRmIrInstances

struct Sciclient_rmIrInst gRmIrInstances[SCICLIENT_RM_IR_NUM_INST]

◆ CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 48,
}

◆ CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
Initial value:
= {
.lbase = 16,
.len = 8,
.rbase = 48,
}

◆ CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
Initial value:
= {
.lbase = 16,
.len = 8,
.rbase = 48,
}

◆ CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
Initial value:
= {
.lbase = 24,
.len = 8,
.rbase = 48,
}

◆ CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
Initial value:
= {
.lbase = 24,
.len = 8,
.rbase = 48,
}

◆ CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7

const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
Initial value:
= {
.lbase = 32,
.len = 8,
.rbase = 0,
}

◆ tisci_if_CMP_EVENT_INTROUTER0

◆ tisci_irq_CMP_EVENT_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_CMP_EVENT_INTROUTER0
static
Initial value:

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
Initial value:
= {
.lbase = 0,
.len = 16,
.rbase = 32,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
Initial value:
= {
.lbase = 30,
.len = 8,
.rbase = 16,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
Initial value:
= {
.lbase = 16,
.len = 2,
.rbase = 24,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
Initial value:
= {
.lbase = 18,
.len = 6,
.rbase = 4,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
Initial value:
= {
.lbase = 24,
.len = 6,
.rbase = 10,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
Initial value:
= {
.lbase = 38,
.len = 8,
.rbase = 46,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
Initial value:
= {
.lbase = 18,
.len = 6,
.rbase = 4,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
Initial value:
= {
.lbase = 24,
.len = 6,
.rbase = 10,
}

◆ MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53

const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
Initial value:
= {
.lbase = 46,
.len = 8,
.rbase = 46,
}

◆ tisci_if_MAIN_GPIOMUX_INTROUTER0

◆ tisci_irq_MAIN_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0
static
Initial value:

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
Initial value:
= {
.lbase = 0,
.len = 4,
.rbase = 104,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
Initial value:
= {
.lbase = 4,
.len = 4,
.rbase = 0,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 88,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 92,
}

◆ MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99

const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
Initial value:
= {
.lbase = 8,
.len = 4,
.rbase = 96,
}

◆ tisci_if_MCU_MCU_GPIOMUX_INTROUTER0

◆ tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
static
Initial value:

◆ TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
Initial value:
= {
.lbase = 0,
.len = 8,
.rbase = 8,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
Initial value:
= {
.lbase = 8,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
Initial value:
= {
.lbase = 9,
.len = 1,
.rbase = 1,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
Initial value:
= {
.lbase = 10,
.len = 1,
.rbase = 2,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
Initial value:
= {
.lbase = 11,
.len = 1,
.rbase = 3,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
Initial value:
= {
.lbase = 12,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
Initial value:
= {
.lbase = 13,
.len = 1,
.rbase = 1,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
Initial value:
= {
.lbase = 14,
.len = 1,
.rbase = 2,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
Initial value:
= {
.lbase = 15,
.len = 1,
.rbase = 3,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
Initial value:
= {
.lbase = 16,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
Initial value:
= {
.lbase = 17,
.len = 1,
.rbase = 1,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
Initial value:
= {
.lbase = 18,
.len = 1,
.rbase = 2,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
Initial value:
= {
.lbase = 19,
.len = 1,
.rbase = 3,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
Initial value:
= {
.lbase = 20,
.len = 1,
.rbase = 4,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
Initial value:
= {
.lbase = 21,
.len = 1,
.rbase = 5,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
Initial value:
= {
.lbase = 22,
.len = 1,
.rbase = 6,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
Initial value:
= {
.lbase = 23,
.len = 1,
.rbase = 7,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
Initial value:
= {
.lbase = 29,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
Initial value:
= {
.lbase = 30,
.len = 1,
.rbase = 0,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
Initial value:
= {
.lbase = 31,
.len = 1,
.rbase = 1,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
Initial value:
= {
.lbase = 32,
.len = 1,
.rbase = 2,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
Initial value:
= {
.lbase = 33,
.len = 1,
.rbase = 3,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
Initial value:
= {
.lbase = 34,
.len = 1,
.rbase = 4,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
Initial value:
= {
.lbase = 35,
.len = 1,
.rbase = 5,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
Initial value:
= {
.lbase = 36,
.len = 1,
.rbase = 6,
}

◆ TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7

const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
Initial value:
= {
.lbase = 37,
.len = 1,
.rbase = 7,
}

◆ tisci_if_TIMESYNC_EVENT_INTROUTER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMESYNC_EVENT_INTROUTER0[]
Initial value:
= {
}

◆ tisci_irq_TIMESYNC_EVENT_INTROUTER0

const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0
static
Initial value:

◆ CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80

const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 80,
}

◆ CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21

const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 21,
}

◆ CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22

const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 22,
}

◆ CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34

const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 34,
}

◆ tisci_if_CPSW0

◆ tisci_irq_CPSW0

const struct Sciclient_rmIrqNode tisci_irq_CPSW0
static
Initial value:
= {
.n_if = 4,
.p_if = &tisci_if_CPSW0[0],
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
Initial value:
= {
.lbase = 0,
.len = 40,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
Initial value:
= {
.lbase = 72,
.len = 8,
.rbase = 8,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
Initial value:
= {
.lbase = 40,
.len = 32,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
Initial value:
= {
.lbase = 80,
.len = 8,
.rbase = 8,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
Initial value:
= {
.lbase = 40,
.len = 32,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
Initial value:
= {
.lbase = 120,
.len = 8,
.rbase = 8,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
Initial value:
= {
.lbase = 88,
.len = 32,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
Initial value:
= {
.lbase = 128,
.len = 8,
.rbase = 8,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
Initial value:
= {
.lbase = 88,
.len = 32,
.rbase = 64,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
Initial value:
= {
.lbase = 152,
.len = 8,
.rbase = 16,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
Initial value:
= {
.lbase = 160,
.len = 8,
.rbase = 16,
}

◆ DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47

const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
Initial value:
= {
.lbase = 168,
.len = 16,
.rbase = 32,
}

◆ tisci_if_DMASS0_INTAGGR_0

◆ tisci_irq_DMASS0_INTAGGR_0

const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0
static
Initial value:
= {
.n_if = 12,
}

◆ TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0

const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 0,
}

◆ tisci_if_TIMER0

const struct Sciclient_rmIrqIf* const tisci_if_TIMER0[]

◆ tisci_irq_TIMER0

const struct Sciclient_rmIrqNode tisci_irq_TIMER0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER0[0],
}

◆ TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1

const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 1,
}

◆ tisci_if_TIMER1

const struct Sciclient_rmIrqIf* const tisci_if_TIMER1[]

◆ tisci_irq_TIMER1

const struct Sciclient_rmIrqNode tisci_irq_TIMER1
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER1[0],
}

◆ TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2

const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 2,
}

◆ tisci_if_TIMER2

const struct Sciclient_rmIrqIf* const tisci_if_TIMER2[]

◆ tisci_irq_TIMER2

const struct Sciclient_rmIrqNode tisci_irq_TIMER2
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER2[0],
}

◆ TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3

const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 3,
}

◆ tisci_if_TIMER3

const struct Sciclient_rmIrqIf* const tisci_if_TIMER3[]

◆ tisci_irq_TIMER3

const struct Sciclient_rmIrqNode tisci_irq_TIMER3
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_TIMER3[0],
}

◆ GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36

const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 36,
}

◆ tisci_if_GTC0

const struct Sciclient_rmIrqIf* const tisci_if_GTC0[]

◆ tisci_irq_GTC0

const struct Sciclient_rmIrqNode tisci_irq_GTC0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_GTC0[0],
}

◆ GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89

const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
Initial value:
= {
.lbase = 0,
.len = 90,
.rbase = 0,
}

◆ GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198

const struct Sciclient_rmIrqIf GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
Initial value:
= {
.lbase = 90,
.len = 9,
.rbase = 190,
}

◆ tisci_if_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_GPIO0[]

◆ tisci_irq_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_GPIO0
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_GPIO0[0],
}

◆ GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179

const struct Sciclient_rmIrqIf GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
Initial value:
= {
.lbase = 0,
.len = 90,
.rbase = 90,
}

◆ GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188

const struct Sciclient_rmIrqIf GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
Initial value:
= {
.lbase = 90,
.len = 9,
.rbase = 180,
}

◆ tisci_if_GPIO1

const struct Sciclient_rmIrqIf* const tisci_if_GPIO1[]

◆ tisci_irq_GPIO1

const struct Sciclient_rmIrqNode tisci_irq_GPIO1
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_GPIO1[0],
}

◆ MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
Initial value:
= {
.lbase = 0,
.len = 30,
.rbase = 0,
}

◆ MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31

const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
Initial value:
= {
.lbase = 30,
.len = 2,
.rbase = 30,
}

◆ tisci_if_MCU_GPIO0

const struct Sciclient_rmIrqIf* const tisci_if_MCU_GPIO0[]

◆ tisci_irq_MCU_GPIO0

const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0
static
Initial value:
= {
.n_if = 2,
.p_if = &tisci_if_MCU_GPIO0[0],
}

◆ GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29

const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 29,
}

◆ tisci_if_GPMC0

const struct Sciclient_rmIrqIf* const tisci_if_GPMC0[]

◆ tisci_irq_GPMC0

const struct Sciclient_rmIrqNode tisci_irq_GPMC0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_GPMC0[0],
}

◆ PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 25,
}

◆ PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 26,
}

◆ PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 27,
}

◆ PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 28,
}

◆ PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
Initial value:
= {
.lbase = 4,
.len = 8,
.rbase = 0,
}

◆ PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
Initial value:
= {
.lbase = 12,
.len = 16,
.rbase = 16,
}

◆ PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47

const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
Initial value:
= {
.lbase = 28,
.len = 16,
.rbase = 32,
}

◆ tisci_if_PRU_ICSSG0

◆ tisci_irq_PRU_ICSSG0

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0
static
Initial value:
= {
.n_if = 7,
.p_if = &tisci_if_PRU_ICSSG0[0],
}

◆ PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 29,
}

◆ PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 30,
}

◆ PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 31,
}

◆ PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 32,
}

◆ PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
Initial value:
= {
.lbase = 4,
.len = 8,
.rbase = 8,
}

◆ PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
Initial value:
= {
.lbase = 12,
.len = 16,
.rbase = 48,
}

◆ PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79

const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
Initial value:
= {
.lbase = 28,
.len = 16,
.rbase = 64,
}

◆ tisci_if_PRU_ICSSG1

◆ tisci_irq_PRU_ICSSG1

const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1
static
Initial value:
= {
.n_if = 7,
.p_if = &tisci_if_PRU_ICSSG1[0],
}

◆ CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82

const struct Sciclient_rmIrqIf CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 82,
}

◆ CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16

const struct Sciclient_rmIrqIf CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 16,
}

◆ CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17

const struct Sciclient_rmIrqIf CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 17,
}

◆ CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18

const struct Sciclient_rmIrqIf CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 18,
}

◆ CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19

const struct Sciclient_rmIrqIf CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
Initial value:
= {
.lbase = 4,
.len = 1,
.rbase = 19,
}

◆ CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20

const struct Sciclient_rmIrqIf CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
Initial value:
= {
.lbase = 5,
.len = 1,
.rbase = 20,
}

◆ CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24

const struct Sciclient_rmIrqIf CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
Initial value:
= {
.lbase = 6,
.len = 1,
.rbase = 24,
}

◆ CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35

const struct Sciclient_rmIrqIf CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
Initial value:
= {
.lbase = 7,
.len = 1,
.rbase = 35,
}

◆ tisci_if_CPTS0

◆ tisci_irq_CPTS0

const struct Sciclient_rmIrqNode tisci_irq_CPTS0
static
Initial value:
= {
.n_if = 8,
.p_if = &tisci_if_CPTS0[0],
}

◆ EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39

const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 39,
}

◆ tisci_if_EPWM0

const struct Sciclient_rmIrqIf* const tisci_if_EPWM0[]

◆ tisci_irq_EPWM0

const struct Sciclient_rmIrqNode tisci_irq_EPWM0
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_EPWM0[0],
}

◆ EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40

const struct Sciclient_rmIrqIf EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 40,
}

◆ tisci_if_EPWM3

const struct Sciclient_rmIrqIf* const tisci_if_EPWM3[]

◆ tisci_irq_EPWM3

const struct Sciclient_rmIrqNode tisci_irq_EPWM3
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_EPWM3[0],
}

◆ EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41

const struct Sciclient_rmIrqIf EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 41,
}

◆ tisci_if_EPWM6

const struct Sciclient_rmIrqIf* const tisci_if_EPWM6[]

◆ tisci_irq_EPWM6

const struct Sciclient_rmIrqNode tisci_irq_EPWM6
static
Initial value:
= {
.n_if = 1,
.p_if = &tisci_if_EPWM6[0],
}

◆ PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
Initial value:
= {
.lbase = 0,
.len = 1,
.rbase = 81,
}

◆ PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
Initial value:
= {
.lbase = 1,
.len = 1,
.rbase = 23,
}

◆ PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
Initial value:
= {
.lbase = 3,
.len = 1,
.rbase = 33,
}

◆ PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37

const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
Initial value:
= {
.lbase = 2,
.len = 1,
.rbase = 37,
}

◆ PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38

const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
Initial value:
= {
.lbase = 4,
.len = 1,
.rbase = 38,
}

◆ tisci_if_PCIE0

◆ tisci_irq_PCIE0

const struct Sciclient_rmIrqNode tisci_irq_PCIE0
static
Initial value:
= {
.n_if = 5,
.p_if = &tisci_if_PCIE0[0],
}

◆ gRmIrqTree

◆ gRmIrqTreeCount

const uint32_t gRmIrqTreeCount = sizeof(gRmIrqTree)/sizeof(gRmIrqTree[0])
TISCI_DEV_EPWM0
#define TISCI_DEV_EPWM0
Definition: tisci_devices.h:138
DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_72_79_to_R5FSS0_CORE0_intr_8_15
Definition: sciclient_irq_rm.c:589
PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_25_25
Definition: sciclient_irq_rm.c:841
tisci_if_EPWM0
const struct Sciclient_rmIrqIf *const tisci_if_EPWM0[]
Definition: sciclient_irq_rm.c:1028
TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_22_22_to_CPTS0_cpts_hw7_push_6_6
Definition: sciclient_irq_rm.c:445
DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_160_167_to_PRU_ICSSG1_pr1_slv_intr_16_23
Definition: sciclient_irq_rm.c:643
CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
const struct Sciclient_rmIrqIf CPSW0_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_34_34
Definition: sciclient_irq_rm.c:564
TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_20_20_to_CPTS0_cpts_hw5_push_4_4
Definition: sciclient_irq_rm.c:433
MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_16_17_to_DMASS0_INTAGGR_0_intaggr_levi_pend_24_25
Definition: sciclient_irq_rm.c:219
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE0_intr_32_47
Definition: sciclient_irq_rm.c:201
TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_18_18_to_CPTS0_cpts_hw3_push_2_2
Definition: sciclient_irq_rm.c:421
EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
const struct Sciclient_rmIrqIf EPWM3_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_40_40
Definition: sciclient_irq_rm.c:1038
tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_MCU_MCU_GPIOMUX_INTROUTER0
Definition: sciclient_irq_rm.c:348
TISCI_DEV_TIMER1
#define TISCI_DEV_TIMER1
Definition: tisci_devices.h:90
PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
const struct Sciclient_rmIrqIf PCIE0_pcie_ptm_valid_pulse_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_38_38
Definition: sciclient_irq_rm.c:1094
CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
const struct Sciclient_rmIrqIf CPTS0_cpts_genf3_4_4_to_TIMESYNC_EVENT_INTROUTER0_in_19_19
Definition: sciclient_irq_rm.c:981
tisci_if_GPMC0
const struct Sciclient_rmIrqIf *const tisci_if_GPMC0[]
Definition: sciclient_irq_rm.c:831
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE0_intr_104_107
Definition: sciclient_irq_rm.c:301
TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_10_10_to_PRU_ICSSG0_pr1_edc1_latch0_in_2_2
Definition: sciclient_irq_rm.c:373
CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
const struct Sciclient_rmIrqIf CPTS0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_16_16
Definition: sciclient_irq_rm.c:963
tisci_irq_MAIN_GPIOMUX_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_MAIN_GPIOMUX_INTROUTER0
Definition: sciclient_irq_rm.c:276
TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0
#define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0
Definition: tisci_devices.h:64
MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_4_7_to_MCU_M4FSS0_CORE0_nvic_0_3
Definition: sciclient_irq_rm.c:313
GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
const struct Sciclient_rmIrqIf GPIO0_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_190_198
Definition: sciclient_irq_rm.c:762
MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG0_pr1_iep1_cap_intr_req_10_15
Definition: sciclient_irq_rm.c:231
tisci_irq_TIMER0
static const struct Sciclient_rmIrqNode tisci_irq_TIMER0
Definition: sciclient_irq_rm.c:685
TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_31_31_to_CPSW0_cpts_hw2_push_1_1
Definition: sciclient_irq_rm.c:469
TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_0_7_to_DMASS0_INTAGGR_0_intaggr_levi_pend_8_15
Definition: sciclient_irq_rm.c:355
CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_32_39_to_DMASS0_INTAGGR_0_intaggr_levi_pend_0_7
Definition: sciclient_irq_rm.c:162
PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_hw1_push_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_37_37
Definition: sciclient_irq_rm.c:1088
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS1_CORE1_intr_32_47
Definition: sciclient_irq_rm.c:207
tisci_if_TIMER1
const struct Sciclient_rmIrqIf *const tisci_if_TIMER1[]
Definition: sciclient_irq_rm.c:698
TISCI_DEV_EPWM3
#define TISCI_DEV_EPWM3
Definition: tisci_devices.h:141
MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_bank_30_31_to_MCU_MCU_GPIOMUX_INTROUTER0_in_30_31
Definition: sciclient_irq_rm.c:808
PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_81_81
Definition: sciclient_irq_rm.c:1070
CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
const struct Sciclient_rmIrqIf CPTS0_cpts_genf4_5_5_to_TIMESYNC_EVENT_INTROUTER0_in_20_20
Definition: sciclient_irq_rm.c:987
TISCI_DEV_R5FSS0_CORE1
#define TISCI_DEV_R5FSS0_CORE1
Definition: tisci_devices.h:164
MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_24_29_to_PRU_ICSSG1_pr1_iep1_cap_intr_req_10_15
Definition: sciclient_irq_rm.c:249
TISCI_DEV_PCIE0
#define TISCI_DEV_PCIE0
Definition: tisci_devices.h:160
MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event1_92_95
Definition: sciclient_irq_rm.c:325
TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_14_14_to_PRU_ICSSG1_pr1_edc1_latch0_in_2_2
Definition: sciclient_irq_rm.c:397
TISCI_DEV_CPSW0
#define TISCI_DEV_CPSW0
Definition: tisci_devices.h:69
TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_29_29_to_PCIE0_pcie_cpts_hw2_push_0_0
Definition: sciclient_irq_rm.c:457
TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_19_19_to_CPTS0_cpts_hw4_push_3_3
Definition: sciclient_irq_rm.c:427
tisci_if_GPIO0
const struct Sciclient_rmIrqIf *const tisci_if_GPIO0[]
Definition: sciclient_irq_rm.c:768
tisci_if_MCU_GPIO0
const struct Sciclient_rmIrqIf *const tisci_if_MCU_GPIO0[]
Definition: sciclient_irq_rm.c:814
TISCI_DEV_DMASS0_INTAGGR_0
#define TISCI_DEV_DMASS0_INTAGGR_0
Definition: tisci_devices.h:84
tisci_if_GPIO1
const struct Sciclient_rmIrqIf *const tisci_if_GPIO1[]
Definition: sciclient_irq_rm.c:791
tisci_if_PCIE0
const struct Sciclient_rmIrqIf *const tisci_if_PCIE0[]
Definition: sciclient_irq_rm.c:1100
tisci_if_CPTS0
const struct Sciclient_rmIrqIf *const tisci_if_CPTS0[]
Definition: sciclient_irq_rm.c:1005
tisci_irq_CMP_EVENT_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_CMP_EVENT_INTROUTER0
Definition: sciclient_irq_rm.c:176
PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_8_15
Definition: sciclient_irq_rm.c:923
tisci_if_TIMER2
const struct Sciclient_rmIrqIf *const tisci_if_TIMER2[]
Definition: sciclient_irq_rm.c:714
TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_9_9_to_PRU_ICSSG0_pr1_edc0_latch1_in_1_1
Definition: sciclient_irq_rm.c:367
DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_168_183_to_MCU_M4FSS0_CORE0_nvic_32_47
Definition: sciclient_irq_rm.c:649
CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE1_intr_48_55
Definition: sciclient_irq_rm.c:144
CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
const struct Sciclient_rmIrqIf CPTS0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_82_82
Definition: sciclient_irq_rm.c:957
CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
const struct Sciclient_rmIrqIf CPSW0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_22_22
Definition: sciclient_irq_rm.c:558
TISCI_DEV_TIMER2
#define TISCI_DEV_TIMER2
Definition: tisci_devices.h:91
TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
const struct Sciclient_rmIrqIf TIMER3_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_3_3
Definition: sciclient_irq_rm.c:724
DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_120_127_to_R5FSS1_CORE0_intr_8_15
Definition: sciclient_irq_rm.c:613
PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_16_31
Definition: sciclient_irq_rm.c:871
PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_64_79
Definition: sciclient_irq_rm.c:935
tisci_if_PRU_ICSSG1
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG1[]
Definition: sciclient_irq_rm.c:941
DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE0_intr_64_95
Definition: sciclient_irq_rm.c:619
tisci_irq_GPIO1
static const struct Sciclient_rmIrqNode tisci_irq_GPIO1
Definition: sciclient_irq_rm.c:795
TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_17_17_to_CPTS0_cpts_hw2_push_1_1
Definition: sciclient_irq_rm.c:415
DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE0_intr_64_95
Definition: sciclient_irq_rm.c:595
TISCI_DEV_R5FSS0_CORE0
#define TISCI_DEV_R5FSS0_CORE0
Definition: tisci_devices.h:163
tisci_if_TIMER0
const struct Sciclient_rmIrqIf *const tisci_if_TIMER0[]
Definition: sciclient_irq_rm.c:682
EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
const struct Sciclient_rmIrqIf EPWM6_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_41_41
Definition: sciclient_irq_rm.c:1054
MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_46_53_to_PRU_ICSSG1_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:255
tisci_if_MAIN_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_MAIN_GPIOMUX_INTROUTER0[]
Definition: sciclient_irq_rm.c:261
GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
const struct Sciclient_rmIrqIf GPMC0_gpmc_sdmareq_0_0_to_DMASS0_INTAGGR_0_intaggr_levi_pend_29_29
Definition: sciclient_irq_rm.c:825
GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
const struct Sciclient_rmIrqIf GPIO0_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_0_89
Definition: sciclient_irq_rm.c:756
tisci_irq_CPSW0
static const struct Sciclient_rmIrqNode tisci_irq_CPSW0
Definition: sciclient_irq_rm.c:576
TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_32_32_to_CPSW0_cpts_hw3_push_2_2
Definition: sciclient_irq_rm.c:475
TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_21_21_to_CPTS0_cpts_hw6_push_5_5
Definition: sciclient_irq_rm.c:439
TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_16_16_to_CPTS0_cpts_hw1_push_0_0
Definition: sciclient_irq_rm.c:409
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE0_intr_32_47
Definition: sciclient_irq_rm.c:189
TISCI_DEV_PRU_ICSSG1
#define TISCI_DEV_PRU_ICSSG1
Definition: tisci_devices.h:134
CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
const struct Sciclient_rmIrqIf CPSW0_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_21_21
Definition: sciclient_irq_rm.c:552
tisci_if_CMP_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_CMP_EVENT_INTROUTER0[]
Definition: sciclient_irq_rm.c:168
PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_31_31
Definition: sciclient_irq_rm.c:911
TISCI_DEV_TIMER0
#define TISCI_DEV_TIMER0
Definition: tisci_devices.h:89
MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG0_pr1_iep0_cap_intr_req_4_9
Definition: sciclient_irq_rm.c:225
CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
const struct Sciclient_rmIrqIf CPTS0_cpts_genf2_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_18_18
Definition: sciclient_irq_rm.c:975
TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_13_13_to_PRU_ICSSG1_pr1_edc0_latch1_in_1_1
Definition: sciclient_irq_rm.c:391
MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event2_96_99
Definition: sciclient_irq_rm.c:331
TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_23_23_to_CPTS0_cpts_hw8_push_7_7
Definition: sciclient_irq_rm.c:451
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_R5FSS0_CORE1_intr_32_47
Definition: sciclient_irq_rm.c:195
DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_40_71_to_R5FSS0_CORE1_intr_64_95
Definition: sciclient_irq_rm.c:607
CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
const struct Sciclient_rmIrqIf CPTS0_cpts_sync_7_7_to_TIMESYNC_EVENT_INTROUTER0_in_35_35
Definition: sciclient_irq_rm.c:999
PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_32_32
Definition: sciclient_irq_rm.c:917
TISCI_DEV_MAIN_GPIOMUX_INTROUTER0
#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0
Definition: tisci_devices.h:63
TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_35_35_to_CPSW0_cpts_hw6_push_5_5
Definition: sciclient_irq_rm.c:493
tisci_if_EPWM6
const struct Sciclient_rmIrqIf *const tisci_if_EPWM6[]
Definition: sciclient_irq_rm.c:1060
vint_usage_count_DMASS0_INTAGGR_0
uint8_t vint_usage_count_DMASS0_INTAGGR_0[184]
Definition: sciclient_irq_rm.c:50
DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_128_135_to_R5FSS1_CORE1_intr_8_15
Definition: sciclient_irq_rm.c:625
PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_30_30
Definition: sciclient_irq_rm.c:905
CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
const struct Sciclient_rmIrqIf CPTS0_cpts_genf1_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_17_17
Definition: sciclient_irq_rm.c:969
TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_34_34_to_CPSW0_cpts_hw5_push_4_4
Definition: sciclient_irq_rm.c:487
tisci_irq_PRU_ICSSG0
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG0
Definition: sciclient_irq_rm.c:892
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE1_intr_104_107
Definition: sciclient_irq_rm.c:295
TISCI_DEV_R5FSS1_CORE0
#define TISCI_DEV_R5FSS1_CORE0
Definition: tisci_devices.h:165
tisci_if_EPWM3
const struct Sciclient_rmIrqIf *const tisci_if_EPWM3[]
Definition: sciclient_irq_rm.c:1044
tisci_if_TIMESYNC_EVENT_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_TIMESYNC_EVENT_INTROUTER0[]
Definition: sciclient_irq_rm.c:511
PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_iep0_cmp_intr_req_12_27_to_CMP_EVENT_INTROUTER0_in_48_63
Definition: sciclient_irq_rm.c:929
TISCI_DEV_EPWM6
#define TISCI_DEV_EPWM6
Definition: tisci_devices.h:144
tisci_irq_EPWM3
static const struct Sciclient_rmIrqNode tisci_irq_EPWM3
Definition: sciclient_irq_rm.c:1047
TISCI_DEV_CPTS0
#define TISCI_DEV_CPTS0
Definition: tisci_devices.h:136
tisci_if_DMASS0_INTAGGR_0
const struct Sciclient_rmIrqIf *const tisci_if_DMASS0_INTAGGR_0[]
Definition: sciclient_irq_rm.c:655
TISCI_DEV_TIMER3
#define TISCI_DEV_TIMER3
Definition: tisci_devices.h:92
PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_sync_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_33_33
Definition: sciclient_irq_rm.c:1082
PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync1_out_3_3_to_TIMESYNC_EVENT_INTROUTER0_in_28_28
Definition: sciclient_irq_rm.c:859
TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_37_37_to_CPSW0_cpts_hw8_push_7_7
Definition: sciclient_irq_rm.c:505
tisci_irq_PRU_ICSSG1
static const struct Sciclient_rmIrqNode tisci_irq_PRU_ICSSG1
Definition: sciclient_irq_rm.c:950
GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
const struct Sciclient_rmIrqIf GPIO1_gpio_bank_90_98_to_MAIN_GPIOMUX_INTROUTER0_in_180_188
Definition: sciclient_irq_rm.c:785
tisci_if_MCU_MCU_GPIOMUX_INTROUTER0
const struct Sciclient_rmIrqIf *const tisci_if_MCU_MCU_GPIOMUX_INTROUTER0[]
Definition: sciclient_irq_rm.c:337
MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
const struct Sciclient_rmIrqIf MCU_GPIO0_gpio_0_29_to_MCU_MCU_GPIOMUX_INTROUTER0_in_0_29
Definition: sciclient_irq_rm.c:802
tisci_irq_CPTS0
static const struct Sciclient_rmIrqNode tisci_irq_CPTS0
Definition: sciclient_irq_rm.c:1015
EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
const struct Sciclient_rmIrqIf EPWM0_epwm_synco_o_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_39_39
Definition: sciclient_irq_rm.c:1022
MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_38_45_to_PRU_ICSSG0_pr1_slv_intr_46_53
Definition: sciclient_irq_rm.c:237
tisci_irq_EPWM0
static const struct Sciclient_rmIrqNode tisci_irq_EPWM0
Definition: sciclient_irq_rm.c:1031
DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_0_39_to_GICSS0_spi_64_103
Definition: sciclient_irq_rm.c:583
tisci_if_GTC0
const struct Sciclient_rmIrqIf *const tisci_if_GTC0[]
Definition: sciclient_irq_rm.c:746
TISCI_DEV_PRU_ICSSG0
#define TISCI_DEV_PRU_ICSSG0
Definition: tisci_devices.h:133
CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE0_intr_48_55
Definition: sciclient_irq_rm.c:150
TISCI_DEV_CMP_EVENT_INTROUTER0
#define TISCI_DEV_CMP_EVENT_INTROUTER0
Definition: tisci_devices.h:61
TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_33_33_to_CPSW0_cpts_hw4_push_3_3
Definition: sciclient_irq_rm.c:481
TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
const struct Sciclient_rmIrqIf TIMER1_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_1_1
Definition: sciclient_irq_rm.c:692
MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_30_37_to_DMASS0_INTAGGR_0_intaggr_levi_pend_16_23
Definition: sciclient_irq_rm.c:213
tisci_irq_TIMER3
static const struct Sciclient_rmIrqNode tisci_irq_TIMER3
Definition: sciclient_irq_rm.c:733
DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_80_87_to_R5FSS0_CORE1_intr_8_15
Definition: sciclient_irq_rm.c:601
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS1_CORE1_intr_104_107
Definition: sciclient_irq_rm.c:307
tisci_irq_EPWM6
static const struct Sciclient_rmIrqNode tisci_irq_EPWM6
Definition: sciclient_irq_rm.c:1063
PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
const struct Sciclient_rmIrqIf PRU_ICSSG1_pr1_edc0_sync0_out_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_29_29
Definition: sciclient_irq_rm.c:899
tisci_irq_TIMESYNC_EVENT_INTROUTER0
static const struct Sciclient_rmIrqNode tisci_irq_TIMESYNC_EVENT_INTROUTER0
Definition: sciclient_irq_rm.c:539
tisci_if_CPSW0
const struct Sciclient_rmIrqIf *const tisci_if_CPSW0[]
Definition: sciclient_irq_rm.c:570
MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_8_11_to_MCU_ESM0_esm_pls_event0_88_91
Definition: sciclient_irq_rm.c:319
tisci_irq_MCU_GPIO0
static const struct Sciclient_rmIrqNode tisci_irq_MCU_GPIO0
Definition: sciclient_irq_rm.c:818
tisci_irq_GPIO0
static const struct Sciclient_rmIrqNode tisci_irq_GPIO0
Definition: sciclient_irq_rm.c:772
TISCI_DEV_MCU_ESM0
#define TISCI_DEV_MCU_ESM0
Definition: tisci_devices.h:116
TISCI_DEV_TIMESYNC_EVENT_INTROUTER0
#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0
Definition: tisci_devices.h:65
tisci_irq_GPMC0
static const struct Sciclient_rmIrqNode tisci_irq_GPMC0
Definition: sciclient_irq_rm.c:834
TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_30_30_to_CPSW0_cpts_hw1_push_0_0
Definition: sciclient_irq_rm.c:463
PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
const struct Sciclient_rmIrqIf PCIE0_pcie_cpts_genf0_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_23_23
Definition: sciclient_irq_rm.c:1076
TISCI_DEV_MCU_GPIO0
#define TISCI_DEV_MCU_GPIO0
Definition: tisci_devices.h:131
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_GICSS0_spi_104_107
Definition: sciclient_irq_rm.c:283
PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc1_sync0_out_2_2_to_TIMESYNC_EVENT_INTROUTER0_in_27_27
Definition: sciclient_irq_rm.c:853
PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_iep1_cmp_intr_req_28_43_to_CMP_EVENT_INTROUTER0_in_32_47
Definition: sciclient_irq_rm.c:877
MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_0_15_to_GICSS0_spi_32_47
Definition: sciclient_irq_rm.c:183
TISCI_DEV_GICSS0
#define TISCI_DEV_GICSS0
Definition: tisci_devices.h:128
GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
const struct Sciclient_rmIrqIf GPIO1_gpio_0_89_to_MAIN_GPIOMUX_INTROUTER0_in_90_179
Definition: sciclient_irq_rm.c:779
TISCI_DEV_GPIO0
#define TISCI_DEV_GPIO0
Definition: tisci_devices.h:129
tisci_irq_DMASS0_INTAGGR_0
static const struct Sciclient_rmIrqNode tisci_irq_DMASS0_INTAGGR_0
Definition: sciclient_irq_rm.c:669
TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_36_36_to_CPSW0_cpts_hw7_push_6_6
Definition: sciclient_irq_rm.c:499
TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
const struct Sciclient_rmIrqIf TIMER0_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_0_0
Definition: sciclient_irq_rm.c:676
TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_11_11_to_PRU_ICSSG0_pr1_edc1_latch1_in_3_3
Definition: sciclient_irq_rm.c:379
tisci_if_PRU_ICSSG0
const struct Sciclient_rmIrqIf *const tisci_if_PRU_ICSSG0[]
Definition: sciclient_irq_rm.c:883
tisci_irq_TIMER2
static const struct Sciclient_rmIrqNode tisci_irq_TIMER2
Definition: sciclient_irq_rm.c:717
TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_8_8_to_PRU_ICSSG0_pr1_edc0_latch0_in_0_0
Definition: sciclient_irq_rm.c:361
TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
const struct Sciclient_rmIrqIf TIMER2_timer_pwm_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_2_2
Definition: sciclient_irq_rm.c:708
DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_88_119_to_R5FSS1_CORE1_intr_64_95
Definition: sciclient_irq_rm.c:631
PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_host_intr_req_4_11_to_CMP_EVENT_INTROUTER0_in_0_7
Definition: sciclient_irq_rm.c:865
CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_0_15_to_GICSS0_spi_48_63
Definition: sciclient_irq_rm.c:132
tisci_irq_TIMER1
static const struct Sciclient_rmIrqNode tisci_irq_TIMER1
Definition: sciclient_irq_rm.c:701
CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_16_23_to_R5FSS0_CORE0_intr_48_55
Definition: sciclient_irq_rm.c:138
TISCI_DEV_GTC0
#define TISCI_DEV_GTC0
Definition: tisci_devices.h:113
rom_usage_DMASS0_INTAGGR_0
static struct Sciclient_rmIaUsedMapping rom_usage_DMASS0_INTAGGR_0[5U]
Definition: sciclient_irq_rm.c:51
TISCI_DEV_R5FSS1_CORE1
#define TISCI_DEV_R5FSS1_CORE1
Definition: tisci_devices.h:166
MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
const struct Sciclient_rmIrqIf MAIN_GPIOMUX_INTROUTER0_outp_18_23_to_PRU_ICSSG1_pr1_iep0_cap_intr_req_4_9
Definition: sciclient_irq_rm.c:243
GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
const struct Sciclient_rmIrqIf GTC0_gtc_push_event_0_0_to_TIMESYNC_EVENT_INTROUTER0_in_36_36
Definition: sciclient_irq_rm.c:740
TISCI_DEV_GPMC0
#define TISCI_DEV_GPMC0
Definition: tisci_devices.h:132
TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_12_12_to_PRU_ICSSG1_pr1_edc0_latch0_in_0_0
Definition: sciclient_irq_rm.c:385
PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
const struct Sciclient_rmIrqIf PRU_ICSSG0_pr1_edc0_sync1_out_1_1_to_TIMESYNC_EVENT_INTROUTER0_in_26_26
Definition: sciclient_irq_rm.c:847
CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
const struct Sciclient_rmIrqIf CMP_EVENT_INTROUTER0_outp_24_31_to_R5FSS1_CORE1_intr_48_55
Definition: sciclient_irq_rm.c:156
CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
const struct Sciclient_rmIrqIf CPSW0_cpts_comp_0_0_to_CMP_EVENT_INTROUTER0_in_80_80
Definition: sciclient_irq_rm.c:546
MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
const struct Sciclient_rmIrqIf MCU_MCU_GPIOMUX_INTROUTER0_outp_0_3_to_R5FSS0_CORE0_intr_104_107
Definition: sciclient_irq_rm.c:289
TISCI_DEV_MCU_M4FSS0_CORE0
#define TISCI_DEV_MCU_M4FSS0_CORE0
Definition: tisci_devices.h:68
tisci_irq_GTC0
static const struct Sciclient_rmIrqNode tisci_irq_GTC0
Definition: sciclient_irq_rm.c:749
CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
const struct Sciclient_rmIrqIf CPTS0_cpts_genf5_6_6_to_TIMESYNC_EVENT_INTROUTER0_in_24_24
Definition: sciclient_irq_rm.c:993
tisci_if_TIMER3
const struct Sciclient_rmIrqIf *const tisci_if_TIMER3[]
Definition: sciclient_irq_rm.c:730
tisci_irq_PCIE0
static const struct Sciclient_rmIrqNode tisci_irq_PCIE0
Definition: sciclient_irq_rm.c:1107
TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
const struct Sciclient_rmIrqIf TIMESYNC_EVENT_INTROUTER0_outl_15_15_to_PRU_ICSSG1_pr1_edc1_latch1_in_3_3
Definition: sciclient_irq_rm.c:403
DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
const struct Sciclient_rmIrqIf DMASS0_INTAGGR_0_intaggr_vintr_pend_152_159_to_PRU_ICSSG0_pr1_slv_intr_16_23
Definition: sciclient_irq_rm.c:637
TISCI_DEV_GPIO1
#define TISCI_DEV_GPIO1
Definition: tisci_devices.h:130