AM64x MCU+ SDK  10.00.00
sciclient_fmwMsgParams.h File Reference

Introduction

This file contains the definition of all the parameter IDs for PM, RM, Security.

Go to the source code of this file.

Macros

#define TISCI_PARAM_UNDEF   (0xFFFFFFFFU)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE   (0xFFFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX   (0xFFFFFFFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR   (0xFFFFFFFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT   (0xFFFFFFFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_MODE   (0xFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE   (0xFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID   (0xFFu)
 
#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE   (0xFFu)
 
#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX   (0xFFFFFFFFu)
 
Sciclient Firmware ABI revisions

ABI revisions for compatibility check.

#define SCICLIENT_FIRMWARE_ABI_MAJOR   (4U)
 
#define SCICLIENT_FIRMWARE_ABI_MINOR   (0U)
 
Sciclient Context Ids

Context IDs for Sciclient_ConfigPrms_t .

#define SCICLIENT_CONTEXT_R5_0_SEC_0   (0U)
 
#define SCICLIENT_CONTEXT_R5_0_NONSEC_0   (1U)
 
#define SCICLIENT_CONTEXT_R5_0_SEC_1   (2U)
 
#define SCICLIENT_CONTEXT_R5_0_NONSEC_1   (3U)
 
#define SCICLIENT_CONTEXT_A53_SEC_0   (4U)
 
#define SCICLIENT_CONTEXT_A53_NONSEC_0   (5U)
 
#define SCICLIENT_CONTEXT_A53_NONSEC_1   (6U)
 
#define SCICLIENT_CONTEXT_A53_NONSEC_2   (7U)
 
#define SCICLIENT_CONTEXT_M4_NONSEC_0   (8U)
 
#define SCICLIENT_CONTEXT_R5_1_SEC_0   (9U)
 
#define SCICLIENT_CONTEXT_R5_1_NONSEC_0   (10U)
 
#define SCICLIENT_CONTEXT_R5_1_SEC_1   (11U)
 
#define SCICLIENT_CONTEXT_R5_1_NONSEC_1   (12U)
 
#define SCICLIENT_CONTEXT_ICSSG_NONSEC_0   (13U)
 
#define SCICLIENT_CONTEXT_M4_SEC_0   (14U) /* TBD */
 
#define SCICLIENT_CONTEXT_MAX_NUM   (15U)
 
Sciclient Processor Ids

Processor IDs for the Processor Boot Configuration APIs.

#define SCICLIENT_PROCID_A53_CL0_C0   (0x20U)
 
#define SCICLIENT_PROCID_A53_CL0_C1   (0x21U)
 
#define SCICLIENT_PROCID_R5_CL0_C0   (0x01U)
 
#define SCICLIENT_PROCID_R5_CL0_C1   (0x02U)
 
#define SCICLIENT_PROCID_R5_CL1_C0   (0x06U)
 
#define SCICLIENT_PROCID_R5_CL1_C1   (0x07U)
 
#define SCICLIENT_PROCID_MCU_M4FSS0_C0   (0x18U)
 
IRQ source index start

Start offset of IRQ source index.

#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START   (20U)
 
#define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START   (32U)
 
#define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START   (0U)
 
#define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START   (4096U)
 
#define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START   (4608U)
 
#define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START   (5120U)
 
#define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START   (5632U)
 
#define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START   (6144U)
 
#define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START   (6656U)
 
#define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START   (8192U)
 
#define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START   (8704U)
 
#define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START   (9216U)
 
#define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START   (9728U)
 
#define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START   (10240U)
 
#define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START   (10752U)
 
#define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START   (11264U)
 
#define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START   (11776U)
 
#define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START   (12288U)
 

Macro Definition Documentation

◆ TISCI_PARAM_UNDEF

#define TISCI_PARAM_UNDEF   (0xFFFFFFFFU)

Undefined Param Undefined

◆ SCICLIENT_FIRMWARE_ABI_MAJOR

#define SCICLIENT_FIRMWARE_ABI_MAJOR   (4U)

◆ SCICLIENT_FIRMWARE_ABI_MINOR

#define SCICLIENT_FIRMWARE_ABI_MINOR   (0U)

◆ SCICLIENT_CONTEXT_R5_0_SEC_0

#define SCICLIENT_CONTEXT_R5_0_SEC_0   (0U)

r5(Secure): Cortex R5 Context 0

◆ SCICLIENT_CONTEXT_R5_0_NONSEC_0

#define SCICLIENT_CONTEXT_R5_0_NONSEC_0   (1U)

r5(Non Secure): Cortex R5 Context 1

◆ SCICLIENT_CONTEXT_R5_0_SEC_1

#define SCICLIENT_CONTEXT_R5_0_SEC_1   (2U)

r5(Secure): Cortex R5 Context 2

◆ SCICLIENT_CONTEXT_R5_0_NONSEC_1

#define SCICLIENT_CONTEXT_R5_0_NONSEC_1   (3U)

r5(Non Secure): Cortex R5 Context 3

◆ SCICLIENT_CONTEXT_A53_SEC_0

#define SCICLIENT_CONTEXT_A53_SEC_0   (4U)

a53(Secure): Cortex A53 context 0

◆ SCICLIENT_CONTEXT_A53_NONSEC_0

#define SCICLIENT_CONTEXT_A53_NONSEC_0   (5U)

a53(Non Secure): Cortex A53 context 1

◆ SCICLIENT_CONTEXT_A53_NONSEC_1

#define SCICLIENT_CONTEXT_A53_NONSEC_1   (6U)

a53(Non Secure): Cortex A53 context 2

◆ SCICLIENT_CONTEXT_A53_NONSEC_2

#define SCICLIENT_CONTEXT_A53_NONSEC_2   (7U)

a53(Non Secure): Cortex A53 context 3

◆ SCICLIENT_CONTEXT_M4_NONSEC_0

#define SCICLIENT_CONTEXT_M4_NONSEC_0   (8U)

M4 (Non Secure): Cortex M4 context 1

◆ SCICLIENT_CONTEXT_R5_1_SEC_0

#define SCICLIENT_CONTEXT_R5_1_SEC_0   (9U)

r5(Secure): Cortex R5 Context 0

◆ SCICLIENT_CONTEXT_R5_1_NONSEC_0

#define SCICLIENT_CONTEXT_R5_1_NONSEC_0   (10U)

r5(Non Secure): Cortex R5 Context 1

◆ SCICLIENT_CONTEXT_R5_1_SEC_1

#define SCICLIENT_CONTEXT_R5_1_SEC_1   (11U)

r5(Secure): Cortex R5 Context 2

◆ SCICLIENT_CONTEXT_R5_1_NONSEC_1

#define SCICLIENT_CONTEXT_R5_1_NONSEC_1   (12U)

r5(Non Secure): Cortex R5 Context 3

◆ SCICLIENT_CONTEXT_ICSSG_NONSEC_0

#define SCICLIENT_CONTEXT_ICSSG_NONSEC_0   (13U)

ICSSG (Non Secure) : ICSSG Non Secure Context

◆ SCICLIENT_CONTEXT_M4_SEC_0

#define SCICLIENT_CONTEXT_M4_SEC_0   (14U) /* TBD */

M4 (Secure): Cortex M4 context 1

◆ SCICLIENT_CONTEXT_MAX_NUM

#define SCICLIENT_CONTEXT_MAX_NUM   (15U)

Total number of possible contexts for application.

◆ SCICLIENT_PROCID_A53_CL0_C0

#define SCICLIENT_PROCID_A53_CL0_C0   (0x20U)

AM64_MAIN_SEC_MMR_MAIN_0: (Cluster 9 Processor 0)

◆ SCICLIENT_PROCID_A53_CL0_C1

#define SCICLIENT_PROCID_A53_CL0_C1   (0x21U)

AM64_MAIN_SEC_MMR_MAIN_0: (Cluster 9 Processor 1)

◆ SCICLIENT_PROCID_R5_CL0_C0

#define SCICLIENT_PROCID_R5_CL0_C0   (0x01U)

AM64_MAIN_SEC_MMR_MAIN_0: (Cluster 0 Processor 0)

◆ SCICLIENT_PROCID_R5_CL0_C1

#define SCICLIENT_PROCID_R5_CL0_C1   (0x02U)

AM64_MAIN_SEC_MMR_MAIN_0: (Cluster 0 Processor 1)

◆ SCICLIENT_PROCID_R5_CL1_C0

#define SCICLIENT_PROCID_R5_CL1_C0   (0x06U)

AM64_MAIN_SEC_MMR_MAIN_0: (Cluster 1 Processor 0)

◆ SCICLIENT_PROCID_R5_CL1_C1

#define SCICLIENT_PROCID_R5_CL1_C1   (0x07U)

AM64_MAIN_SEC_MMR_MAIN_0: (Cluster 1 Processor 1)

◆ SCICLIENT_PROCID_MCU_M4FSS0_C0

#define SCICLIENT_PROCID_MCU_M4FSS0_C0   (0x18U)

◆ TISCI_MSG_VALUE_RM_NULL_RING_TYPE

#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE   (0xFFFFu)

-----------------— Resource Management Parameters ------------------—

◆ TISCI_MSG_VALUE_RM_NULL_RING_INDEX

#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX   (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_ADDR

#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR   (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_COUNT

#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT   (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_MODE

#define TISCI_MSG_VALUE_RM_NULL_RING_MODE   (0xFFu)

The ring mode field of the RING_SIZE register is not modified if this value is used for: tisci_msg_rm_ring_cfg_req::mode

◆ TISCI_MSG_VALUE_RM_NULL_RING_SIZE

#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE   (0xFFu)

◆ TISCI_MSG_VALUE_RM_NULL_ORDER_ID

#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID   (0xFFu)

◆ TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE   (0xFFu)

◆ TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX   (0xFFFFFFFFu)

◆ TISCI_RINGACC0_OES_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START   (20U)

◆ TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START   (32U)

◆ TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START

#define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START   (0U)

◆ TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START   (4096U)

◆ TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START   (4608U)

◆ TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START   (5120U)

◆ TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START   (5632U)

◆ TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START   (6144U)

◆ TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START   (6656U)

◆ TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START   (8192U)

◆ TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START   (8704U)

◆ TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START   (9216U)

◆ TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START   (9728U)

◆ TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START   (10240U)

◆ TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START   (10752U)

◆ TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START   (11264U)

◆ TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START   (11776U)

◆ TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START   (12288U)