AM64x MCU+ SDK  10.00.00

Introduction

DMSC controls the power management, security and resource management of the device.

Macros

#define TISCI_HOST_ID_DMSC   (0U)
 This file contains: More...
 
#define TISCI_HOST_ID_MAIN_0_R5_0   (35U)
 
#define TISCI_HOST_ID_MAIN_0_R5_1   (36U)
 
#define TISCI_HOST_ID_MAIN_0_R5_2   (37U)
 
#define TISCI_HOST_ID_MAIN_0_R5_3   (38U)
 
#define TISCI_HOST_ID_A53_0   (10U)
 
#define TISCI_HOST_ID_A53_1   (11U)
 
#define TISCI_HOST_ID_A53_2   (12U)
 
#define TISCI_HOST_ID_A53_3   (13U)
 
#define TISCI_HOST_ID_M4_0   (30U)
 
#define TISCI_HOST_ID_MAIN_1_R5_0   (40U)
 
#define TISCI_HOST_ID_MAIN_1_R5_1   (41U)
 
#define TISCI_HOST_ID_MAIN_1_R5_2   (42U)
 
#define TISCI_HOST_ID_MAIN_1_R5_3   (43U)
 
#define TISCI_HOST_ID_A53_4   (14U)
 
#define TISCI_HOST_ID_ICSSG_0   (50U)
 
#define TISCI_HOST_ID_ICSSG_1   (51U)
 
#define TISCI_HOST_ID_ALL   (128U)
 
#define TISCI_HOST_ID_CNT   (17U)
 

Macro Definition Documentation

◆ TISCI_HOST_ID_DMSC

#define TISCI_HOST_ID_DMSC   (0U)

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

System Firmware Source File

Host IDs for AM64X device

Data version: 230209_212853 DMSC(Secure): Device Management and Security Control

◆ TISCI_HOST_ID_MAIN_0_R5_0

#define TISCI_HOST_ID_MAIN_0_R5_0   (35U)

MAIN_0_R5_0(Secure): Cortex R5_0 context 0 on Main island(BOOT)

◆ TISCI_HOST_ID_MAIN_0_R5_1

#define TISCI_HOST_ID_MAIN_0_R5_1   (36U)

MAIN_0_R5_1(Non Secure): Cortex R5_0 context 1 on Main island

◆ TISCI_HOST_ID_MAIN_0_R5_2

#define TISCI_HOST_ID_MAIN_0_R5_2   (37U)

MAIN_0_R5_2(Secure): Cortex R5_0 context 2 on Main island

◆ TISCI_HOST_ID_MAIN_0_R5_3

#define TISCI_HOST_ID_MAIN_0_R5_3   (38U)

MAIN_0_R5_3(Non Secure): Cortex R5_0 context 3 on Main island

◆ TISCI_HOST_ID_A53_0

#define TISCI_HOST_ID_A53_0   (10U)

A53_0(Secure): Cortex a53 context 0 on Main island

◆ TISCI_HOST_ID_A53_1

#define TISCI_HOST_ID_A53_1   (11U)

A53_1(Secure): Cortex A53 context 1 on Main island

◆ TISCI_HOST_ID_A53_2

#define TISCI_HOST_ID_A53_2   (12U)

A53_2(Non Secure): Cortex A53 context 2 on Main island

◆ TISCI_HOST_ID_A53_3

#define TISCI_HOST_ID_A53_3   (13U)

A53_3(Non Secure): Cortex A53 context 3 on Main island

◆ TISCI_HOST_ID_M4_0

#define TISCI_HOST_ID_M4_0   (30U)

M4_0(Non Secure): M4

◆ TISCI_HOST_ID_MAIN_1_R5_0

#define TISCI_HOST_ID_MAIN_1_R5_0   (40U)

MAIN_1_R5_0(Secure): Cortex R5_1 context 0 on Main island

◆ TISCI_HOST_ID_MAIN_1_R5_1

#define TISCI_HOST_ID_MAIN_1_R5_1   (41U)

MAIN_1_R5_1(Non Secure): Cortex R5_1 context 1 on Main island

◆ TISCI_HOST_ID_MAIN_1_R5_2

#define TISCI_HOST_ID_MAIN_1_R5_2   (42U)

MAIN_1_R5_2(Secure): Cortex R5_1 context 2 on Main island

◆ TISCI_HOST_ID_MAIN_1_R5_3

#define TISCI_HOST_ID_MAIN_1_R5_3   (43U)

MAIN_1_R5_3(Non Secure): Cortex R5_1 context 3 on Main island

◆ TISCI_HOST_ID_A53_4

#define TISCI_HOST_ID_A53_4   (14U)

A53_4(Non Secure): Cortex A53 context 1 on Main island

◆ TISCI_HOST_ID_ICSSG_0

#define TISCI_HOST_ID_ICSSG_0   (50U)

ICSSG_0(Non Secure): ICSSG context 0 on Main island

◆ TISCI_HOST_ID_ICSSG_1

#define TISCI_HOST_ID_ICSSG_1   (51U)

ICSSG_1(Non Secure): ICSSG context 1 on Main island

◆ TISCI_HOST_ID_ALL

#define TISCI_HOST_ID_ALL   (128U)

Host catch all. Used in board configuration resource assignments to define resource ranges useable by all hosts. Cannot be used

◆ TISCI_HOST_ID_CNT

#define TISCI_HOST_ID_CNT   (17U)

Number of unique hosts on the SoC