AM64x MCU+ SDK  10.00.00

Introduction

DMSC controls the power management, security and resource management of the device.

Macros

#define TISCI_DEV_ADC0_ADC_CLK   0
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#define TISCI_DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK   2
 
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK   3
 
#define TISCI_DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   4
 
#define TISCI_DEV_ADC0_SYS_CLK   5
 
#define TISCI_DEV_ADC0_VBUS_CLK   6
 
#define TISCI_DEV_CMP_EVENT_INTROUTER0_INTR_CLK   0
 
#define TISCI_DEV_DBGSUSPENDROUTER0_INTR_CLK   0
 
#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK   0
 
#define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK   0
 
#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK   0
 
#define TISCI_DEV_MCU_M4FSS0_CBASS_0_CLK   0
 
#define TISCI_DEV_MCU_M4FSS0_CORE0_DAP_CLK   0
 
#define TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK   1
 
#define TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK   2
 
#define TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2   3
 
#define TISCI_DEV_CPSW0_CPPI_CLK_CLK   0
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK   1
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   2
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   3
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   4
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   5
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   8
 
#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   9
 
#define TISCI_DEV_CPSW0_GMII1_MR_CLK   10
 
#define TISCI_DEV_CPSW0_GMII1_MT_CLK   11
 
#define TISCI_DEV_CPSW0_GMII2_MR_CLK   12
 
#define TISCI_DEV_CPSW0_GMII2_MT_CLK   13
 
#define TISCI_DEV_CPSW0_GMII_RFT_CLK   14
 
#define TISCI_DEV_CPSW0_RGMII1_RXC_I   15
 
#define TISCI_DEV_CPSW0_RGMII1_TXC_I   16
 
#define TISCI_DEV_CPSW0_RGMII2_RXC_I   17
 
#define TISCI_DEV_CPSW0_RGMII2_TXC_I   18
 
#define TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK   19
 
#define TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK   20
 
#define TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK   21
 
#define TISCI_DEV_CPSW0_RMII_MHZ_50_CLK   22
 
#define TISCI_DEV_CPSW0_CPTS_GENF0   23
 
#define TISCI_DEV_CPSW0_CPTS_GENF1   24
 
#define TISCI_DEV_CPSW0_RGMII1_TXC_O   25
 
#define TISCI_DEV_CPSW0_RGMII2_TXC_O   26
 
#define TISCI_DEV_CPT2_AGGR0_VCLK_CLK   0
 
#define TISCI_DEV_STM0_ATB_CLK   0
 
#define TISCI_DEV_STM0_CORE_CLK   1
 
#define TISCI_DEV_STM0_VBUSP_CLK   2
 
#define TISCI_DEV_DCC0_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_DCC0_DCC_CLKSRC1_CLK   1
 
#define TISCI_DEV_DCC0_DCC_CLKSRC2_CLK   2
 
#define TISCI_DEV_DCC0_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC0_DCC_CLKSRC4_CLK   4
 
#define TISCI_DEV_DCC0_DCC_CLKSRC5_CLK   5
 
#define TISCI_DEV_DCC0_DCC_CLKSRC6_CLK   6
 
#define TISCI_DEV_DCC0_DCC_CLKSRC7_CLK   7
 
#define TISCI_DEV_DCC0_DCC_INPUT00_CLK   8
 
#define TISCI_DEV_DCC0_DCC_INPUT01_CLK   9
 
#define TISCI_DEV_DCC0_DCC_INPUT02_CLK   10
 
#define TISCI_DEV_DCC0_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC0_VBUS_CLK   12
 
#define TISCI_DEV_DCC1_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_DCC1_DCC_CLKSRC1_CLK   1
 
#define TISCI_DEV_DCC1_DCC_CLKSRC2_CLK   2
 
#define TISCI_DEV_DCC1_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC1_DCC_CLKSRC4_CLK   4
 
#define TISCI_DEV_DCC1_DCC_CLKSRC5_CLK   5
 
#define TISCI_DEV_DCC1_DCC_CLKSRC6_CLK   6
 
#define TISCI_DEV_DCC1_DCC_CLKSRC7_CLK   7
 
#define TISCI_DEV_DCC1_DCC_INPUT00_CLK   8
 
#define TISCI_DEV_DCC1_DCC_INPUT01_CLK   9
 
#define TISCI_DEV_DCC1_DCC_INPUT02_CLK   10
 
#define TISCI_DEV_DCC1_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC1_VBUS_CLK   12
 
#define TISCI_DEV_DCC2_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_DCC2_DCC_CLKSRC1_CLK   1
 
#define TISCI_DEV_DCC2_DCC_CLKSRC2_CLK   2
 
#define TISCI_DEV_DCC2_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC2_DCC_CLKSRC4_CLK   4
 
#define TISCI_DEV_DCC2_DCC_CLKSRC5_CLK   5
 
#define TISCI_DEV_DCC2_DCC_CLKSRC6_CLK   6
 
#define TISCI_DEV_DCC2_DCC_CLKSRC7_CLK   7
 
#define TISCI_DEV_DCC2_DCC_INPUT00_CLK   8
 
#define TISCI_DEV_DCC2_DCC_INPUT01_CLK   9
 
#define TISCI_DEV_DCC2_DCC_INPUT02_CLK   10
 
#define TISCI_DEV_DCC2_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC2_VBUS_CLK   12
 
#define TISCI_DEV_DCC3_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_DCC3_DCC_CLKSRC1_CLK   1
 
#define TISCI_DEV_DCC3_DCC_CLKSRC2_CLK   2
 
#define TISCI_DEV_DCC3_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC3_DCC_CLKSRC4_CLK   4
 
#define TISCI_DEV_DCC3_DCC_CLKSRC5_CLK   5
 
#define TISCI_DEV_DCC3_DCC_CLKSRC6_CLK   6
 
#define TISCI_DEV_DCC3_DCC_CLKSRC7_CLK   7
 
#define TISCI_DEV_DCC3_DCC_INPUT00_CLK   8
 
#define TISCI_DEV_DCC3_DCC_INPUT01_CLK   9
 
#define TISCI_DEV_DCC3_DCC_INPUT02_CLK   10
 
#define TISCI_DEV_DCC3_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC3_VBUS_CLK   12
 
#define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK   1
 
#define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK   2
 
#define TISCI_DEV_DCC4_DCC_CLKSRC1_CLK   3
 
#define TISCI_DEV_DCC4_DCC_CLKSRC2_CLK   4
 
#define TISCI_DEV_DCC4_DCC_CLKSRC3_CLK   5
 
#define TISCI_DEV_DCC4_DCC_CLKSRC4_CLK   6
 
#define TISCI_DEV_DCC4_DCC_CLKSRC5_CLK   7
 
#define TISCI_DEV_DCC4_DCC_CLKSRC6_CLK   8
 
#define TISCI_DEV_DCC4_DCC_CLKSRC7_CLK   9
 
#define TISCI_DEV_DCC4_DCC_INPUT00_CLK   10
 
#define TISCI_DEV_DCC4_DCC_INPUT01_CLK   11
 
#define TISCI_DEV_DCC4_DCC_INPUT02_CLK   12
 
#define TISCI_DEV_DCC4_DCC_INPUT10_CLK   13
 
#define TISCI_DEV_DCC4_VBUS_CLK   14
 
#define TISCI_DEV_DCC5_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_DCC5_DCC_CLKSRC1_CLK   1
 
#define TISCI_DEV_DCC5_DCC_CLKSRC2_CLK   2
 
#define TISCI_DEV_DCC5_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_DCC5_DCC_CLKSRC4_CLK   4
 
#define TISCI_DEV_DCC5_DCC_CLKSRC5_CLK   5
 
#define TISCI_DEV_DCC5_DCC_CLKSRC6_CLK   6
 
#define TISCI_DEV_DCC5_DCC_CLKSRC7_CLK   7
 
#define TISCI_DEV_DCC5_DCC_INPUT00_CLK   8
 
#define TISCI_DEV_DCC5_DCC_INPUT01_CLK   9
 
#define TISCI_DEV_DCC5_DCC_INPUT02_CLK   10
 
#define TISCI_DEV_DCC5_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_DCC5_VBUS_CLK   12
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK   0
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK   1
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK   2
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK   3
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK   4
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK   5
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK   6
 
#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK   7
 
#define TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK   8
 
#define TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK   9
 
#define TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK   10
 
#define TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK   11
 
#define TISCI_DEV_MCU_DCC0_VBUS_CLK   12
 
#define TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK   0
 
#define TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK   1
 
#define TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK   2
 
#define TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK   3
 
#define TISCI_DEV_DMASS0_BCDMA_0_CLK   0
 
#define TISCI_DEV_DMASS0_CBASS_0_CLK   0
 
#define TISCI_DEV_DMASS0_INTAGGR_0_CLK   0
 
#define TISCI_DEV_DMASS0_IPCSS_0_CLK   0
 
#define TISCI_DEV_DMASS0_PKTDMA_0_CLK   0
 
#define TISCI_DEV_DMASS0_RINGACC_0_CLK   0
 
#define TISCI_DEV_TIMER0_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER0_TIMER_PWM   18
 
#define TISCI_DEV_TIMER1_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER1_TIMER_PWM   18
 
#define TISCI_DEV_TIMER10_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER10_TIMER_PWM   18
 
#define TISCI_DEV_TIMER11_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER11_TIMER_PWM   18
 
#define TISCI_DEV_TIMER2_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER2_TIMER_PWM   18
 
#define TISCI_DEV_TIMER3_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER3_TIMER_PWM   18
 
#define TISCI_DEV_TIMER4_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER4_TIMER_PWM   18
 
#define TISCI_DEV_TIMER5_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER5_TIMER_PWM   18
 
#define TISCI_DEV_TIMER6_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER6_TIMER_PWM   18
 
#define TISCI_DEV_TIMER7_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER7_TIMER_PWM   18
 
#define TISCI_DEV_TIMER8_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER8_TIMER_PWM   18
 
#define TISCI_DEV_TIMER9_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16
 
#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17
 
#define TISCI_DEV_TIMER9_TIMER_PWM   18
 
#define TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8
 
#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9
 
#define TISCI_DEV_MCU_TIMER0_TIMER_PWM   10
 
#define TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8
 
#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9
 
#define TISCI_DEV_MCU_TIMER1_TIMER_PWM   10
 
#define TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8
 
#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9
 
#define TISCI_DEV_MCU_TIMER2_TIMER_PWM   10
 
#define TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK   0
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK   1
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8
 
#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9
 
#define TISCI_DEV_MCU_TIMER3_TIMER_PWM   10
 
#define TISCI_DEV_ECAP0_VBUS_CLK   0
 
#define TISCI_DEV_ECAP1_VBUS_CLK   0
 
#define TISCI_DEV_ECAP2_VBUS_CLK   0
 
#define TISCI_DEV_ELM0_VBUSP_CLK   0
 
#define TISCI_DEV_MMCSD0_EMMCSS_VBUS_CLK   0
 
#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK   1
 
#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK   2
 
#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK   3
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I   0
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT   1
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O   2
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK   3
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK   4
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK   5
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK   6
 
#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O   7
 
#define TISCI_DEV_EQEP0_VBUS_CLK   0
 
#define TISCI_DEV_EQEP1_VBUS_CLK   0
 
#define TISCI_DEV_EQEP2_VBUS_CLK   0
 
#define TISCI_DEV_ESM0_CLK   0
 
#define TISCI_DEV_MCU_ESM0_CLK   0
 
#define TISCI_DEV_FSIRX0_FSI_RX_CK   0
 
#define TISCI_DEV_FSIRX0_FSI_RX_LPBK_CK   1
 
#define TISCI_DEV_FSIRX0_FSI_RX_VBUS_CLK   2
 
#define TISCI_DEV_FSIRX1_FSI_RX_CK   0
 
#define TISCI_DEV_FSIRX1_FSI_RX_LPBK_CK   1
 
#define TISCI_DEV_FSIRX1_FSI_RX_VBUS_CLK   2
 
#define TISCI_DEV_FSIRX2_FSI_RX_CK   0
 
#define TISCI_DEV_FSIRX2_FSI_RX_LPBK_CK   1
 
#define TISCI_DEV_FSIRX2_FSI_RX_VBUS_CLK   2
 
#define TISCI_DEV_FSIRX3_FSI_RX_CK   0
 
#define TISCI_DEV_FSIRX3_FSI_RX_LPBK_CK   1
 
#define TISCI_DEV_FSIRX3_FSI_RX_VBUS_CLK   2
 
#define TISCI_DEV_FSIRX4_FSI_RX_CK   0
 
#define TISCI_DEV_FSIRX4_FSI_RX_LPBK_CK   1
 
#define TISCI_DEV_FSIRX4_FSI_RX_VBUS_CLK   2
 
#define TISCI_DEV_FSIRX5_FSI_RX_CK   0
 
#define TISCI_DEV_FSIRX5_FSI_RX_LPBK_CK   1
 
#define TISCI_DEV_FSIRX5_FSI_RX_VBUS_CLK   2
 
#define TISCI_DEV_FSITX0_FSI_TX_PLL_CLK   0
 
#define TISCI_DEV_FSITX0_FSI_TX_VBUS_CLK   1
 
#define TISCI_DEV_FSITX0_FSI_TX_CK   2
 
#define TISCI_DEV_FSITX1_FSI_TX_PLL_CLK   0
 
#define TISCI_DEV_FSITX1_FSI_TX_VBUS_CLK   1
 
#define TISCI_DEV_FSITX1_FSI_TX_CK   2
 
#define TISCI_DEV_FSS0_FSAS_0_GCLK   0
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_DQS_CLK   0
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_HCLK_CLK   1
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK   2
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT   3
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT   4
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_PCLK_CLK   5
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK   6
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK   7
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK   8
 
#define TISCI_DEV_FSS0_OSPI_0_OSPI_OCLK_CLK   9
 
#define TISCI_DEV_GICSS0_VCLK_CLK   0
 
#define TISCI_DEV_GPIO0_MMR_CLK   0
 
#define TISCI_DEV_GPIO1_MMR_CLK   0
 
#define TISCI_DEV_MCU_GPIO0_MMR_CLK   0
 
#define TISCI_DEV_GPMC0_FUNC_CLK   0
 
#define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK   1
 
#define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK   2
 
#define TISCI_DEV_GPMC0_PI_GPMC_RET_CLK   3
 
#define TISCI_DEV_GPMC0_VBUSM_CLK   4
 
#define TISCI_DEV_GPMC0_PO_GPMC_DEV_CLK   5
 
#define TISCI_DEV_GTC0_GTC_CLK   0
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   1
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   2
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   3
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   4
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   7
 
#define TISCI_DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   8
 
#define TISCI_DEV_GTC0_VBUSP_CLK   9
 
#define TISCI_DEV_PRU_ICSSG0_CORE_CLK   0
 
#define TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK   1
 
#define TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK   2
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK   3
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   4
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   5
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   6
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   7
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   8
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   9
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   10
 
#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   11
 
#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I   12
 
#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I   13
 
#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I   14
 
#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I   15
 
#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK   16
 
#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK   17
 
#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK   18
 
#define TISCI_DEV_PRU_ICSSG0_UCLK_CLK   19
 
#define TISCI_DEV_PRU_ICSSG0_VCLK_CLK   20
 
#define TISCI_DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O   21
 
#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O   22
 
#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O   23
 
#define TISCI_DEV_PRU_ICSSG1_CORE_CLK   0
 
#define TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK   1
 
#define TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK   2
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK   3
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   4
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   5
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   6
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   7
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   8
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   9
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   10
 
#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   11
 
#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I   12
 
#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I   13
 
#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I   14
 
#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I   15
 
#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK   16
 
#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK   17
 
#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK   18
 
#define TISCI_DEV_PRU_ICSSG1_UCLK_CLK   19
 
#define TISCI_DEV_PRU_ICSSG1_VCLK_CLK   20
 
#define TISCI_DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O   21
 
#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O   22
 
#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O   23
 
#define TISCI_DEV_LED0_LED_CLK   0
 
#define TISCI_DEV_LED0_VBUS_CLK   1
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK   0
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   1
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   2
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   3
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   4
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   5
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   6
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   7
 
#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   8
 
#define TISCI_DEV_CPTS0_VBUSP_CLK   9
 
#define TISCI_DEV_CPTS0_CPTS_GENF1   10
 
#define TISCI_DEV_CPTS0_CPTS_GENF2   11
 
#define TISCI_DEV_CPTS0_CPTS_GENF3   12
 
#define TISCI_DEV_CPTS0_CPTS_GENF4   13
 
#define TISCI_DEV_DDPA0_DDPA_CLK   0
 
#define TISCI_DEV_EPWM0_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM1_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM2_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM3_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM4_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM5_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM6_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM7_VBUSP_CLK   0
 
#define TISCI_DEV_EPWM8_VBUSP_CLK   0
 
#define TISCI_DEV_PBIST0_CLK8_CLK   0
 
#define TISCI_DEV_PBIST1_CLK8_CLK   0
 
#define TISCI_DEV_PBIST2_CLK8_CLK   0
 
#define TISCI_DEV_PBIST3_CLK8_CLK   0
 
#define TISCI_DEV_VTM0_FIX_REF2_CLK   0
 
#define TISCI_DEV_VTM0_FIX_REF_CLK   1
 
#define TISCI_DEV_VTM0_VBUSP_CLK   2
 
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK   0
 
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK   1
 
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   2
 
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   3
 
#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   4
 
#define TISCI_DEV_MCAN0_MCANSS_HCLK_CLK   5
 
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK   0
 
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK   1
 
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   2
 
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   3
 
#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   4
 
#define TISCI_DEV_MCAN1_MCANSS_HCLK_CLK   5
 
#define TISCI_DEV_MCU_MCRC64_0_CLK   0
 
#define TISCI_DEV_I2C0_CLK   0
 
#define TISCI_DEV_I2C0_PISCL   1
 
#define TISCI_DEV_I2C0_PISYS_CLK   2
 
#define TISCI_DEV_I2C0_PORSCL   3
 
#define TISCI_DEV_I2C1_CLK   0
 
#define TISCI_DEV_I2C1_PISCL   1
 
#define TISCI_DEV_I2C1_PISYS_CLK   2
 
#define TISCI_DEV_I2C1_PORSCL   3
 
#define TISCI_DEV_I2C2_CLK   0
 
#define TISCI_DEV_I2C2_PISCL   1
 
#define TISCI_DEV_I2C2_PISYS_CLK   2
 
#define TISCI_DEV_I2C2_PORSCL   3
 
#define TISCI_DEV_I2C3_CLK   0
 
#define TISCI_DEV_I2C3_PISCL   1
 
#define TISCI_DEV_I2C3_PISYS_CLK   2
 
#define TISCI_DEV_I2C3_PORSCL   3
 
#define TISCI_DEV_MCU_I2C0_CLK   0
 
#define TISCI_DEV_MCU_I2C0_PISCL   1
 
#define TISCI_DEV_MCU_I2C0_PISYS_CLK   2
 
#define TISCI_DEV_MCU_I2C0_PORSCL   3
 
#define TISCI_DEV_MCU_I2C1_CLK   0
 
#define TISCI_DEV_MCU_I2C1_PISCL   1
 
#define TISCI_DEV_MCU_I2C1_PISYS_CLK   2
 
#define TISCI_DEV_MCU_I2C1_PORSCL   3
 
#define TISCI_DEV_PCIE0_PCIE_CBA_CLK   0
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK   1
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   2
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   3
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   4
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   5
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   7
 
#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   8
 
#define TISCI_DEV_PCIE0_PCIE_LANE0_REFCLK   10
 
#define TISCI_DEV_PCIE0_PCIE_LANE0_RXCLK   11
 
#define TISCI_DEV_PCIE0_PCIE_LANE0_RXFCLK   12
 
#define TISCI_DEV_PCIE0_PCIE_LANE0_TXFCLK   13
 
#define TISCI_DEV_PCIE0_PCIE_LANE0_TXMCLK   14
 
#define TISCI_DEV_PCIE0_PCIE_PM_CLK   15
 
#define TISCI_DEV_PCIE0_PCIE_LANE0_TXCLK   16
 
#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK   0
 
#define TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK   1
 
#define TISCI_DEV_R5FSS0_CORE1_CPU_CLK   0
 
#define TISCI_DEV_R5FSS0_CORE1_INTERFACE_CLK   1
 
#define TISCI_DEV_R5FSS1_CORE0_CPU_CLK   0
 
#define TISCI_DEV_R5FSS1_CORE0_INTERFACE_CLK   1
 
#define TISCI_DEV_R5FSS1_CORE1_CPU_CLK   0
 
#define TISCI_DEV_R5FSS1_CORE1_INTERFACE_CLK   1
 
#define TISCI_DEV_RTI0_RTI_CLK   0
 
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_RTI0_VBUSP_CLK   5
 
#define TISCI_DEV_RTI1_RTI_CLK   0
 
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_RTI1_VBUSP_CLK   5
 
#define TISCI_DEV_RTI8_RTI_CLK   0
 
#define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_RTI8_VBUSP_CLK   5
 
#define TISCI_DEV_RTI9_RTI_CLK   0
 
#define TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_RTI9_VBUSP_CLK   5
 
#define TISCI_DEV_RTI10_RTI_CLK   0
 
#define TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_RTI10_VBUSP_CLK   5
 
#define TISCI_DEV_RTI11_RTI_CLK   0
 
#define TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_RTI11_VBUSP_CLK   5
 
#define TISCI_DEV_MCU_RTI0_RTI_CLK   0
 
#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1
 
#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2
 
#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3
 
#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4
 
#define TISCI_DEV_MCU_RTI0_VBUSP_CLK   5
 
#define TISCI_DEV_SA2_UL0_PKA_IN_CLK   0
 
#define TISCI_DEV_SA2_UL0_X1_CLK   1
 
#define TISCI_DEV_SA2_UL0_X2_CLK   2
 
#define TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK   0
 
#define TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK   0
 
#define TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK   0
 
#define TISCI_DEV_A53SS0_PLL_CTRL_CLK   1
 
#define TISCI_DEV_DDR16SS0_DDRSS_DDR_PLL_CLK   0
 
#define TISCI_DEV_DDR16SS0_PLL_CTRL_CLK   1
 
#define TISCI_DEV_PSC0_CLK   0
 
#define TISCI_DEV_PSC0_SLOW_CLK   1
 
#define TISCI_DEV_MCU_PSC0_CLK   0
 
#define TISCI_DEV_MCU_PSC0_SLOW_CLK   1
 
#define TISCI_DEV_MCSPI0_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT   2
 
#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI0_VBUSP_CLK   4
 
#define TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_MCSPI1_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT   2
 
#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI1_VBUSP_CLK   4
 
#define TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_MCSPI2_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT   2
 
#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI2_VBUSP_CLK   4
 
#define TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_MCSPI3_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT   2
 
#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI3_VBUSP_CLK   4
 
#define TISCI_DEV_MCSPI3_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_MCSPI4_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT   2
 
#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCSPI4_VBUSP_CLK   4
 
#define TISCI_DEV_MCSPI4_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_MCU_MCSPI0_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT   2
 
#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCU_MCSPI0_VBUSP_CLK   4
 
#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_MCU_MCSPI1_CLKSPIREF_CLK   0
 
#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK   1
 
#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT   2
 
#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK   3
 
#define TISCI_DEV_MCU_MCSPI1_VBUSP_CLK   4
 
#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPIO_CLK   5
 
#define TISCI_DEV_SPINLOCK0_VCLK_CLK   0
 
#define TISCI_DEV_TIMERMGR0_VCLK_CLK   0
 
#define TISCI_DEV_UART0_FCLK_CLK   0
 
#define TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0   1
 
#define TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART0_VBUSP_CLK   3
 
#define TISCI_DEV_UART1_FCLK_CLK   0
 
#define TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1   1
 
#define TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART1_VBUSP_CLK   3
 
#define TISCI_DEV_UART2_FCLK_CLK   0
 
#define TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2   1
 
#define TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART2_VBUSP_CLK   3
 
#define TISCI_DEV_UART3_FCLK_CLK   0
 
#define TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3   1
 
#define TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART3_VBUSP_CLK   3
 
#define TISCI_DEV_UART4_FCLK_CLK   0
 
#define TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4   1
 
#define TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART4_VBUSP_CLK   3
 
#define TISCI_DEV_UART5_FCLK_CLK   0
 
#define TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5   1
 
#define TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART5_VBUSP_CLK   3
 
#define TISCI_DEV_UART6_FCLK_CLK   0
 
#define TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6   1
 
#define TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2
 
#define TISCI_DEV_UART6_VBUSP_CLK   3
 
#define TISCI_DEV_MCU_UART0_FCLK_CLK   0
 
#define TISCI_DEV_MCU_UART0_VBUSP_CLK   1
 
#define TISCI_DEV_MCU_UART1_FCLK_CLK   0
 
#define TISCI_DEV_MCU_UART1_VBUSP_CLK   1
 
#define TISCI_DEV_USB0_ACLK_CLK   0
 
#define TISCI_DEV_USB0_CLK_LPM_CLK   1
 
#define TISCI_DEV_USB0_PCLK_CLK   2
 
#define TISCI_DEV_USB0_PIPE_REFCLK   3
 
#define TISCI_DEV_USB0_PIPE_RXCLK   4
 
#define TISCI_DEV_USB0_PIPE_RXFCLK   5
 
#define TISCI_DEV_USB0_PIPE_TXFCLK   6
 
#define TISCI_DEV_USB0_PIPE_TXMCLK   7
 
#define TISCI_DEV_USB0_USB2_APB_PCLK_CLK   8
 
#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK   9
 
#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   10
 
#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK   11
 
#define TISCI_DEV_USB0_PIPE_TXCLK   12
 
#define TISCI_DEV_SERDES_10G0_CLK   0
 
#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK   1
 
#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2
 
#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   3
 
#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK   4
 
#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK   5
 
#define TISCI_DEV_SERDES_10G0_IP1_LN0_TXCLK   6
 
#define TISCI_DEV_SERDES_10G0_IP2_LN0_TXCLK   7
 
#define TISCI_DEV_SERDES_10G0_IP1_LN0_REFCLK   8
 
#define TISCI_DEV_SERDES_10G0_IP1_LN0_RXCLK   9
 
#define TISCI_DEV_SERDES_10G0_IP1_LN0_RXFCLK   10
 
#define TISCI_DEV_SERDES_10G0_IP1_LN0_TXFCLK   11
 
#define TISCI_DEV_SERDES_10G0_IP1_LN0_TXMCLK   12
 
#define TISCI_DEV_SERDES_10G0_IP2_LN0_REFCLK   13
 
#define TISCI_DEV_SERDES_10G0_IP2_LN0_RXCLK   14
 
#define TISCI_DEV_SERDES_10G0_IP2_LN0_RXFCLK   15
 
#define TISCI_DEV_SERDES_10G0_IP2_LN0_TXFCLK   16
 
#define TISCI_DEV_SERDES_10G0_IP2_LN0_TXMCLK   17
 
#define TISCI_DEV_BOARD0_FSI_TX0_CLK_IN   0
 
#define TISCI_DEV_BOARD0_FSI_TX1_CLK_IN   1
 
#define TISCI_DEV_BOARD0_GPMC0_CLKLB_IN   2
 
#define TISCI_DEV_BOARD0_GPMC0_CLK_IN   3
 
#define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN   4
 
#define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK   5
 
#define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK   6
 
#define TISCI_DEV_BOARD0_I2C0_SCL_IN   7
 
#define TISCI_DEV_BOARD0_I2C1_SCL_IN   8
 
#define TISCI_DEV_BOARD0_I2C2_SCL_IN   9
 
#define TISCI_DEV_BOARD0_I2C3_SCL_IN   10
 
#define TISCI_DEV_BOARD0_MCU_I2C0_SCL_IN   11
 
#define TISCI_DEV_BOARD0_MCU_I2C1_SCL_IN   12
 
#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN   13
 
#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0   14
 
#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT   15
 
#define TISCI_DEV_BOARD0_MCU_SPI0_CLK_IN   16
 
#define TISCI_DEV_BOARD0_MCU_SPI1_CLK_IN   17
 
#define TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN   18
 
#define TISCI_DEV_BOARD0_MCU_TIMER_IO0_IN   19
 
#define TISCI_DEV_BOARD0_MCU_TIMER_IO1_IN   20
 
#define TISCI_DEV_BOARD0_MCU_TIMER_IO2_IN   21
 
#define TISCI_DEV_BOARD0_MCU_TIMER_IO3_IN   22
 
#define TISCI_DEV_BOARD0_MMC1_CLK_IN   23
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN   24
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK   25
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK   26
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   27
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   28
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   29
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   30
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   31
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK   32
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK   33
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK   34
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK   35
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT   36
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   37
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0   38
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT   39
 
#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   40
 
#define TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN   41
 
#define TISCI_DEV_BOARD0_PRG0_MDIO0_MDC_IN   42
 
#define TISCI_DEV_BOARD0_PRG0_RGMII1_TXC_IN   43
 
#define TISCI_DEV_BOARD0_PRG0_RGMII2_TXC_IN   44
 
#define TISCI_DEV_BOARD0_PRG1_MDIO0_MDC_IN   45
 
#define TISCI_DEV_BOARD0_PRG1_RGMII1_TXC_IN   46
 
#define TISCI_DEV_BOARD0_PRG1_RGMII2_TXC_IN   47
 
#define TISCI_DEV_BOARD0_RGMII1_TXC_IN   48
 
#define TISCI_DEV_BOARD0_RGMII2_TXC_IN   49
 
#define TISCI_DEV_BOARD0_SPI0_CLK_IN   50
 
#define TISCI_DEV_BOARD0_SPI1_CLK_IN   51
 
#define TISCI_DEV_BOARD0_SPI2_CLK_IN   52
 
#define TISCI_DEV_BOARD0_SPI3_CLK_IN   53
 
#define TISCI_DEV_BOARD0_SPI4_CLK_IN   54
 
#define TISCI_DEV_BOARD0_SYSCLKOUT0_IN   55
 
#define TISCI_DEV_BOARD0_TIMER_IO0_IN   56
 
#define TISCI_DEV_BOARD0_TIMER_IO10_IN   57
 
#define TISCI_DEV_BOARD0_TIMER_IO11_IN   58
 
#define TISCI_DEV_BOARD0_TIMER_IO1_IN   59
 
#define TISCI_DEV_BOARD0_TIMER_IO2_IN   60
 
#define TISCI_DEV_BOARD0_TIMER_IO3_IN   61
 
#define TISCI_DEV_BOARD0_TIMER_IO4_IN   62
 
#define TISCI_DEV_BOARD0_TIMER_IO5_IN   63
 
#define TISCI_DEV_BOARD0_TIMER_IO6_IN   64
 
#define TISCI_DEV_BOARD0_TIMER_IO7_IN   65
 
#define TISCI_DEV_BOARD0_TIMER_IO8_IN   66
 
#define TISCI_DEV_BOARD0_TIMER_IO9_IN   67
 
#define TISCI_DEV_BOARD0_CPTS0_RFT_CLK_OUT   68
 
#define TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT   69
 
#define TISCI_DEV_BOARD0_EXT_REFCLK1_OUT   70
 
#define TISCI_DEV_BOARD0_FSI_RX0_CLK_OUT   71
 
#define TISCI_DEV_BOARD0_FSI_RX1_CLK_OUT   72
 
#define TISCI_DEV_BOARD0_FSI_RX2_CLK_OUT   73
 
#define TISCI_DEV_BOARD0_FSI_RX3_CLK_OUT   74
 
#define TISCI_DEV_BOARD0_FSI_RX4_CLK_OUT   75
 
#define TISCI_DEV_BOARD0_FSI_RX5_CLK_OUT   76
 
#define TISCI_DEV_BOARD0_GPMC0_CLKLB_OUT   77
 
#define TISCI_DEV_BOARD0_I2C0_SCL_OUT   78
 
#define TISCI_DEV_BOARD0_I2C1_SCL_OUT   79
 
#define TISCI_DEV_BOARD0_I2C2_SCL_OUT   80
 
#define TISCI_DEV_BOARD0_I2C3_SCL_OUT   81
 
#define TISCI_DEV_BOARD0_LED_CLK_OUT   82
 
#define TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT   83
 
#define TISCI_DEV_BOARD0_MCU_I2C0_SCL_OUT   84
 
#define TISCI_DEV_BOARD0_MCU_I2C1_SCL_OUT   85
 
#define TISCI_DEV_BOARD0_MCU_SPI0_CLK_OUT   86
 
#define TISCI_DEV_BOARD0_MCU_SPI1_CLK_OUT   87
 
#define TISCI_DEV_BOARD0_MMC1_CLKLB_OUT   88
 
#define TISCI_DEV_BOARD0_OSPI0_DQS_OUT   89
 
#define TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT   90
 
#define TISCI_DEV_BOARD0_PRG0_RGMII1_RXC_OUT   91
 
#define TISCI_DEV_BOARD0_PRG0_RGMII1_TXC_OUT   92
 
#define TISCI_DEV_BOARD0_PRG0_RGMII2_RXC_OUT   93
 
#define TISCI_DEV_BOARD0_PRG0_RGMII2_TXC_OUT   94
 
#define TISCI_DEV_BOARD0_PRG1_RGMII1_RXC_OUT   95
 
#define TISCI_DEV_BOARD0_PRG1_RGMII1_TXC_OUT   96
 
#define TISCI_DEV_BOARD0_PRG1_RGMII2_RXC_OUT   97
 
#define TISCI_DEV_BOARD0_PRG1_RGMII2_TXC_OUT   98
 
#define TISCI_DEV_BOARD0_RGMII1_RXC_OUT   99
 
#define TISCI_DEV_BOARD0_RGMII1_TXC_OUT   100
 
#define TISCI_DEV_BOARD0_RGMII2_RXC_OUT   101
 
#define TISCI_DEV_BOARD0_RGMII2_TXC_OUT   102
 
#define TISCI_DEV_BOARD0_RMII_REF_CLK_OUT   103
 
#define TISCI_DEV_BOARD0_SPI0_CLK_OUT   104
 
#define TISCI_DEV_BOARD0_SPI1_CLK_OUT   105
 
#define TISCI_DEV_BOARD0_SPI2_CLK_OUT   106
 
#define TISCI_DEV_BOARD0_SPI3_CLK_OUT   107
 
#define TISCI_DEV_BOARD0_SPI4_CLK_OUT   108
 
#define TISCI_DEV_BOARD0_TCK_OUT   109
 
#define TISCI_DEV_BOARD0_CLKOUT0_IN   123
 
#define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK5   124
 
#define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK10   125
 

Macro Definition Documentation

◆ TISCI_DEV_ADC0_ADC_CLK

#define TISCI_DEV_ADC0_ADC_CLK   0

This file contains:

    WARNING!!: Autogenerated file from SYSFW. DO NOT MODIFY!!

Data version: 230209_212853

◆ TISCI_DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_ADC0_ADC_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK

#define TISCI_DEV_ADC0_ADC_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT6_CLK   2

◆ TISCI_DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK

#define TISCI_DEV_ADC0_ADC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT8_CLK   3

◆ TISCI_DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_ADC0_ADC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   4

◆ TISCI_DEV_ADC0_SYS_CLK

#define TISCI_DEV_ADC0_SYS_CLK   5

◆ TISCI_DEV_ADC0_VBUS_CLK

#define TISCI_DEV_ADC0_VBUS_CLK   6

◆ TISCI_DEV_CMP_EVENT_INTROUTER0_INTR_CLK

#define TISCI_DEV_CMP_EVENT_INTROUTER0_INTR_CLK   0

◆ TISCI_DEV_DBGSUSPENDROUTER0_INTR_CLK

#define TISCI_DEV_DBGSUSPENDROUTER0_INTR_CLK   0

◆ TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK

#define TISCI_DEV_MAIN_GPIOMUX_INTROUTER0_INTR_CLK   0

◆ TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK

#define TISCI_DEV_MCU_MCU_GPIOMUX_INTROUTER0_INTR_CLK   0

◆ TISCI_DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK

#define TISCI_DEV_TIMESYNC_EVENT_INTROUTER0_INTR_CLK   0

◆ TISCI_DEV_MCU_M4FSS0_CBASS_0_CLK

#define TISCI_DEV_MCU_M4FSS0_CBASS_0_CLK   0

◆ TISCI_DEV_MCU_M4FSS0_CORE0_DAP_CLK

#define TISCI_DEV_MCU_M4FSS0_CORE0_DAP_CLK   0

◆ TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK

#define TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK   1

◆ TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK

#define TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK   2

◆ TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2

#define TISCI_DEV_MCU_M4FSS0_CORE0_VBUS_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK2   3

◆ TISCI_DEV_CPSW0_CPPI_CLK_CLK

#define TISCI_DEV_CPSW0_CPPI_CLK_CLK   0

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK   1

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   2

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   3

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   4

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   5

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   7

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   8

◆ TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK

#define TISCI_DEV_CPSW0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   9

◆ TISCI_DEV_CPSW0_GMII1_MR_CLK

#define TISCI_DEV_CPSW0_GMII1_MR_CLK   10

◆ TISCI_DEV_CPSW0_GMII1_MT_CLK

#define TISCI_DEV_CPSW0_GMII1_MT_CLK   11

◆ TISCI_DEV_CPSW0_GMII2_MR_CLK

#define TISCI_DEV_CPSW0_GMII2_MR_CLK   12

◆ TISCI_DEV_CPSW0_GMII2_MT_CLK

#define TISCI_DEV_CPSW0_GMII2_MT_CLK   13

◆ TISCI_DEV_CPSW0_GMII_RFT_CLK

#define TISCI_DEV_CPSW0_GMII_RFT_CLK   14

◆ TISCI_DEV_CPSW0_RGMII1_RXC_I

#define TISCI_DEV_CPSW0_RGMII1_RXC_I   15

◆ TISCI_DEV_CPSW0_RGMII1_TXC_I

#define TISCI_DEV_CPSW0_RGMII1_TXC_I   16

◆ TISCI_DEV_CPSW0_RGMII2_RXC_I

#define TISCI_DEV_CPSW0_RGMII2_RXC_I   17

◆ TISCI_DEV_CPSW0_RGMII2_TXC_I

#define TISCI_DEV_CPSW0_RGMII2_TXC_I   18

◆ TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK

#define TISCI_DEV_CPSW0_RGMII_MHZ_250_CLK   19

◆ TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK

#define TISCI_DEV_CPSW0_RGMII_MHZ_50_CLK   20

◆ TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK

#define TISCI_DEV_CPSW0_RGMII_MHZ_5_CLK   21

◆ TISCI_DEV_CPSW0_RMII_MHZ_50_CLK

#define TISCI_DEV_CPSW0_RMII_MHZ_50_CLK   22

◆ TISCI_DEV_CPSW0_CPTS_GENF0

#define TISCI_DEV_CPSW0_CPTS_GENF0   23

◆ TISCI_DEV_CPSW0_CPTS_GENF1

#define TISCI_DEV_CPSW0_CPTS_GENF1   24

◆ TISCI_DEV_CPSW0_RGMII1_TXC_O

#define TISCI_DEV_CPSW0_RGMII1_TXC_O   25

◆ TISCI_DEV_CPSW0_RGMII2_TXC_O

#define TISCI_DEV_CPSW0_RGMII2_TXC_O   26

◆ TISCI_DEV_CPT2_AGGR0_VCLK_CLK

#define TISCI_DEV_CPT2_AGGR0_VCLK_CLK   0

◆ TISCI_DEV_STM0_ATB_CLK

#define TISCI_DEV_STM0_ATB_CLK   0

◆ TISCI_DEV_STM0_CORE_CLK

#define TISCI_DEV_STM0_CORE_CLK   1

◆ TISCI_DEV_STM0_VBUSP_CLK

#define TISCI_DEV_STM0_VBUSP_CLK   2

◆ TISCI_DEV_DCC0_DCC_CLKSRC0_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_DCC0_DCC_CLKSRC1_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC1_CLK   1

◆ TISCI_DEV_DCC0_DCC_CLKSRC2_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC2_CLK   2

◆ TISCI_DEV_DCC0_DCC_CLKSRC3_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC3_CLK   3

◆ TISCI_DEV_DCC0_DCC_CLKSRC4_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC4_CLK   4

◆ TISCI_DEV_DCC0_DCC_CLKSRC5_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC5_CLK   5

◆ TISCI_DEV_DCC0_DCC_CLKSRC6_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC6_CLK   6

◆ TISCI_DEV_DCC0_DCC_CLKSRC7_CLK

#define TISCI_DEV_DCC0_DCC_CLKSRC7_CLK   7

◆ TISCI_DEV_DCC0_DCC_INPUT00_CLK

#define TISCI_DEV_DCC0_DCC_INPUT00_CLK   8

◆ TISCI_DEV_DCC0_DCC_INPUT01_CLK

#define TISCI_DEV_DCC0_DCC_INPUT01_CLK   9

◆ TISCI_DEV_DCC0_DCC_INPUT02_CLK

#define TISCI_DEV_DCC0_DCC_INPUT02_CLK   10

◆ TISCI_DEV_DCC0_DCC_INPUT10_CLK

#define TISCI_DEV_DCC0_DCC_INPUT10_CLK   11

◆ TISCI_DEV_DCC0_VBUS_CLK

#define TISCI_DEV_DCC0_VBUS_CLK   12

◆ TISCI_DEV_DCC1_DCC_CLKSRC0_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_DCC1_DCC_CLKSRC1_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC1_CLK   1

◆ TISCI_DEV_DCC1_DCC_CLKSRC2_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC2_CLK   2

◆ TISCI_DEV_DCC1_DCC_CLKSRC3_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC3_CLK   3

◆ TISCI_DEV_DCC1_DCC_CLKSRC4_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC4_CLK   4

◆ TISCI_DEV_DCC1_DCC_CLKSRC5_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC5_CLK   5

◆ TISCI_DEV_DCC1_DCC_CLKSRC6_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC6_CLK   6

◆ TISCI_DEV_DCC1_DCC_CLKSRC7_CLK

#define TISCI_DEV_DCC1_DCC_CLKSRC7_CLK   7

◆ TISCI_DEV_DCC1_DCC_INPUT00_CLK

#define TISCI_DEV_DCC1_DCC_INPUT00_CLK   8

◆ TISCI_DEV_DCC1_DCC_INPUT01_CLK

#define TISCI_DEV_DCC1_DCC_INPUT01_CLK   9

◆ TISCI_DEV_DCC1_DCC_INPUT02_CLK

#define TISCI_DEV_DCC1_DCC_INPUT02_CLK   10

◆ TISCI_DEV_DCC1_DCC_INPUT10_CLK

#define TISCI_DEV_DCC1_DCC_INPUT10_CLK   11

◆ TISCI_DEV_DCC1_VBUS_CLK

#define TISCI_DEV_DCC1_VBUS_CLK   12

◆ TISCI_DEV_DCC2_DCC_CLKSRC0_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_DCC2_DCC_CLKSRC1_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC1_CLK   1

◆ TISCI_DEV_DCC2_DCC_CLKSRC2_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC2_CLK   2

◆ TISCI_DEV_DCC2_DCC_CLKSRC3_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC3_CLK   3

◆ TISCI_DEV_DCC2_DCC_CLKSRC4_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC4_CLK   4

◆ TISCI_DEV_DCC2_DCC_CLKSRC5_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC5_CLK   5

◆ TISCI_DEV_DCC2_DCC_CLKSRC6_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC6_CLK   6

◆ TISCI_DEV_DCC2_DCC_CLKSRC7_CLK

#define TISCI_DEV_DCC2_DCC_CLKSRC7_CLK   7

◆ TISCI_DEV_DCC2_DCC_INPUT00_CLK

#define TISCI_DEV_DCC2_DCC_INPUT00_CLK   8

◆ TISCI_DEV_DCC2_DCC_INPUT01_CLK

#define TISCI_DEV_DCC2_DCC_INPUT01_CLK   9

◆ TISCI_DEV_DCC2_DCC_INPUT02_CLK

#define TISCI_DEV_DCC2_DCC_INPUT02_CLK   10

◆ TISCI_DEV_DCC2_DCC_INPUT10_CLK

#define TISCI_DEV_DCC2_DCC_INPUT10_CLK   11

◆ TISCI_DEV_DCC2_VBUS_CLK

#define TISCI_DEV_DCC2_VBUS_CLK   12

◆ TISCI_DEV_DCC3_DCC_CLKSRC0_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_DCC3_DCC_CLKSRC1_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC1_CLK   1

◆ TISCI_DEV_DCC3_DCC_CLKSRC2_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC2_CLK   2

◆ TISCI_DEV_DCC3_DCC_CLKSRC3_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC3_CLK   3

◆ TISCI_DEV_DCC3_DCC_CLKSRC4_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC4_CLK   4

◆ TISCI_DEV_DCC3_DCC_CLKSRC5_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC5_CLK   5

◆ TISCI_DEV_DCC3_DCC_CLKSRC6_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC6_CLK   6

◆ TISCI_DEV_DCC3_DCC_CLKSRC7_CLK

#define TISCI_DEV_DCC3_DCC_CLKSRC7_CLK   7

◆ TISCI_DEV_DCC3_DCC_INPUT00_CLK

#define TISCI_DEV_DCC3_DCC_INPUT00_CLK   8

◆ TISCI_DEV_DCC3_DCC_INPUT01_CLK

#define TISCI_DEV_DCC3_DCC_INPUT01_CLK   9

◆ TISCI_DEV_DCC3_DCC_INPUT02_CLK

#define TISCI_DEV_DCC3_DCC_INPUT02_CLK   10

◆ TISCI_DEV_DCC3_DCC_INPUT10_CLK

#define TISCI_DEV_DCC3_DCC_INPUT10_CLK   11

◆ TISCI_DEV_DCC3_VBUS_CLK

#define TISCI_DEV_DCC3_VBUS_CLK   12

◆ TISCI_DEV_DCC4_DCC_CLKSRC0_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK   1

◆ TISCI_DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC0_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK   2

◆ TISCI_DEV_DCC4_DCC_CLKSRC1_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC1_CLK   3

◆ TISCI_DEV_DCC4_DCC_CLKSRC2_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC2_CLK   4

◆ TISCI_DEV_DCC4_DCC_CLKSRC3_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC3_CLK   5

◆ TISCI_DEV_DCC4_DCC_CLKSRC4_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC4_CLK   6

◆ TISCI_DEV_DCC4_DCC_CLKSRC5_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC5_CLK   7

◆ TISCI_DEV_DCC4_DCC_CLKSRC6_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC6_CLK   8

◆ TISCI_DEV_DCC4_DCC_CLKSRC7_CLK

#define TISCI_DEV_DCC4_DCC_CLKSRC7_CLK   9

◆ TISCI_DEV_DCC4_DCC_INPUT00_CLK

#define TISCI_DEV_DCC4_DCC_INPUT00_CLK   10

◆ TISCI_DEV_DCC4_DCC_INPUT01_CLK

#define TISCI_DEV_DCC4_DCC_INPUT01_CLK   11

◆ TISCI_DEV_DCC4_DCC_INPUT02_CLK

#define TISCI_DEV_DCC4_DCC_INPUT02_CLK   12

◆ TISCI_DEV_DCC4_DCC_INPUT10_CLK

#define TISCI_DEV_DCC4_DCC_INPUT10_CLK   13

◆ TISCI_DEV_DCC4_VBUS_CLK

#define TISCI_DEV_DCC4_VBUS_CLK   14

◆ TISCI_DEV_DCC5_DCC_CLKSRC0_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_DCC5_DCC_CLKSRC1_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC1_CLK   1

◆ TISCI_DEV_DCC5_DCC_CLKSRC2_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC2_CLK   2

◆ TISCI_DEV_DCC5_DCC_CLKSRC3_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC3_CLK   3

◆ TISCI_DEV_DCC5_DCC_CLKSRC4_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC4_CLK   4

◆ TISCI_DEV_DCC5_DCC_CLKSRC5_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC5_CLK   5

◆ TISCI_DEV_DCC5_DCC_CLKSRC6_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC6_CLK   6

◆ TISCI_DEV_DCC5_DCC_CLKSRC7_CLK

#define TISCI_DEV_DCC5_DCC_CLKSRC7_CLK   7

◆ TISCI_DEV_DCC5_DCC_INPUT00_CLK

#define TISCI_DEV_DCC5_DCC_INPUT00_CLK   8

◆ TISCI_DEV_DCC5_DCC_INPUT01_CLK

#define TISCI_DEV_DCC5_DCC_INPUT01_CLK   9

◆ TISCI_DEV_DCC5_DCC_INPUT02_CLK

#define TISCI_DEV_DCC5_DCC_INPUT02_CLK   10

◆ TISCI_DEV_DCC5_DCC_INPUT10_CLK

#define TISCI_DEV_DCC5_DCC_INPUT10_CLK   11

◆ TISCI_DEV_DCC5_VBUS_CLK

#define TISCI_DEV_DCC5_VBUS_CLK   12

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC0_CLK   0

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC1_CLK   1

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC2_CLK   2

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC3_CLK   3

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC4_CLK   4

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC5_CLK   5

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC6_CLK   6

◆ TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK

#define TISCI_DEV_MCU_DCC0_DCC_CLKSRC7_CLK   7

◆ TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK

#define TISCI_DEV_MCU_DCC0_DCC_INPUT00_CLK   8

◆ TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK

#define TISCI_DEV_MCU_DCC0_DCC_INPUT01_CLK   9

◆ TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK

#define TISCI_DEV_MCU_DCC0_DCC_INPUT02_CLK   10

◆ TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK

#define TISCI_DEV_MCU_DCC0_DCC_INPUT10_CLK   11

◆ TISCI_DEV_MCU_DCC0_VBUS_CLK

#define TISCI_DEV_MCU_DCC0_VBUS_CLK   12

◆ TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK

#define TISCI_DEV_DEBUGSS_WRAP0_ATB_CLK   0

◆ TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK

#define TISCI_DEV_DEBUGSS_WRAP0_CORE_CLK   1

◆ TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK

#define TISCI_DEV_DEBUGSS_WRAP0_JTAG_TCK   2

◆ TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK

#define TISCI_DEV_DEBUGSS_WRAP0_TREXPT_CLK   3

◆ TISCI_DEV_DMASS0_BCDMA_0_CLK

#define TISCI_DEV_DMASS0_BCDMA_0_CLK   0

◆ TISCI_DEV_DMASS0_CBASS_0_CLK

#define TISCI_DEV_DMASS0_CBASS_0_CLK   0

◆ TISCI_DEV_DMASS0_INTAGGR_0_CLK

#define TISCI_DEV_DMASS0_INTAGGR_0_CLK   0

◆ TISCI_DEV_DMASS0_IPCSS_0_CLK

#define TISCI_DEV_DMASS0_IPCSS_0_CLK   0

◆ TISCI_DEV_DMASS0_PKTDMA_0_CLK

#define TISCI_DEV_DMASS0_PKTDMA_0_CLK   0

◆ TISCI_DEV_DMASS0_RINGACC_0_CLK

#define TISCI_DEV_DMASS0_RINGACC_0_CLK   0

◆ TISCI_DEV_TIMER0_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER0_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER0_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER0_TIMER_PWM

#define TISCI_DEV_TIMER0_TIMER_PWM   18

◆ TISCI_DEV_TIMER1_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER1_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER1_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER1_TIMER_PWM

#define TISCI_DEV_TIMER1_TIMER_PWM   18

◆ TISCI_DEV_TIMER10_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER10_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER10_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER10_TIMER_PWM

#define TISCI_DEV_TIMER10_TIMER_PWM   18

◆ TISCI_DEV_TIMER11_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER11_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER11_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER11_TIMER_PWM

#define TISCI_DEV_TIMER11_TIMER_PWM   18

◆ TISCI_DEV_TIMER2_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER2_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER2_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER2_TIMER_PWM

#define TISCI_DEV_TIMER2_TIMER_PWM   18

◆ TISCI_DEV_TIMER3_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER3_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER3_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER3_TIMER_PWM

#define TISCI_DEV_TIMER3_TIMER_PWM   18

◆ TISCI_DEV_TIMER4_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER4_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER4_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER4_TIMER_PWM

#define TISCI_DEV_TIMER4_TIMER_PWM   18

◆ TISCI_DEV_TIMER5_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER5_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER5_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER5_TIMER_PWM

#define TISCI_DEV_TIMER5_TIMER_PWM   18

◆ TISCI_DEV_TIMER6_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER6_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER6_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER6_TIMER_PWM

#define TISCI_DEV_TIMER6_TIMER_PWM   18

◆ TISCI_DEV_TIMER7_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER7_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER7_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER7_TIMER_PWM

#define TISCI_DEV_TIMER7_TIMER_PWM   18

◆ TISCI_DEV_TIMER8_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER8_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER8_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER8_TIMER_PWM

#define TISCI_DEV_TIMER8_TIMER_PWM   18

◆ TISCI_DEV_TIMER9_TIMER_HCLK_CLK

#define TISCI_DEV_TIMER9_TIMER_HCLK_CLK   0

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK   1

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   3

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   4

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   5

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   6

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   7

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   8

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_K3_CPTS_MAIN_0_CPTS_GENF4   9

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT7_CLK   10

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   11

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   12

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   13

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   14

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   15

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT3_CLK   16

◆ TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK

#define TISCI_DEV_TIMER9_TIMER_TCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT6_CLK   17

◆ TISCI_DEV_TIMER9_TIMER_PWM

#define TISCI_DEV_TIMER9_TIMER_PWM   18

◆ TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK

#define TISCI_DEV_MCU_TIMER0_TIMER_HCLK_CLK   0

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK   1

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8

◆ TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_MCU_TIMER0_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9

◆ TISCI_DEV_MCU_TIMER0_TIMER_PWM

#define TISCI_DEV_MCU_TIMER0_TIMER_PWM   10

◆ TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK

#define TISCI_DEV_MCU_TIMER1_TIMER_HCLK_CLK   0

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK   1

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8

◆ TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_MCU_TIMER1_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9

◆ TISCI_DEV_MCU_TIMER1_TIMER_PWM

#define TISCI_DEV_MCU_TIMER1_TIMER_PWM   10

◆ TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK

#define TISCI_DEV_MCU_TIMER2_TIMER_HCLK_CLK   0

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK   1

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8

◆ TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_MCU_TIMER2_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9

◆ TISCI_DEV_MCU_TIMER2_TIMER_PWM

#define TISCI_DEV_MCU_TIMER2_TIMER_PWM   10

◆ TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK

#define TISCI_DEV_MCU_TIMER3_TIMER_HCLK_CLK   0

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK   1

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_K3_PLL_CTRL_WRAP_MCU_0_CHIP_DIV1_CLK_CLK4   3

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   4

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV4_16FFT_MCU_0_HSDIVOUT3_CLK   5

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   7

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   8

◆ TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_MCU_TIMER3_TIMER_TCLK_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   9

◆ TISCI_DEV_MCU_TIMER3_TIMER_PWM

#define TISCI_DEV_MCU_TIMER3_TIMER_PWM   10

◆ TISCI_DEV_ECAP0_VBUS_CLK

#define TISCI_DEV_ECAP0_VBUS_CLK   0

◆ TISCI_DEV_ECAP1_VBUS_CLK

#define TISCI_DEV_ECAP1_VBUS_CLK   0

◆ TISCI_DEV_ECAP2_VBUS_CLK

#define TISCI_DEV_ECAP2_VBUS_CLK   0

◆ TISCI_DEV_ELM0_VBUSP_CLK

#define TISCI_DEV_ELM0_VBUSP_CLK   0

◆ TISCI_DEV_MMCSD0_EMMCSS_VBUS_CLK

#define TISCI_DEV_MMCSD0_EMMCSS_VBUS_CLK   0

◆ TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK

#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK   1

◆ TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK

#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK   2

◆ TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK

#define TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK   3

◆ TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I

#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I   0

◆ TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT

#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_BOARD_0_MMC1_CLKLB_OUT   1

◆ TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O

#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_I_PARENT_EMMCSD4SS_MAIN_0_EMMCSDSS_IO_CLK_O   2

◆ TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK

#define TISCI_DEV_MMCSD1_EMMCSDSS_VBUS_CLK   3

◆ TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK

#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK   4

◆ TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK

#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT5_CLK   5

◆ TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK

#define TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT2_CLK   6

◆ TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O

#define TISCI_DEV_MMCSD1_EMMCSDSS_IO_CLK_O   7

◆ TISCI_DEV_EQEP0_VBUS_CLK

#define TISCI_DEV_EQEP0_VBUS_CLK   0

◆ TISCI_DEV_EQEP1_VBUS_CLK

#define TISCI_DEV_EQEP1_VBUS_CLK   0

◆ TISCI_DEV_EQEP2_VBUS_CLK

#define TISCI_DEV_EQEP2_VBUS_CLK   0

◆ TISCI_DEV_ESM0_CLK

#define TISCI_DEV_ESM0_CLK   0

◆ TISCI_DEV_MCU_ESM0_CLK

#define TISCI_DEV_MCU_ESM0_CLK   0

◆ TISCI_DEV_FSIRX0_FSI_RX_CK

#define TISCI_DEV_FSIRX0_FSI_RX_CK   0

◆ TISCI_DEV_FSIRX0_FSI_RX_LPBK_CK

#define TISCI_DEV_FSIRX0_FSI_RX_LPBK_CK   1

◆ TISCI_DEV_FSIRX0_FSI_RX_VBUS_CLK

#define TISCI_DEV_FSIRX0_FSI_RX_VBUS_CLK   2

◆ TISCI_DEV_FSIRX1_FSI_RX_CK

#define TISCI_DEV_FSIRX1_FSI_RX_CK   0

◆ TISCI_DEV_FSIRX1_FSI_RX_LPBK_CK

#define TISCI_DEV_FSIRX1_FSI_RX_LPBK_CK   1

◆ TISCI_DEV_FSIRX1_FSI_RX_VBUS_CLK

#define TISCI_DEV_FSIRX1_FSI_RX_VBUS_CLK   2

◆ TISCI_DEV_FSIRX2_FSI_RX_CK

#define TISCI_DEV_FSIRX2_FSI_RX_CK   0

◆ TISCI_DEV_FSIRX2_FSI_RX_LPBK_CK

#define TISCI_DEV_FSIRX2_FSI_RX_LPBK_CK   1

◆ TISCI_DEV_FSIRX2_FSI_RX_VBUS_CLK

#define TISCI_DEV_FSIRX2_FSI_RX_VBUS_CLK   2

◆ TISCI_DEV_FSIRX3_FSI_RX_CK

#define TISCI_DEV_FSIRX3_FSI_RX_CK   0

◆ TISCI_DEV_FSIRX3_FSI_RX_LPBK_CK

#define TISCI_DEV_FSIRX3_FSI_RX_LPBK_CK   1

◆ TISCI_DEV_FSIRX3_FSI_RX_VBUS_CLK

#define TISCI_DEV_FSIRX3_FSI_RX_VBUS_CLK   2

◆ TISCI_DEV_FSIRX4_FSI_RX_CK

#define TISCI_DEV_FSIRX4_FSI_RX_CK   0

◆ TISCI_DEV_FSIRX4_FSI_RX_LPBK_CK

#define TISCI_DEV_FSIRX4_FSI_RX_LPBK_CK   1

◆ TISCI_DEV_FSIRX4_FSI_RX_VBUS_CLK

#define TISCI_DEV_FSIRX4_FSI_RX_VBUS_CLK   2

◆ TISCI_DEV_FSIRX5_FSI_RX_CK

#define TISCI_DEV_FSIRX5_FSI_RX_CK   0

◆ TISCI_DEV_FSIRX5_FSI_RX_LPBK_CK

#define TISCI_DEV_FSIRX5_FSI_RX_LPBK_CK   1

◆ TISCI_DEV_FSIRX5_FSI_RX_VBUS_CLK

#define TISCI_DEV_FSIRX5_FSI_RX_VBUS_CLK   2

◆ TISCI_DEV_FSITX0_FSI_TX_PLL_CLK

#define TISCI_DEV_FSITX0_FSI_TX_PLL_CLK   0

◆ TISCI_DEV_FSITX0_FSI_TX_VBUS_CLK

#define TISCI_DEV_FSITX0_FSI_TX_VBUS_CLK   1

◆ TISCI_DEV_FSITX0_FSI_TX_CK

#define TISCI_DEV_FSITX0_FSI_TX_CK   2

◆ TISCI_DEV_FSITX1_FSI_TX_PLL_CLK

#define TISCI_DEV_FSITX1_FSI_TX_PLL_CLK   0

◆ TISCI_DEV_FSITX1_FSI_TX_VBUS_CLK

#define TISCI_DEV_FSITX1_FSI_TX_VBUS_CLK   1

◆ TISCI_DEV_FSITX1_FSI_TX_CK

#define TISCI_DEV_FSITX1_FSI_TX_CK   2

◆ TISCI_DEV_FSS0_FSAS_0_GCLK

#define TISCI_DEV_FSS0_FSAS_0_GCLK   0

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_DQS_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_DQS_CLK   0

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_HCLK_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_HCLK_CLK   1

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK   2

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT

#define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_DQS_OUT   3

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT

#define TISCI_DEV_FSS0_OSPI_0_OSPI_ICLK_CLK_PARENT_BOARD_0_OSPI0_LBCLKO_OUT   4

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_PCLK_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_PCLK_CLK   5

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK   6

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT1_CLK   7

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK_PARENT_POSTDIV1_16FFT_MAIN_1_HSDIVOUT5_CLK   8

◆ TISCI_DEV_FSS0_OSPI_0_OSPI_OCLK_CLK

#define TISCI_DEV_FSS0_OSPI_0_OSPI_OCLK_CLK   9

◆ TISCI_DEV_GICSS0_VCLK_CLK

#define TISCI_DEV_GICSS0_VCLK_CLK   0

◆ TISCI_DEV_GPIO0_MMR_CLK

#define TISCI_DEV_GPIO0_MMR_CLK   0

◆ TISCI_DEV_GPIO1_MMR_CLK

#define TISCI_DEV_GPIO1_MMR_CLK   0

◆ TISCI_DEV_MCU_GPIO0_MMR_CLK

#define TISCI_DEV_MCU_GPIO0_MMR_CLK   0

◆ TISCI_DEV_GPMC0_FUNC_CLK

#define TISCI_DEV_GPMC0_FUNC_CLK   0

◆ TISCI_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK

#define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK   1

◆ TISCI_DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK

#define TISCI_DEV_GPMC0_FUNC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK   2

◆ TISCI_DEV_GPMC0_PI_GPMC_RET_CLK

#define TISCI_DEV_GPMC0_PI_GPMC_RET_CLK   3

◆ TISCI_DEV_GPMC0_VBUSM_CLK

#define TISCI_DEV_GPMC0_VBUSM_CLK   4

◆ TISCI_DEV_GPMC0_PO_GPMC_DEV_CLK

#define TISCI_DEV_GPMC0_PO_GPMC_DEV_CLK   5

◆ TISCI_DEV_GTC0_GTC_CLK

#define TISCI_DEV_GTC0_GTC_CLK   0

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   1

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   2

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   3

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   4

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   5

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   6

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   7

◆ TISCI_DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK

#define TISCI_DEV_GTC0_GTC_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   8

◆ TISCI_DEV_GTC0_VBUSP_CLK

#define TISCI_DEV_GTC0_VBUSP_CLK   9

◆ TISCI_DEV_PRU_ICSSG0_CORE_CLK

#define TISCI_DEV_PRU_ICSSG0_CORE_CLK   0

◆ TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK

#define TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK   1

◆ TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK

#define TISCI_DEV_PRU_ICSSG0_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK   2

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK   3

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   4

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   5

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   6

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   7

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   8

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   9

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   10

◆ TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK

#define TISCI_DEV_PRU_ICSSG0_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   11

◆ TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I

#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_RXC_I   12

◆ TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I

#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_I   13

◆ TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I

#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_RXC_I   14

◆ TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I

#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_I   15

◆ TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK

#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK   16

◆ TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK

#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_50_CLK   17

◆ TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK

#define TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_5_CLK   18

◆ TISCI_DEV_PRU_ICSSG0_UCLK_CLK

#define TISCI_DEV_PRU_ICSSG0_UCLK_CLK   19

◆ TISCI_DEV_PRU_ICSSG0_VCLK_CLK

#define TISCI_DEV_PRU_ICSSG0_VCLK_CLK   20

◆ TISCI_DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O

#define TISCI_DEV_PRU_ICSSG0_PR1_MDIO_MDCLK_O   21

◆ TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O

#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII0_TXC_O   22

◆ TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O

#define TISCI_DEV_PRU_ICSSG0_PR1_RGMII1_TXC_O   23

◆ TISCI_DEV_PRU_ICSSG1_CORE_CLK

#define TISCI_DEV_PRU_ICSSG1_CORE_CLK   0

◆ TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK

#define TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK   1

◆ TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK

#define TISCI_DEV_PRU_ICSSG1_CORE_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT9_CLK   2

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK   3

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   4

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   5

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   6

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   7

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   8

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   9

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   10

◆ TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK

#define TISCI_DEV_PRU_ICSSG1_IEP_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   11

◆ TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I

#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_RXC_I   12

◆ TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I

#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_I   13

◆ TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I

#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_RXC_I   14

◆ TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I

#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_I   15

◆ TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK

#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK   16

◆ TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK

#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_50_CLK   17

◆ TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK

#define TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_5_CLK   18

◆ TISCI_DEV_PRU_ICSSG1_UCLK_CLK

#define TISCI_DEV_PRU_ICSSG1_UCLK_CLK   19

◆ TISCI_DEV_PRU_ICSSG1_VCLK_CLK

#define TISCI_DEV_PRU_ICSSG1_VCLK_CLK   20

◆ TISCI_DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O

#define TISCI_DEV_PRU_ICSSG1_PR1_MDIO_MDCLK_O   21

◆ TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O

#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII0_TXC_O   22

◆ TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O

#define TISCI_DEV_PRU_ICSSG1_PR1_RGMII1_TXC_O   23

◆ TISCI_DEV_LED0_LED_CLK

#define TISCI_DEV_LED0_LED_CLK   0

◆ TISCI_DEV_LED0_VBUS_CLK

#define TISCI_DEV_LED0_VBUS_CLK   1

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK   0

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   1

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   2

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   3

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   4

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   5

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   6

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   7

◆ TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK

#define TISCI_DEV_CPTS0_CPTS_RFT_CLK_PARENT_K3_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK   8

◆ TISCI_DEV_CPTS0_VBUSP_CLK

#define TISCI_DEV_CPTS0_VBUSP_CLK   9

◆ TISCI_DEV_CPTS0_CPTS_GENF1

#define TISCI_DEV_CPTS0_CPTS_GENF1   10

◆ TISCI_DEV_CPTS0_CPTS_GENF2

#define TISCI_DEV_CPTS0_CPTS_GENF2   11

◆ TISCI_DEV_CPTS0_CPTS_GENF3

#define TISCI_DEV_CPTS0_CPTS_GENF3   12

◆ TISCI_DEV_CPTS0_CPTS_GENF4

#define TISCI_DEV_CPTS0_CPTS_GENF4   13

◆ TISCI_DEV_DDPA0_DDPA_CLK

#define TISCI_DEV_DDPA0_DDPA_CLK   0

◆ TISCI_DEV_EPWM0_VBUSP_CLK

#define TISCI_DEV_EPWM0_VBUSP_CLK   0

◆ TISCI_DEV_EPWM1_VBUSP_CLK

#define TISCI_DEV_EPWM1_VBUSP_CLK   0

◆ TISCI_DEV_EPWM2_VBUSP_CLK

#define TISCI_DEV_EPWM2_VBUSP_CLK   0

◆ TISCI_DEV_EPWM3_VBUSP_CLK

#define TISCI_DEV_EPWM3_VBUSP_CLK   0

◆ TISCI_DEV_EPWM4_VBUSP_CLK

#define TISCI_DEV_EPWM4_VBUSP_CLK   0

◆ TISCI_DEV_EPWM5_VBUSP_CLK

#define TISCI_DEV_EPWM5_VBUSP_CLK   0

◆ TISCI_DEV_EPWM6_VBUSP_CLK

#define TISCI_DEV_EPWM6_VBUSP_CLK   0

◆ TISCI_DEV_EPWM7_VBUSP_CLK

#define TISCI_DEV_EPWM7_VBUSP_CLK   0

◆ TISCI_DEV_EPWM8_VBUSP_CLK

#define TISCI_DEV_EPWM8_VBUSP_CLK   0

◆ TISCI_DEV_PBIST0_CLK8_CLK

#define TISCI_DEV_PBIST0_CLK8_CLK   0

◆ TISCI_DEV_PBIST1_CLK8_CLK

#define TISCI_DEV_PBIST1_CLK8_CLK   0

◆ TISCI_DEV_PBIST2_CLK8_CLK

#define TISCI_DEV_PBIST2_CLK8_CLK   0

◆ TISCI_DEV_PBIST3_CLK8_CLK

#define TISCI_DEV_PBIST3_CLK8_CLK   0

◆ TISCI_DEV_VTM0_FIX_REF2_CLK

#define TISCI_DEV_VTM0_FIX_REF2_CLK   0

◆ TISCI_DEV_VTM0_FIX_REF_CLK

#define TISCI_DEV_VTM0_FIX_REF_CLK   1

◆ TISCI_DEV_VTM0_VBUSP_CLK

#define TISCI_DEV_VTM0_VBUSP_CLK   2

◆ TISCI_DEV_MCAN0_MCANSS_CCLK_CLK

#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK   0

◆ TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK

#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK   1

◆ TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   2

◆ TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   3

◆ TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   4

◆ TISCI_DEV_MCAN0_MCANSS_HCLK_CLK

#define TISCI_DEV_MCAN0_MCANSS_HCLK_CLK   5

◆ TISCI_DEV_MCAN1_MCANSS_CCLK_CLK

#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK   0

◆ TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK

#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK   1

◆ TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   2

◆ TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   3

◆ TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCAN1_MCANSS_CCLK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   4

◆ TISCI_DEV_MCAN1_MCANSS_HCLK_CLK

#define TISCI_DEV_MCAN1_MCANSS_HCLK_CLK   5

◆ TISCI_DEV_MCU_MCRC64_0_CLK

#define TISCI_DEV_MCU_MCRC64_0_CLK   0

◆ TISCI_DEV_I2C0_CLK

#define TISCI_DEV_I2C0_CLK   0

◆ TISCI_DEV_I2C0_PISCL

#define TISCI_DEV_I2C0_PISCL   1

◆ TISCI_DEV_I2C0_PISYS_CLK

#define TISCI_DEV_I2C0_PISYS_CLK   2

◆ TISCI_DEV_I2C0_PORSCL

#define TISCI_DEV_I2C0_PORSCL   3

◆ TISCI_DEV_I2C1_CLK

#define TISCI_DEV_I2C1_CLK   0

◆ TISCI_DEV_I2C1_PISCL

#define TISCI_DEV_I2C1_PISCL   1

◆ TISCI_DEV_I2C1_PISYS_CLK

#define TISCI_DEV_I2C1_PISYS_CLK   2

◆ TISCI_DEV_I2C1_PORSCL

#define TISCI_DEV_I2C1_PORSCL   3

◆ TISCI_DEV_I2C2_CLK

#define TISCI_DEV_I2C2_CLK   0

◆ TISCI_DEV_I2C2_PISCL

#define TISCI_DEV_I2C2_PISCL   1

◆ TISCI_DEV_I2C2_PISYS_CLK

#define TISCI_DEV_I2C2_PISYS_CLK   2

◆ TISCI_DEV_I2C2_PORSCL

#define TISCI_DEV_I2C2_PORSCL   3

◆ TISCI_DEV_I2C3_CLK

#define TISCI_DEV_I2C3_CLK   0

◆ TISCI_DEV_I2C3_PISCL

#define TISCI_DEV_I2C3_PISCL   1

◆ TISCI_DEV_I2C3_PISYS_CLK

#define TISCI_DEV_I2C3_PISYS_CLK   2

◆ TISCI_DEV_I2C3_PORSCL

#define TISCI_DEV_I2C3_PORSCL   3

◆ TISCI_DEV_MCU_I2C0_CLK

#define TISCI_DEV_MCU_I2C0_CLK   0

◆ TISCI_DEV_MCU_I2C0_PISCL

#define TISCI_DEV_MCU_I2C0_PISCL   1

◆ TISCI_DEV_MCU_I2C0_PISYS_CLK

#define TISCI_DEV_MCU_I2C0_PISYS_CLK   2

◆ TISCI_DEV_MCU_I2C0_PORSCL

#define TISCI_DEV_MCU_I2C0_PORSCL   3

◆ TISCI_DEV_MCU_I2C1_CLK

#define TISCI_DEV_MCU_I2C1_CLK   0

◆ TISCI_DEV_MCU_I2C1_PISCL

#define TISCI_DEV_MCU_I2C1_PISCL   1

◆ TISCI_DEV_MCU_I2C1_PISYS_CLK

#define TISCI_DEV_MCU_I2C1_PISYS_CLK   2

◆ TISCI_DEV_MCU_I2C1_PORSCL

#define TISCI_DEV_MCU_I2C1_PORSCL   3

◆ TISCI_DEV_PCIE0_PCIE_CBA_CLK

#define TISCI_DEV_PCIE0_PCIE_CBA_CLK   0

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK   1

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK   2

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK   3

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT   4

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_CPTS0_RFT_CLK_OUT   5

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT   6

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   7

◆ TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK

#define TISCI_DEV_PCIE0_PCIE_CPTS_RCLK_CLK_PARENT_WIZ16B2M4CT_MAIN_0_IP1_LN0_TXMCLK   8

◆ TISCI_DEV_PCIE0_PCIE_LANE0_REFCLK

#define TISCI_DEV_PCIE0_PCIE_LANE0_REFCLK   10

◆ TISCI_DEV_PCIE0_PCIE_LANE0_RXCLK

#define TISCI_DEV_PCIE0_PCIE_LANE0_RXCLK   11

◆ TISCI_DEV_PCIE0_PCIE_LANE0_RXFCLK

#define TISCI_DEV_PCIE0_PCIE_LANE0_RXFCLK   12

◆ TISCI_DEV_PCIE0_PCIE_LANE0_TXFCLK

#define TISCI_DEV_PCIE0_PCIE_LANE0_TXFCLK   13

◆ TISCI_DEV_PCIE0_PCIE_LANE0_TXMCLK

#define TISCI_DEV_PCIE0_PCIE_LANE0_TXMCLK   14

◆ TISCI_DEV_PCIE0_PCIE_PM_CLK

#define TISCI_DEV_PCIE0_PCIE_PM_CLK   15

◆ TISCI_DEV_PCIE0_PCIE_LANE0_TXCLK

#define TISCI_DEV_PCIE0_PCIE_LANE0_TXCLK   16

◆ TISCI_DEV_R5FSS0_CORE0_CPU_CLK

#define TISCI_DEV_R5FSS0_CORE0_CPU_CLK   0

◆ TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK

#define TISCI_DEV_R5FSS0_CORE0_INTERFACE_CLK   1

◆ TISCI_DEV_R5FSS0_CORE1_CPU_CLK

#define TISCI_DEV_R5FSS0_CORE1_CPU_CLK   0

◆ TISCI_DEV_R5FSS0_CORE1_INTERFACE_CLK

#define TISCI_DEV_R5FSS0_CORE1_INTERFACE_CLK   1

◆ TISCI_DEV_R5FSS1_CORE0_CPU_CLK

#define TISCI_DEV_R5FSS1_CORE0_CPU_CLK   0

◆ TISCI_DEV_R5FSS1_CORE0_INTERFACE_CLK

#define TISCI_DEV_R5FSS1_CORE0_INTERFACE_CLK   1

◆ TISCI_DEV_R5FSS1_CORE1_CPU_CLK

#define TISCI_DEV_R5FSS1_CORE1_CPU_CLK   0

◆ TISCI_DEV_R5FSS1_CORE1_INTERFACE_CLK

#define TISCI_DEV_R5FSS1_CORE1_INTERFACE_CLK   1

◆ TISCI_DEV_RTI0_RTI_CLK

#define TISCI_DEV_RTI0_RTI_CLK   0

◆ TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_RTI0_VBUSP_CLK

#define TISCI_DEV_RTI0_VBUSP_CLK   5

◆ TISCI_DEV_RTI1_RTI_CLK

#define TISCI_DEV_RTI1_RTI_CLK   0

◆ TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_RTI1_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_RTI1_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_RTI1_VBUSP_CLK

#define TISCI_DEV_RTI1_VBUSP_CLK   5

◆ TISCI_DEV_RTI8_RTI_CLK

#define TISCI_DEV_RTI8_RTI_CLK   0

◆ TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_RTI8_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_RTI8_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_RTI8_VBUSP_CLK

#define TISCI_DEV_RTI8_VBUSP_CLK   5

◆ TISCI_DEV_RTI9_RTI_CLK

#define TISCI_DEV_RTI9_RTI_CLK   0

◆ TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_RTI9_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_RTI9_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_RTI9_VBUSP_CLK

#define TISCI_DEV_RTI9_VBUSP_CLK   5

◆ TISCI_DEV_RTI10_RTI_CLK

#define TISCI_DEV_RTI10_RTI_CLK   0

◆ TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_RTI10_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_RTI10_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_RTI10_VBUSP_CLK

#define TISCI_DEV_RTI10_VBUSP_CLK   5

◆ TISCI_DEV_RTI11_RTI_CLK

#define TISCI_DEV_RTI11_RTI_CLK   0

◆ TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_RTI11_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_RTI11_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_RTI11_VBUSP_CLK

#define TISCI_DEV_RTI11_VBUSP_CLK   5

◆ TISCI_DEV_MCU_RTI0_RTI_CLK

#define TISCI_DEV_MCU_RTI0_RTI_CLK   0

◆ TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   1

◆ TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   2

◆ TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT   3

◆ TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_MCU_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   4

◆ TISCI_DEV_MCU_RTI0_VBUSP_CLK

#define TISCI_DEV_MCU_RTI0_VBUSP_CLK   5

◆ TISCI_DEV_SA2_UL0_PKA_IN_CLK

#define TISCI_DEV_SA2_UL0_PKA_IN_CLK   0

◆ TISCI_DEV_SA2_UL0_X1_CLK

#define TISCI_DEV_SA2_UL0_X1_CLK   1

◆ TISCI_DEV_SA2_UL0_X2_CLK

#define TISCI_DEV_SA2_UL0_X2_CLK   2

◆ TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK

#define TISCI_DEV_A53SS0_CORE_0_A53_CORE0_ARM_CLK_CLK   0

◆ TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK

#define TISCI_DEV_A53SS0_CORE_1_A53_CORE1_ARM_CLK_CLK   0

◆ TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK

#define TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK   0

◆ TISCI_DEV_A53SS0_PLL_CTRL_CLK

#define TISCI_DEV_A53SS0_PLL_CTRL_CLK   1

◆ TISCI_DEV_DDR16SS0_DDRSS_DDR_PLL_CLK

#define TISCI_DEV_DDR16SS0_DDRSS_DDR_PLL_CLK   0

◆ TISCI_DEV_DDR16SS0_PLL_CTRL_CLK

#define TISCI_DEV_DDR16SS0_PLL_CTRL_CLK   1

◆ TISCI_DEV_PSC0_CLK

#define TISCI_DEV_PSC0_CLK   0

◆ TISCI_DEV_PSC0_SLOW_CLK

#define TISCI_DEV_PSC0_SLOW_CLK   1

◆ TISCI_DEV_MCU_PSC0_CLK

#define TISCI_DEV_MCU_PSC0_CLK   0

◆ TISCI_DEV_MCU_PSC0_SLOW_CLK

#define TISCI_DEV_MCU_PSC0_SLOW_CLK   1

◆ TISCI_DEV_MCSPI0_CLKSPIREF_CLK

#define TISCI_DEV_MCSPI0_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCSPI0_IO_CLKSPII_CLK

#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT

#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI0_CLK_OUT   2

◆ TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MAIN_0_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCSPI0_VBUSP_CLK

#define TISCI_DEV_MCSPI0_VBUSP_CLK   4

◆ TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI0_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_MCSPI1_CLKSPIREF_CLK

#define TISCI_DEV_MCSPI1_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCSPI1_IO_CLKSPII_CLK

#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT

#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI1_CLK_OUT   2

◆ TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MAIN_1_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCSPI1_VBUSP_CLK

#define TISCI_DEV_MCSPI1_VBUSP_CLK   4

◆ TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI1_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_MCSPI2_CLKSPIREF_CLK

#define TISCI_DEV_MCSPI2_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCSPI2_IO_CLKSPII_CLK

#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT

#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI2_CLK_OUT   2

◆ TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI2_IO_CLKSPII_CLK_PARENT_SPI_MAIN_2_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCSPI2_VBUSP_CLK

#define TISCI_DEV_MCSPI2_VBUSP_CLK   4

◆ TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI2_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_MCSPI3_CLKSPIREF_CLK

#define TISCI_DEV_MCSPI3_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCSPI3_IO_CLKSPII_CLK

#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT

#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI3_CLK_OUT   2

◆ TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI3_IO_CLKSPII_CLK_PARENT_SPI_MAIN_3_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCSPI3_VBUSP_CLK

#define TISCI_DEV_MCSPI3_VBUSP_CLK   4

◆ TISCI_DEV_MCSPI3_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI3_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_MCSPI4_CLKSPIREF_CLK

#define TISCI_DEV_MCSPI4_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCSPI4_IO_CLKSPII_CLK

#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT

#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_BOARD_0_SPI4_CLK_OUT   2

◆ TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI4_IO_CLKSPII_CLK_PARENT_SPI_MAIN_4_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCSPI4_VBUSP_CLK

#define TISCI_DEV_MCSPI4_VBUSP_CLK   4

◆ TISCI_DEV_MCSPI4_IO_CLKSPIO_CLK

#define TISCI_DEV_MCSPI4_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_MCU_MCSPI0_CLKSPIREF_CLK

#define TISCI_DEV_MCU_MCSPI0_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK

#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT

#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI0_CLK_OUT   2

◆ TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK

#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPII_CLK_PARENT_SPI_MCU_0_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCU_MCSPI0_VBUSP_CLK

#define TISCI_DEV_MCU_MCSPI0_VBUSP_CLK   4

◆ TISCI_DEV_MCU_MCSPI0_IO_CLKSPIO_CLK

#define TISCI_DEV_MCU_MCSPI0_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_MCU_MCSPI1_CLKSPIREF_CLK

#define TISCI_DEV_MCU_MCSPI1_CLKSPIREF_CLK   0

◆ TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK

#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK   1

◆ TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT

#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_BOARD_0_MCU_SPI1_CLK_OUT   2

◆ TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK

#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPII_CLK_PARENT_SPI_MCU_1_IO_CLKSPIO_CLK   3

◆ TISCI_DEV_MCU_MCSPI1_VBUSP_CLK

#define TISCI_DEV_MCU_MCSPI1_VBUSP_CLK   4

◆ TISCI_DEV_MCU_MCSPI1_IO_CLKSPIO_CLK

#define TISCI_DEV_MCU_MCSPI1_IO_CLKSPIO_CLK   5

◆ TISCI_DEV_SPINLOCK0_VCLK_CLK

#define TISCI_DEV_SPINLOCK0_VCLK_CLK   0

◆ TISCI_DEV_TIMERMGR0_VCLK_CLK

#define TISCI_DEV_TIMERMGR0_VCLK_CLK   0

◆ TISCI_DEV_UART0_FCLK_CLK

#define TISCI_DEV_UART0_FCLK_CLK   0

◆ TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0

#define TISCI_DEV_UART0_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT0   1

◆ TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART0_VBUSP_CLK

#define TISCI_DEV_UART0_VBUSP_CLK   3

◆ TISCI_DEV_UART1_FCLK_CLK

#define TISCI_DEV_UART1_FCLK_CLK   0

◆ TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1

#define TISCI_DEV_UART1_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT1   1

◆ TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART1_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART1_VBUSP_CLK

#define TISCI_DEV_UART1_VBUSP_CLK   3

◆ TISCI_DEV_UART2_FCLK_CLK

#define TISCI_DEV_UART2_FCLK_CLK   0

◆ TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2

#define TISCI_DEV_UART2_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT2   1

◆ TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART2_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART2_VBUSP_CLK

#define TISCI_DEV_UART2_VBUSP_CLK   3

◆ TISCI_DEV_UART3_FCLK_CLK

#define TISCI_DEV_UART3_FCLK_CLK   0

◆ TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3

#define TISCI_DEV_UART3_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT3   1

◆ TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART3_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART3_VBUSP_CLK

#define TISCI_DEV_UART3_VBUSP_CLK   3

◆ TISCI_DEV_UART4_FCLK_CLK

#define TISCI_DEV_UART4_FCLK_CLK   0

◆ TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4

#define TISCI_DEV_UART4_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT4   1

◆ TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART4_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART4_VBUSP_CLK

#define TISCI_DEV_UART4_VBUSP_CLK   3

◆ TISCI_DEV_UART5_FCLK_CLK

#define TISCI_DEV_UART5_FCLK_CLK   0

◆ TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5

#define TISCI_DEV_UART5_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT5   1

◆ TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART5_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART5_VBUSP_CLK

#define TISCI_DEV_UART5_VBUSP_CLK   3

◆ TISCI_DEV_UART6_FCLK_CLK

#define TISCI_DEV_UART6_FCLK_CLK   0

◆ TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6

#define TISCI_DEV_UART6_FCLK_CLK_PARENT_USART_PROGRAMMABLE_CLOCK_DIVIDER_OUT6   1

◆ TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK

#define TISCI_DEV_UART6_FCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT1_CLK   2

◆ TISCI_DEV_UART6_VBUSP_CLK

#define TISCI_DEV_UART6_VBUSP_CLK   3

◆ TISCI_DEV_MCU_UART0_FCLK_CLK

#define TISCI_DEV_MCU_UART0_FCLK_CLK   0

◆ TISCI_DEV_MCU_UART0_VBUSP_CLK

#define TISCI_DEV_MCU_UART0_VBUSP_CLK   1

◆ TISCI_DEV_MCU_UART1_FCLK_CLK

#define TISCI_DEV_MCU_UART1_FCLK_CLK   0

◆ TISCI_DEV_MCU_UART1_VBUSP_CLK

#define TISCI_DEV_MCU_UART1_VBUSP_CLK   1

◆ TISCI_DEV_USB0_ACLK_CLK

#define TISCI_DEV_USB0_ACLK_CLK   0

◆ TISCI_DEV_USB0_CLK_LPM_CLK

#define TISCI_DEV_USB0_CLK_LPM_CLK   1

◆ TISCI_DEV_USB0_PCLK_CLK

#define TISCI_DEV_USB0_PCLK_CLK   2

◆ TISCI_DEV_USB0_PIPE_REFCLK

#define TISCI_DEV_USB0_PIPE_REFCLK   3

◆ TISCI_DEV_USB0_PIPE_RXCLK

#define TISCI_DEV_USB0_PIPE_RXCLK   4

◆ TISCI_DEV_USB0_PIPE_RXFCLK

#define TISCI_DEV_USB0_PIPE_RXFCLK   5

◆ TISCI_DEV_USB0_PIPE_TXFCLK

#define TISCI_DEV_USB0_PIPE_TXFCLK   6

◆ TISCI_DEV_USB0_PIPE_TXMCLK

#define TISCI_DEV_USB0_PIPE_TXMCLK   7

◆ TISCI_DEV_USB0_USB2_APB_PCLK_CLK

#define TISCI_DEV_USB0_USB2_APB_PCLK_CLK   8

◆ TISCI_DEV_USB0_USB2_REFCLOCK_CLK

#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK   9

◆ TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   10

◆ TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK

#define TISCI_DEV_USB0_USB2_REFCLOCK_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK   11

◆ TISCI_DEV_USB0_PIPE_TXCLK

#define TISCI_DEV_USB0_PIPE_TXCLK   12

◆ TISCI_DEV_SERDES_10G0_CLK

#define TISCI_DEV_SERDES_10G0_CLK   0

◆ TISCI_DEV_SERDES_10G0_CORE_REF_CLK

#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK   1

◆ TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT   2

◆ TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT

#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT   3

◆ TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK

#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT8_CLK   4

◆ TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK

#define TISCI_DEV_SERDES_10G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK   5

◆ TISCI_DEV_SERDES_10G0_IP1_LN0_TXCLK

#define TISCI_DEV_SERDES_10G0_IP1_LN0_TXCLK   6

◆ TISCI_DEV_SERDES_10G0_IP2_LN0_TXCLK

#define TISCI_DEV_SERDES_10G0_IP2_LN0_TXCLK   7

◆ TISCI_DEV_SERDES_10G0_IP1_LN0_REFCLK

#define TISCI_DEV_SERDES_10G0_IP1_LN0_REFCLK   8

◆ TISCI_DEV_SERDES_10G0_IP1_LN0_RXCLK

#define TISCI_DEV_SERDES_10G0_IP1_LN0_RXCLK   9

◆ TISCI_DEV_SERDES_10G0_IP1_LN0_RXFCLK

#define TISCI_DEV_SERDES_10G0_IP1_LN0_RXFCLK   10

◆ TISCI_DEV_SERDES_10G0_IP1_LN0_TXFCLK

#define TISCI_DEV_SERDES_10G0_IP1_LN0_TXFCLK   11

◆ TISCI_DEV_SERDES_10G0_IP1_LN0_TXMCLK

#define TISCI_DEV_SERDES_10G0_IP1_LN0_TXMCLK   12

◆ TISCI_DEV_SERDES_10G0_IP2_LN0_REFCLK

#define TISCI_DEV_SERDES_10G0_IP2_LN0_REFCLK   13

◆ TISCI_DEV_SERDES_10G0_IP2_LN0_RXCLK

#define TISCI_DEV_SERDES_10G0_IP2_LN0_RXCLK   14

◆ TISCI_DEV_SERDES_10G0_IP2_LN0_RXFCLK

#define TISCI_DEV_SERDES_10G0_IP2_LN0_RXFCLK   15

◆ TISCI_DEV_SERDES_10G0_IP2_LN0_TXFCLK

#define TISCI_DEV_SERDES_10G0_IP2_LN0_TXFCLK   16

◆ TISCI_DEV_SERDES_10G0_IP2_LN0_TXMCLK

#define TISCI_DEV_SERDES_10G0_IP2_LN0_TXMCLK   17

◆ TISCI_DEV_BOARD0_FSI_TX0_CLK_IN

#define TISCI_DEV_BOARD0_FSI_TX0_CLK_IN   0

◆ TISCI_DEV_BOARD0_FSI_TX1_CLK_IN

#define TISCI_DEV_BOARD0_FSI_TX1_CLK_IN   1

◆ TISCI_DEV_BOARD0_GPMC0_CLKLB_IN

#define TISCI_DEV_BOARD0_GPMC0_CLKLB_IN   2

◆ TISCI_DEV_BOARD0_GPMC0_CLK_IN

#define TISCI_DEV_BOARD0_GPMC0_CLK_IN   3

◆ TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN

#define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN   4

◆ TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK

#define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT3_CLK   5

◆ TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK

#define TISCI_DEV_BOARD0_GPMC0_FCLK_MUX_IN_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT7_CLK   6

◆ TISCI_DEV_BOARD0_I2C0_SCL_IN

#define TISCI_DEV_BOARD0_I2C0_SCL_IN   7

◆ TISCI_DEV_BOARD0_I2C1_SCL_IN

#define TISCI_DEV_BOARD0_I2C1_SCL_IN   8

◆ TISCI_DEV_BOARD0_I2C2_SCL_IN

#define TISCI_DEV_BOARD0_I2C2_SCL_IN   9

◆ TISCI_DEV_BOARD0_I2C3_SCL_IN

#define TISCI_DEV_BOARD0_I2C3_SCL_IN   10

◆ TISCI_DEV_BOARD0_MCU_I2C0_SCL_IN

#define TISCI_DEV_BOARD0_MCU_I2C0_SCL_IN   11

◆ TISCI_DEV_BOARD0_MCU_I2C1_SCL_IN

#define TISCI_DEV_BOARD0_MCU_I2C1_SCL_IN   12

◆ TISCI_DEV_BOARD0_MCU_OBSCLK0_IN

#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN   13

◆ TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0

#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_MCU_OBSCLK_DIV_OUT0   14

◆ TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_BOARD0_MCU_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT   15

◆ TISCI_DEV_BOARD0_MCU_SPI0_CLK_IN

#define TISCI_DEV_BOARD0_MCU_SPI0_CLK_IN   16

◆ TISCI_DEV_BOARD0_MCU_SPI1_CLK_IN

#define TISCI_DEV_BOARD0_MCU_SPI1_CLK_IN   17

◆ TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN

#define TISCI_DEV_BOARD0_MCU_SYSCLKOUT0_IN   18

◆ TISCI_DEV_BOARD0_MCU_TIMER_IO0_IN

#define TISCI_DEV_BOARD0_MCU_TIMER_IO0_IN   19

◆ TISCI_DEV_BOARD0_MCU_TIMER_IO1_IN

#define TISCI_DEV_BOARD0_MCU_TIMER_IO1_IN   20

◆ TISCI_DEV_BOARD0_MCU_TIMER_IO2_IN

#define TISCI_DEV_BOARD0_MCU_TIMER_IO2_IN   21

◆ TISCI_DEV_BOARD0_MCU_TIMER_IO3_IN

#define TISCI_DEV_BOARD0_MCU_TIMER_IO3_IN   22

◆ TISCI_DEV_BOARD0_MMC1_CLK_IN

#define TISCI_DEV_BOARD0_MMC1_CLK_IN   23

◆ TISCI_DEV_BOARD0_OBSCLK0_IN

#define TISCI_DEV_BOARD0_OBSCLK0_IN   24

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK   25

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT0_CLK   26

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF0   27

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_CPSW_3GUSS_MAIN_0_CPTS_GENF1   28

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF1   29

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF2   30

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_K3_CPTS_MAIN_0_CPTS_GENF3   31

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV1_16FFT_MAIN_14_HSDIVOUT0_CLK   32

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT0_CLK   33

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_8_HSDIVOUT0_CLK   34

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MAIN_12_HSDIVOUT0_CLK   35

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLKOUT   36

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV0_16FFT_MCU_32KHZ_GEN_0_HSDIVOUT0_CLK8   37

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT0_CLK_DUP0   38

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_HFOSC0_CLKOUT   39

◆ TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3

#define TISCI_DEV_BOARD0_OBSCLK0_IN_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3   40

◆ TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN

#define TISCI_DEV_BOARD0_OSPI0_LBCLKO_IN   41

◆ TISCI_DEV_BOARD0_PRG0_MDIO0_MDC_IN

#define TISCI_DEV_BOARD0_PRG0_MDIO0_MDC_IN   42

◆ TISCI_DEV_BOARD0_PRG0_RGMII1_TXC_IN

#define TISCI_DEV_BOARD0_PRG0_RGMII1_TXC_IN   43

◆ TISCI_DEV_BOARD0_PRG0_RGMII2_TXC_IN

#define TISCI_DEV_BOARD0_PRG0_RGMII2_TXC_IN   44

◆ TISCI_DEV_BOARD0_PRG1_MDIO0_MDC_IN

#define TISCI_DEV_BOARD0_PRG1_MDIO0_MDC_IN   45

◆ TISCI_DEV_BOARD0_PRG1_RGMII1_TXC_IN

#define TISCI_DEV_BOARD0_PRG1_RGMII1_TXC_IN   46

◆ TISCI_DEV_BOARD0_PRG1_RGMII2_TXC_IN

#define TISCI_DEV_BOARD0_PRG1_RGMII2_TXC_IN   47

◆ TISCI_DEV_BOARD0_RGMII1_TXC_IN

#define TISCI_DEV_BOARD0_RGMII1_TXC_IN   48

◆ TISCI_DEV_BOARD0_RGMII2_TXC_IN

#define TISCI_DEV_BOARD0_RGMII2_TXC_IN   49

◆ TISCI_DEV_BOARD0_SPI0_CLK_IN

#define TISCI_DEV_BOARD0_SPI0_CLK_IN   50

◆ TISCI_DEV_BOARD0_SPI1_CLK_IN

#define TISCI_DEV_BOARD0_SPI1_CLK_IN   51

◆ TISCI_DEV_BOARD0_SPI2_CLK_IN

#define TISCI_DEV_BOARD0_SPI2_CLK_IN   52

◆ TISCI_DEV_BOARD0_SPI3_CLK_IN

#define TISCI_DEV_BOARD0_SPI3_CLK_IN   53

◆ TISCI_DEV_BOARD0_SPI4_CLK_IN

#define TISCI_DEV_BOARD0_SPI4_CLK_IN   54

◆ TISCI_DEV_BOARD0_SYSCLKOUT0_IN

#define TISCI_DEV_BOARD0_SYSCLKOUT0_IN   55

◆ TISCI_DEV_BOARD0_TIMER_IO0_IN

#define TISCI_DEV_BOARD0_TIMER_IO0_IN   56

◆ TISCI_DEV_BOARD0_TIMER_IO10_IN

#define TISCI_DEV_BOARD0_TIMER_IO10_IN   57

◆ TISCI_DEV_BOARD0_TIMER_IO11_IN

#define TISCI_DEV_BOARD0_TIMER_IO11_IN   58

◆ TISCI_DEV_BOARD0_TIMER_IO1_IN

#define TISCI_DEV_BOARD0_TIMER_IO1_IN   59

◆ TISCI_DEV_BOARD0_TIMER_IO2_IN

#define TISCI_DEV_BOARD0_TIMER_IO2_IN   60

◆ TISCI_DEV_BOARD0_TIMER_IO3_IN

#define TISCI_DEV_BOARD0_TIMER_IO3_IN   61

◆ TISCI_DEV_BOARD0_TIMER_IO4_IN

#define TISCI_DEV_BOARD0_TIMER_IO4_IN   62

◆ TISCI_DEV_BOARD0_TIMER_IO5_IN

#define TISCI_DEV_BOARD0_TIMER_IO5_IN   63

◆ TISCI_DEV_BOARD0_TIMER_IO6_IN

#define TISCI_DEV_BOARD0_TIMER_IO6_IN   64

◆ TISCI_DEV_BOARD0_TIMER_IO7_IN

#define TISCI_DEV_BOARD0_TIMER_IO7_IN   65

◆ TISCI_DEV_BOARD0_TIMER_IO8_IN

#define TISCI_DEV_BOARD0_TIMER_IO8_IN   66

◆ TISCI_DEV_BOARD0_TIMER_IO9_IN

#define TISCI_DEV_BOARD0_TIMER_IO9_IN   67

◆ TISCI_DEV_BOARD0_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_BOARD0_CPTS0_RFT_CLK_OUT   68

◆ TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT

#define TISCI_DEV_BOARD0_CP_GEMAC_CPTS0_RFT_CLK_OUT   69

◆ TISCI_DEV_BOARD0_EXT_REFCLK1_OUT

#define TISCI_DEV_BOARD0_EXT_REFCLK1_OUT   70

◆ TISCI_DEV_BOARD0_FSI_RX0_CLK_OUT

#define TISCI_DEV_BOARD0_FSI_RX0_CLK_OUT   71

◆ TISCI_DEV_BOARD0_FSI_RX1_CLK_OUT

#define TISCI_DEV_BOARD0_FSI_RX1_CLK_OUT   72

◆ TISCI_DEV_BOARD0_FSI_RX2_CLK_OUT

#define TISCI_DEV_BOARD0_FSI_RX2_CLK_OUT   73

◆ TISCI_DEV_BOARD0_FSI_RX3_CLK_OUT

#define TISCI_DEV_BOARD0_FSI_RX3_CLK_OUT   74

◆ TISCI_DEV_BOARD0_FSI_RX4_CLK_OUT

#define TISCI_DEV_BOARD0_FSI_RX4_CLK_OUT   75

◆ TISCI_DEV_BOARD0_FSI_RX5_CLK_OUT

#define TISCI_DEV_BOARD0_FSI_RX5_CLK_OUT   76

◆ TISCI_DEV_BOARD0_GPMC0_CLKLB_OUT

#define TISCI_DEV_BOARD0_GPMC0_CLKLB_OUT   77

◆ TISCI_DEV_BOARD0_I2C0_SCL_OUT

#define TISCI_DEV_BOARD0_I2C0_SCL_OUT   78

◆ TISCI_DEV_BOARD0_I2C1_SCL_OUT

#define TISCI_DEV_BOARD0_I2C1_SCL_OUT   79

◆ TISCI_DEV_BOARD0_I2C2_SCL_OUT

#define TISCI_DEV_BOARD0_I2C2_SCL_OUT   80

◆ TISCI_DEV_BOARD0_I2C3_SCL_OUT

#define TISCI_DEV_BOARD0_I2C3_SCL_OUT   81

◆ TISCI_DEV_BOARD0_LED_CLK_OUT

#define TISCI_DEV_BOARD0_LED_CLK_OUT   82

◆ TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT

#define TISCI_DEV_BOARD0_MCU_EXT_REFCLK0_OUT   83

◆ TISCI_DEV_BOARD0_MCU_I2C0_SCL_OUT

#define TISCI_DEV_BOARD0_MCU_I2C0_SCL_OUT   84

◆ TISCI_DEV_BOARD0_MCU_I2C1_SCL_OUT

#define TISCI_DEV_BOARD0_MCU_I2C1_SCL_OUT   85

◆ TISCI_DEV_BOARD0_MCU_SPI0_CLK_OUT

#define TISCI_DEV_BOARD0_MCU_SPI0_CLK_OUT   86

◆ TISCI_DEV_BOARD0_MCU_SPI1_CLK_OUT

#define TISCI_DEV_BOARD0_MCU_SPI1_CLK_OUT   87

◆ TISCI_DEV_BOARD0_MMC1_CLKLB_OUT

#define TISCI_DEV_BOARD0_MMC1_CLKLB_OUT   88

◆ TISCI_DEV_BOARD0_OSPI0_DQS_OUT

#define TISCI_DEV_BOARD0_OSPI0_DQS_OUT   89

◆ TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT

#define TISCI_DEV_BOARD0_OSPI0_LBCLKO_OUT   90

◆ TISCI_DEV_BOARD0_PRG0_RGMII1_RXC_OUT

#define TISCI_DEV_BOARD0_PRG0_RGMII1_RXC_OUT   91

◆ TISCI_DEV_BOARD0_PRG0_RGMII1_TXC_OUT

#define TISCI_DEV_BOARD0_PRG0_RGMII1_TXC_OUT   92

◆ TISCI_DEV_BOARD0_PRG0_RGMII2_RXC_OUT

#define TISCI_DEV_BOARD0_PRG0_RGMII2_RXC_OUT   93

◆ TISCI_DEV_BOARD0_PRG0_RGMII2_TXC_OUT

#define TISCI_DEV_BOARD0_PRG0_RGMII2_TXC_OUT   94

◆ TISCI_DEV_BOARD0_PRG1_RGMII1_RXC_OUT

#define TISCI_DEV_BOARD0_PRG1_RGMII1_RXC_OUT   95

◆ TISCI_DEV_BOARD0_PRG1_RGMII1_TXC_OUT

#define TISCI_DEV_BOARD0_PRG1_RGMII1_TXC_OUT   96

◆ TISCI_DEV_BOARD0_PRG1_RGMII2_RXC_OUT

#define TISCI_DEV_BOARD0_PRG1_RGMII2_RXC_OUT   97

◆ TISCI_DEV_BOARD0_PRG1_RGMII2_TXC_OUT

#define TISCI_DEV_BOARD0_PRG1_RGMII2_TXC_OUT   98

◆ TISCI_DEV_BOARD0_RGMII1_RXC_OUT

#define TISCI_DEV_BOARD0_RGMII1_RXC_OUT   99

◆ TISCI_DEV_BOARD0_RGMII1_TXC_OUT

#define TISCI_DEV_BOARD0_RGMII1_TXC_OUT   100

◆ TISCI_DEV_BOARD0_RGMII2_RXC_OUT

#define TISCI_DEV_BOARD0_RGMII2_RXC_OUT   101

◆ TISCI_DEV_BOARD0_RGMII2_TXC_OUT

#define TISCI_DEV_BOARD0_RGMII2_TXC_OUT   102

◆ TISCI_DEV_BOARD0_RMII_REF_CLK_OUT

#define TISCI_DEV_BOARD0_RMII_REF_CLK_OUT   103

◆ TISCI_DEV_BOARD0_SPI0_CLK_OUT

#define TISCI_DEV_BOARD0_SPI0_CLK_OUT   104

◆ TISCI_DEV_BOARD0_SPI1_CLK_OUT

#define TISCI_DEV_BOARD0_SPI1_CLK_OUT   105

◆ TISCI_DEV_BOARD0_SPI2_CLK_OUT

#define TISCI_DEV_BOARD0_SPI2_CLK_OUT   106

◆ TISCI_DEV_BOARD0_SPI3_CLK_OUT

#define TISCI_DEV_BOARD0_SPI3_CLK_OUT   107

◆ TISCI_DEV_BOARD0_SPI4_CLK_OUT

#define TISCI_DEV_BOARD0_SPI4_CLK_OUT   108

◆ TISCI_DEV_BOARD0_TCK_OUT

#define TISCI_DEV_BOARD0_TCK_OUT   109

◆ TISCI_DEV_BOARD0_CLKOUT0_IN

#define TISCI_DEV_BOARD0_CLKOUT0_IN   123

◆ TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK5

#define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK5   124

◆ TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK10

#define TISCI_DEV_BOARD0_CLKOUT0_IN_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK10   125