sdl_ecc_soc.h File Reference

Introduction

Header file contains MemEntries, RamIdTables, aggrTables and aggrBaseAddressTable.

declarations for SDL ECC interface.

Go to the source code of this file.

Macros
#define	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES   (24U)
#define	SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (9U)
#define	SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (27U)
#define	SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (8U)
#define	SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (3U)
#define	SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (0U)
#define	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (12U)
#define	SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES   (1U)
#define	SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES   (2U)
#define	SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES   (29U)
#define	SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES   (3U)
#define	SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES   (4U)
#define	SDL_ECC_Base_Address_TOTAL_ENTRIES   (40U)

Variables
static const SDL_MemConfig_t	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_MemEntries [SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_MemEntries [SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_MemEntries [SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_MemEntries [SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_MemEntries [SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_DMASS0_DMSS_AM64_ECCAGGR_MemEntries [SDL_DMASS0_DMSS_AM64_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_MemEntries [SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_MemEntries [SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_MemEntries [SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_MemEntries [SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_MemEntries [SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_MemEntries [SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_groupEntries [SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_groupEntries [SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_groupEntries [SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_groupEntries [SDL_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_MemEntries [SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_MemEntries [SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_MemEntries [SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_DMSC0_DMSC_LITE_MemEntries [SDL_DMSC0_DMSC_LITE_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_MemEntries [SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_ECC_AGGR1_MemEntries [SDL_ECC_AGGR1_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_groupEntries [SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_IK3VTM_N16FFC_MAIN_0_VBUSP_P2P_BRIDGE_IK3VTM_N16FFC_MAIN_0_VBUSP_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_ECC_AGGR1_IAM64_MAIN_INFRA_CBASS_CBASS_MAIN_0_AM64_MAIN_INFRA_CBASS_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_groupEntries [SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_groupEntries [SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_P2P_BRIDGE_IAM64_MCU_CBASS_CBASS_MCU_0_CBASS_DMSC_SLV_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_groupEntries [SDL_ECC_AGGR1_IAM64_MAIN_FW_CBASS_MAIN_0_AM64_MAIN_FW_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_groupEntries [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_MemEntries [SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_MemEntries [SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_MemEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_RAM_IDS_TOTAL_ENTRIES]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IIRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IDRAM_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_RAT_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUSP_S_P2P_BRIDGE_VBUSP_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_BLAZAR_SCR_SCR_BLAZAR_CBASS_BLAZAR_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_SCR_VBUS_CLK_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_I_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_IA2V_D_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_SYS_GASKET_EDC_CTRL_0_MAX_NUM_CHECKERS]
static const SDL_GrpChkConfig_t	SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_groupEntries [SDL_MCU_M4FSS0_BLAZAR_ECC_BLAZAR_ECC_EDC_CTRL_MAX_NUM_CHECKERS]
static const SDL_MemConfig_t	SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_MemEntries [SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_MemEntries [SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_MemEntries [SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_MemEntries [SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_ECC_AGGR0_MemEntries [SDL_ECC_AGGR0_RAM_IDS_TOTAL_ENTRIES]
static const SDL_MemConfig_t	SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_MemEntries [SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RAM_IDS_TOTAL_ENTRIES]
static const SDL_RAMIdEntry_t	SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RamIdTable [SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_CORE0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_RamIdTable [SDL_COMPUTE_CLUSTER0_SAM64_A53_256KB_WRAP_A53_DUAL_WRAP_CBA_WRAP_A53_DUAL_WRAP_CBA_COREPAC_ECC_AGGR_COREPAC_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSG1_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_RamIdTable [SDL_PRU_ICSSG0_ICSS_G_16FF_CORE_BORG_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DMASS0_DMSS_AM64_ECCAGGR_RamIdTable [SDL_DMASS0_DMSS_AM64_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K2_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RamIdTable [SDL_FSS0_FSS_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_RamIdTable [SDL_CPSW0_CPSW_3GUSS_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_RamIdTable [SDL_ADC0_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_RXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD1_EMMCSD4SS_ECC_AGGR_TXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_RamIdTable [SDL_GICSS0_GIC500SS_1_2_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_RamIdTable [SDL_PCIE0_PCIE_G2X1_64_CORE_AXI_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_RamIdTable [SDL_PCIE0_PCIE_G2X1_64_CORE_CORE_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_VTM0_K3VTM_N16FFC_ECCAGGR_RamIdTable [SDL_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_RamIdTable [SDL_SA2_UL0_SA2_UL_SA2_UL_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_RamIdTable [SDL_PDMA1_PDMA_AM64_MAIN1_ECCAGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_RamIdTable [SDL_USB0_USB3P0SS64_16FFC_USB3P0SS64_CORE_A_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_DMSC0_DMSC_LITE_RamIdTable [SDL_DMSC0_DMSC_LITE_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K0_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K3_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K5_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K4_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K7_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_RamIdTable [SDL_MSRAM_256K6_MSRAM32KX64E_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ECC_AGGR1_RamIdTable [SDL_ECC_AGGR1_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable [SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_RamIdTable [SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_TXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_RamIdTable [SDL_MMCSD0_EMMC8SS_16FFC_ECC_AGGR_RXMEM_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_MCU_M4FSS0_BLAZAR_ECC_RamIdTable [SDL_MCU_M4FSS0_BLAZAR_ECC_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_RamIdTable [SDL_R5FSS1_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_RamIdTable [SDL_R5FSS1_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_RamIdTable [SDL_R5FSS0_PULSAR_LITE_CPU0_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_RamIdTable [SDL_R5FSS0_PULSAR_LITE_CPU1_ECC_AGGR_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_ECC_AGGR0_RamIdTable [SDL_ECC_AGGR0_NUM_RAMS]
static const SDL_RAMIdEntry_t	SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_RamIdTable [SDL_PDMA0_PDMA_AM64_MAIN0_ECCAGGR_NUM_RAMS]
SDL_ecc_aggrRegs *	SDL_ECC_aggrTransBaseAddressTable [SDL_ECC_MEMTYPE_MAX]