AM64x MCU+ SDK  08.02.00
tisci_hosts.h
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1 /*
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55 #ifndef TISCI_HOSTS_H
56 #define TISCI_HOSTS_H
57 
59 #define TISCI_HOST_ID_DMSC (0U)
60 
61 #define TISCI_HOST_ID_MAIN_0_R5_0 (35U)
62 
63 #define TISCI_HOST_ID_MAIN_0_R5_1 (36U)
64 
65 #define TISCI_HOST_ID_MAIN_0_R5_2 (37U)
66 
67 #define TISCI_HOST_ID_MAIN_0_R5_3 (38U)
68 
69 #define TISCI_HOST_ID_A53_0 (10U)
70 
71 #define TISCI_HOST_ID_A53_1 (11U)
72 
73 #define TISCI_HOST_ID_A53_2 (12U)
74 
75 #define TISCI_HOST_ID_A53_3 (13U)
76 
77 #define TISCI_HOST_ID_M4_0 (30U)
78 
79 #define TISCI_HOST_ID_MAIN_1_R5_0 (40U)
80 
81 #define TISCI_HOST_ID_MAIN_1_R5_1 (41U)
82 
83 #define TISCI_HOST_ID_MAIN_1_R5_2 (42U)
84 
85 #define TISCI_HOST_ID_MAIN_1_R5_3 (43U)
86 
87 #define TISCI_HOST_ID_ICSSG_0 (50U)
88 
93 #define TISCI_HOST_ID_ALL (128U)
94 
96 #define TISCI_HOST_ID_CNT (15U)
97 
98 #endif /* TISCI_HOSTS_H */
99