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AM64x MCU+ SDK
08.02.00
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AM64x MCU+ SDK
08.02.00
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Go to the source code of this file.
| #define PN_IOD |
| #define NO_PPM 8 |
| #define NO_CPM 8 |
| #define NO_PM 8 |
| #define NO_AR 8 |
| #define YELLOW_SAFETY_MARGIN 0x0280 |
| #define DCP_IDENTREQ_FRAMEID 0xfefe |
| #define DCP_NAME_CMP_NO_OF_CHAR 8 |
| #define DCP_NAME_FRAME_PTR_OFFSET 0x8 |
| #define DCP_NAME_SLAVE_PTR_OFFSET 0x28 |
| #define RTC_3125_CLK_CONST 0x7A12 |
| #define MAX_BRIDGE_DELAY 3020 |
| #define RTC3_PPM_FIFO_PUSH_MARGIN 6720 |
| #define PN_CRITICAL_DHT_REG R29.b0 |
| #define PN_CRITICAL_DHT_FLAG t0 |
| #define RTC_NOTIFY_DHT_EXPIRE_OFFSET 0x10 |
| #define RTC_PPM_INDEX_L1_OFFSET RTC_NOTIFY_DHT_EXPIRE_OFFSET +8 |
| #define RTC_PPM_INDEX_L2_OFFSET RTC_PPM_INDEX_L1_OFFSET + 4 |
| #define RTC_LIST_INDEX_OFFSET RTC_PPM_INDEX_L2_OFFSET + 4 |
| #define RTC_RED_PORT_IDX 0 |
| #define RTC_GREEN_IDX 1 |
| #define RTC_GREEN_PORT_IDX 2 |
| #define RTC_GREEN_END_IDX 3 |
| #define CPM 0 |
| #define PPM 1 |
| #define RTC_CPM_ACTIVE_OFFSET RTC_LIST_INDEX_OFFSET + 2 |
| #define RTC_PPM_OK 1 |
| #define RTC_PPM_ERROR 0 |
| #define RTC_CPM_RUN 1 |
| #define RTC_CPM_FAILURE 0 |
| #define RTC_CPM_STATUS_OFFSET RTC_CPM_ACTIVE_OFFSET + 1 |
| #define RTC_PPM_STATUS_OFFSET RTC_CPM_STATUS_OFFSET + 2 |
| #define RTC_EXECUTE_DHT_CODE RTC_PPM_STATUS_OFFSET + 2 |
| #define RTC_PPM_SEND_STATUS_OFFSET RTC_EXECUTE_DHT_CODE + 1 |
| #define RTC_CPM_BUFFER_LOCK_OFFSET 0x30 |
| #define RTC_MRP_FDB_FLUSH_OFFSET RTC_CPM_BUFFER_LOCK_OFFSET + 9 |
| #define PRU0_PHASE_EVENT_OFFSET RTC_MRP_FDB_FLUSH_OFFSET + 1 |
| #define PRU1_PHASE_EVENT_OFFSET PRU0_PHASE_EVENT_OFFSET + 1 |
| #define RTC_PHASE_COUNTER_OFFSET PRU1_PHASE_EVENT_OFFSET + 3 |
| #define RTC_SEND_LIST_P1_OFFSET RTC_PHASE_COUNTER_OFFSET + 2 |
| #define RTC_SEND_LIST_P2_OFFSET RTC_SEND_LIST_P1_OFFSET + 8 |
| #define RTC_SCF_OFFSET RTC_SEND_LIST_P2_OFFSET + 8 |
| #define RTC_CYCLE_COUNTER_OFFSET RTC_SCF_OFFSET + 2 |
| #define RTC_BASE_CLK_OFFSET RTC_CYCLE_COUNTER_OFFSET + 2 |
| #define PTCP_ABS_COUNTER_OFFSET RTC_BASE_CLK_OFFSET + 4 |
| #define RTC3_SOF_RedFrameID_OFFSET 0x5c |
| #define RTC3_EOF_RedFrameID_OFFSET RTC3_SOF_RedFrameID_OFFSET + 2 |
| #define RTC_DEVICE_SYNC_STATUS_OFFSET RTC3_EOF_RedFrameID_OFFSET + 2 |
| #define RTC_YELLOW_PERIOD_CONFIGURED_OFFSET RTC_DEVICE_SYNC_STATUS_OFFSET + 1 |
| #define PORT1_STATUS_OFFSET RTC_YELLOW_PERIOD_CONFIGURED_OFFSET + 1 |
| #define PORT2_STATUS_OFFSET PORT1_STATUS_OFFSET + 1 |
| #define MAXLINE_RXDELAY_P1_OFFSET PORT2_STATUS_OFFSET + 1 |
| #define MAXLINE_RXDELAY_P2_OFFSET MAXLINE_RXDELAY_P1_OFFSET + 4 |
| #define PRU0_ACTIVE_LIST_INDEX_OFFSET MAXLINE_RXDELAY_P2_OFFSET + 4 |
| #define PRU1_ACTIVE_LIST_INDEX_OFFSET PRU0_ACTIVE_LIST_INDEX_OFFSET + 1 |
| #define RTC_SCH_EXECUTED_HALF_PRU0_OFFSET PRU1_ACTIVE_LIST_INDEX_OFFSET + 1 |
| #define RTC_SCH_EXECUTED_HALF_PRU1_OFFSET RTC_SCH_EXECUTED_HALF_PRU0_OFFSET + 2 |
| #define MRP_PORT1_STATE_OFFSET 0x72 |
| #define MRP_PORT2_STATE_OFFSET MRP_PORT1_STATE_OFFSET + 1 |
| #define RTC_YELLOW_PRD_START_TIME_OFFSET MRP_PORT2_STATE_OFFSET + 1 |
| #define RTC_YELLOW_SAFETY_MARGIN_PRD_START_TIME_OFFSET RTC_YELLOW_PRD_START_TIME_OFFSET + 4 |
| #define RTC_BASE_CLK_CHANGED_OFFSET RTC_YELLOW_SAFETY_MARGIN_PRD_START_TIME_OFFSET + 4 |
| #define RTC_SEND_EXECUTED_HALF_PRU0_OFFSET RTC_BASE_CLK_CHANGED_OFFSET + 2 |
| #define RTC_SEND_EXECUTED_HALF_PRU1_OFFSET RTC_SEND_EXECUTED_HALF_PRU0_OFFSET + 1 |
| #define RTC_GREEN_BEGIN_P1_1_RX_OFFSET 0x80 |
| #define RTC_GREEN_BEGIN_P1_1_TX_OFFSET RTC_GREEN_BEGIN_P1_1_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_2_RX_OFFSET RTC_GREEN_BEGIN_P1_1_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_2_TX_OFFSET RTC_GREEN_BEGIN_P1_2_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_3_RX_OFFSET RTC_GREEN_BEGIN_P1_2_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_3_TX_OFFSET RTC_GREEN_BEGIN_P1_3_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_4_RX_OFFSET RTC_GREEN_BEGIN_P1_3_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_4_TX_OFFSET RTC_GREEN_BEGIN_P1_4_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_5_RX_OFFSET RTC_GREEN_BEGIN_P1_4_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P1_5_TX_OFFSET RTC_GREEN_BEGIN_P1_5_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_1_RX_OFFSET 0xA8 |
| #define RTC_GREEN_BEGIN_P2_1_TX_OFFSET RTC_GREEN_BEGIN_P2_1_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_2_RX_OFFSET RTC_GREEN_BEGIN_P2_1_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_2_TX_OFFSET RTC_GREEN_BEGIN_P2_2_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_3_RX_OFFSET RTC_GREEN_BEGIN_P2_2_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_3_TX_OFFSET RTC_GREEN_BEGIN_P2_3_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_4_RX_OFFSET RTC_GREEN_BEGIN_P2_3_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_4_TX_OFFSET RTC_GREEN_BEGIN_P2_4_RX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_5_RX_OFFSET RTC_GREEN_BEGIN_P2_4_TX_OFFSET + 4 |
| #define RTC_GREEN_BEGIN_P2_5_TX_OFFSET RTC_GREEN_BEGIN_P2_5_RX_OFFSET + 4 |
| #define RTC_PAHSE_MAPPING_OFFSET 0xD0 |
| #define PN_DCPF_NAME_OFFSET RTC_PAHSE_MAPPING_OFFSET + 64 |
| #define PN_DCPF_NAME_LENGTH_OFFSET PN_DCPF_NAME_OFFSET + 8 |
| #define CPM_PREV_CYCLE_COUNTER_OFFSET PN_DCPF_NAME_LENGTH_OFFSET + 4 |
| #define RTC_CPM_DHT_OFFSET CPM_PREV_CYCLE_COUNTER_OFFSET + 16 |
| #define RTC_DHT_TIMEOUT_OFFSET RTC_CPM_DHT_OFFSET + 16 |
| #define RTC_AR_GROUP_PPM_OFFSET RTC_DHT_TIMEOUT_OFFSET + 16 |
| #define RTC_CPM_AR_GROUP_OFFSET RTC_AR_GROUP_PPM_OFFSET + 8 |
| #define RTC_NOTIFY_DHT_EVENT_OFFSET RTC_CPM_AR_GROUP_OFFSET + 8 |
| #define RTC_NOTIFY_LIST_TOGGLE_EVENT_OFFSET RTC_NOTIFY_DHT_EVENT_OFFSET + 10 |
| #define RTC_NOTIFY_DHT_EXPIRE 0x01 |
| #define RTC_NOTIFY_CPM_CRC 0x02 |
| #define RTC_NOTIFY_CPM_SEQ 0x03 |
| #define RTC_NOTIFY_CPM_STAT 0x04 |
| #define RTC_NOTIFY_CPM_LIST_CHANGE 0x05 |
| #define RTC_NOTIFY_PPM_LIST_CHANGE 0x06 |
| #define RTC_NOTIFY_ALL_LIST_CHANGE 0x0B |
| #define RTC_PPM_ACTIVE_OFFSET 0x160 |
| #define RTC_PPM_ACTIVE_SHADOW_OFFSET RTC_PPM_ACTIVE_OFFSET + 8 |
| #define RTC_CPM_BUFFER_ADDRESSES_OFFSET RTC_PPM_ACTIVE_SHADOW_OFFSET + 8 |
| #define ISOM_TIO_TIMEVAL1 0x190 |
| #define ISOM_TIO_DURATION1 ISOM_TIO_TIMEVAL1 + 4 |
| #define ISOM_TIO_TYPE1 ISOM_TIO_DURATION1 + 4 |
| #define ISOM_TIO_ENABLE_OFFSET ISOM_TIO_TYPE1 + 1 |
| #define ISOM_TIO_TIMEVAL2 ISOM_TIO_TYPE1 + 4 |
| #define ISOM_TIO_DURATION2 ISOM_TIO_TIMEVAL2 + 4 |
| #define ISOM_TIO_TYPE2 ISOM_TIO_DURATION2 + 4 |
| #define RTC_IRT_YELLOW_TIME_OFFSET 0x01D0 |
| #define RTC_AR_GROUP_PPM_SHADOW_OFFSET 0x01D4 |
| #define RTC_CPM_BC_EVENT_OFFSET 0x01DC |
| #define COMPENSATION_OFFSET 0x01E4 |
| #define MAXBRIDGE_DELAY_OFFSET 0x01E8 |
| #define EOF_RTC_CONFIG 0x0200 |
| #define RTC_DESC_SIZE 16 |
| #define RTC_CPM_LIST_SIZE RTC_DESC_SIZE * NO_CPM |
| #define RTC_PPM_LIST_SIZE RTC_DESC_SIZE * NO_PPM |
| #define RTC_CPM_IDX0_OFFSET 0x200 |
| #define RTC_PPM_IDX0_OFFSET RTC_CPM_IDX0_OFFSET + RTC_DESC_SIZE * NO_CPM |
| #define RTC_PPM_IDX1_OFFSET RTC_PPM_IDX0_OFFSET + RTC_DESC_SIZE * NO_PPM |
| #define EOF_PPM_LIST_OFFSET RTC_PPM_IDX1_OFFSET + RTC_DESC_SIZE * NO_PPM |
| #define NO_ROWS 50 |
| #define SIZE_OF_ROW 4 |
| #define BLOCKING_STATIC_MAC_TABLE_RCV EOF_PPM_LIST_OFFSET |
| #define BLOCKING_STATIC_MAC_TABLE_FWD BLOCKING_STATIC_MAC_TABLE_RCV + NO_ROWS * SIZE_OF_ROW |
| #define DCP_IDENT_REQ_OFFSET 0x0600 |
| #define PPM_IO_DATA_SIZE 1440 |
| #define PPM_ETH_HEADER 12+4+2+2 |
| #define PPM_TRAILER 2+1+1 |
| #define PPM_BUFFER_OFFSET0 0x0D00 |
| #define PPM_BUFFER_OFFSET1 0x10 |
| #define RTC3_SF_FSO_PRU0_OFFSET 0xBC00 |
| #define RTC3_SF_LENGTH_PRU0_OFFSET RTC3_SF_FSO_PRU0_OFFSET + 4 |
| #define RTC3_SF_BUFFER_PRU0_OFFSET RTC3_SF_LENGTH_PRU0_OFFSET + 4 |
| #define RTC3_SF_FSO_PRU1_OFFSET 0xE814 |
| #define RTC3_SF_LENGTH_PRU1_OFFSET RTC3_SF_FSO_PRU1_OFFSET + 4 |
| #define RTC3_SF_BUFFER_PRU1_OFFSET RTC3_SF_LENGTH_PRU1_OFFSET + 4 |
| #define EOF_PPM_BUFFER_OFFSET 0x1218 |
| #define CPM_IO_DATA_SIZE 1440 |
| #define CPM_ETH_HEADER 12+4+2+2 |
| #define CPM_TRAILER 2+1+1+4 |
| #define EOF_CPM_BUFFER_OFFSET 0xE690 |
| #define CPM_BUFFER_OFFSET 0xC200 |
| #define EOF_48K_BUFFER_OFFSET 0xC200 |
| #define P2_T2_ABS_TS_OFFSET 0x278 |
| #define P1_T2_ABS_TS_OFFSET 0x274 |
| #define SYNC_CYCLE_COUNTER 0x0270 |
| #define SYNC_SF_BUF_OFFSET_P2 PTCP_BASE_ADDR_OFFSET + 528 |
| #define PORT2_DELAY_REQ_FRAME_OFFSET PTCP_BASE_ADDR_OFFSET + 452 |
| #define PORT1_DELAY_REQ_FRAME_OFFSET PTCP_BASE_ADDR_OFFSET + 392 |
| #define PORT2_DELAY_RESP_FRAME_OFFSET PTCP_BASE_ADDR_OFFSET + 324 |
| #define PORT1_DELAY_RESP_FRAME_OFFSET PTCP_BASE_ADDR_OFFSET + 256 |
| #define SYNC_INIT_FLAG_OFFSET PTCP_BASE_ADDR_OFFSET + 254 |
| #define SYNC_MASTER_MAC_OFFSET PTCP_BASE_ADDR_OFFSET + 248 |
| #define SYNC_UUID_OFFSET PTCP_BASE_ADDR_OFFSET + 232 |
| #define SYNC_SF_BUF_OFFSET_P1 PTCP_BASE_ADDR_OFFSET + 136 |
| #define SYNC_SBLOCK_OFFSET PTCP_BASE_ADDR_OFFSET + 104 |
| #define SYNC_W_FUP_CTRL_BYTE_OFFSET PTCP_BASE_ADDR_OFFSET + 100 |
| #define SYNC_CTRL_BYTE_OFFSET PTCP_BASE_ADDR_OFFSET + 96 |
| #define SYNC_RCV_CYCLE_CTR_OFFSET PTCP_BASE_ADDR_OFFSET + 92 |
| #define SYNC_TORG_TIME_OFFSET PTCP_BASE_ADDR_OFFSET + 84 |
| #define SYNC_FUP_DELAY_OFFSET PTCP_BASE_ADDR_OFFSET + 80 |
| #define P2_DELAY_RESP_CTRL_OFFSET PTCP_BASE_ADDR_OFFSET + 78 |
| #define P1_DELAY_RESP_CTRL_OFFSET PTCP_BASE_ADDR_OFFSET + 77 |
| #define SYNC_FWD_ENABLED_OFFSET PTCP_BASE_ADDR_OFFSET + 76 |
| #define SYNC_RX_SOF_OFFSET_P1 PTCP_BASE_ADDR_OFFSET + 72 |
| #define SYNC_RX_SOF_OFFSET PTCP_BASE_ADDR_OFFSET + 68 |
| #define SYNC_INDELAY_PLUS_LD_OFFSET PTCP_BASE_ADDR_OFFSET + 64 |
| #define SYNC_RX_SOF_OFFSET_P2 PTCP_BASE_ADDR_OFFSET + 60 |
| #define SYNC_SEQID_OFFSET PTCP_BASE_ADDR_OFFSET + 56 |
| #define PRU1_HANDSHAKE_OFFSET PTCP_BASE_ADDR_OFFSET + 52 |
| #define P2_SMA_LINE_DELAY_OFFSET PTCP_BASE_ADDR_OFFSET + 48 |
| #define P2_T2_TIME_STAMP_OFFSET PTCP_BASE_ADDR_OFFSET + 44 |
| #define P2_T4_CYCLE_CTR_OFFSET PTCP_BASE_ADDR_OFFSET + 40 |
| #define P2_T4_TIME_STAMP_OFFSET PTCP_BASE_ADDR_OFFSET + 36 |
| #define P2_T1_CYCLE_CTR_OFFSET PTCP_BASE_ADDR_OFFSET + 32 |
| #define P2_T1_TIME_STAMP_OFFSET PTCP_BASE_ADDR_OFFSET + 28 |
| #define PRU0_HANDSHAKE_OFFSET PTCP_BASE_ADDR_OFFSET + 24 |
| #define P1_SMA_LINE_DELAY_OFFSET PTCP_BASE_ADDR_OFFSET + 20 |
| #define P1_T2_TIME_STAMP_OFFSET PTCP_BASE_ADDR_OFFSET + 16 |
| #define P1_T4_CYCLE_CTR_OFFSET PTCP_BASE_ADDR_OFFSET + 12 |
| #define P1_T4_TIME_STAMP_OFFSET PTCP_BASE_ADDR_OFFSET + 8 |
| #define P1_T1_CYCLE_CTR_OFFSET PTCP_BASE_ADDR_OFFSET + 4 |
| #define P1_T1_TIME_STAMP_OFFSET PTCP_BASE_ADDR_OFFSET + 0 |
| #define PTCP_BASE_ADDR_OFFSET 0x0000 |
| #define ECAP_CLR_CONFIG_OFFSET PTCP_L3_OCMC_BASE + 272 |
| #define IEP_CONFIG_ADJ_OFFSET PTCP_L3_OCMC_BASE + 260 |
| #define P2_PTCP_CTRL_OFFSET PTCP_L3_OCMC_BASE + 257 |
| #define P1_PTCP_CTRL_OFFSET PTCP_L3_OCMC_BASE + 256 |
| #define P2_DLY_FUP_PACKET_OFFSET PTCP_L3_OCMC_BASE + 192 |
| #define P1_DLY_FUP_PACKET_OFFSET PTCP_L3_OCMC_BASE + 128 |
| #define P2_DLY_RSP_PACKET_OFFSET PTCP_L3_OCMC_BASE + 64 |
| #define P1_DLY_RSP_PACKET_OFFSET PTCP_L3_OCMC_BASE |
| #define PTCP_L3_OCMC_BASE 0xE700 |
| #define PTCP_PHASE_COUNTER_OFFSET RTC_PHASE_COUNTER_OFFSET |
| #define PTCP_BASE_CLK_OFFSET RTC_BASE_CLK_OFFSET |
| #define PTCP_PM_CYCLE_COUNTER_OFFSET RTC_CYCLE_COUNTER_OFFSET |
| #define PTCP_PM_PHASE_COUNTER_OFFSET RTC_PHASE_COUNTER_OFFSET |
| #define P2_MAC_ADDR 0x1E50 |
| #define P1_MAC_ADDR 0x1E48 |
| #define STATIC_MAC_TABLE_FWD_PORT2 STATIC_MAC_TABLE_RCV_PORT2 + 256 |
| #define STATIC_MAC_TABLE_RCV_PORT2 STATIC_MAC_TABLE_FWD_PORT1 + 256 |
| #define STATIC_MAC_TABLE_FWD_PORT1 STATIC_MAC_TABLE_RCV_PORT1 + 256 |
| #define STATIC_MAC_TABLE_RCV_PORT1 0x2000 |
1.8.20