AM64x MCU+ SDK  08.02.00

Introduction

EtherCAT FWHAL(Firmware and Hardware Abstraction Layer) APIs implement the key interface between EtherCAT Slave Controller Emulation firmware and EtherCAT stack.

Sub Modules

 ESC Firmware Command API
 
 ESC Register/Memory access. Special handling APIs
 
 ESI EEPROM Emulation support
 
 Initialization of stack-firmware interface
 
 Interrupt management APIs for EtherCAT stack
 
 Mutex APIs for EtherCAT stack
 
 PRU Firmware header mapping API
 
 PRU-ICSS DIGIO host side APIs
 
 PRU-ICSS MDIO host side APIs
 
 Spinlock APIs for concurrent Host/Firmware shared memory access
 
 Sync Manager Buffer mode handling
 
 Sync Manager Mailbox mode handling
 
 Sync Manager access and control APIs
 
 Sync Manager properties management
 
 System Time PDI controlled APIs
 
 Timer APIs for EtherCAT stack
 

Files

file  tiescbsp.h
 

Data Structures

struct  bsp_params
 Struct for FWHAL initialization Parameters. More...
 
struct  t_sm_processdata
 Struct for host to PRU-ICSS command interface. More...
 
struct  t_host_interface
 Struct for host to PRU-ICSS command interface Starts at PRU0 DMEM. More...
 
struct  t_register_properties
 Struct for register permission array. More...
 
struct  t_sm_properties
 
struct  t_mdio_params
 Struct for MDIO initialization parameters. More...
 

Typedefs

typedef int32_t(* bsp_eeprom_read_t) (uint8_t *buf, uint32_t len)
 
typedef int32_t(* bsp_eeprom_write_t) (uint8_t *buf, uint32_t len)
 
typedef void(* bsp_init_spinlock_t) (void)
 
typedef uint32_t(* bsp_hwspinlock_lock_t) (int num)
 
typedef void(* bsp_hwspinlock_unlock_t) (int num)
 
typedef void(* bsp_ethphy_init_t) (PRUICSS_Handle pruIcssHandle, uint8_t phy0addr, uint8_t phy1addr, uint8_t enhancedlink_enable)
 
typedef int8_t(* bsp_get_phy_address_t) (uint8_t instance, uint8_t portNumber)
 
typedef void(* bsp_ethercat_stack_isr_function) (void)
 

Macros

#define TIESC_MAX_FRAME_SIZE   (0x7CF)
 TIESC_MAX_FRAME_SIZE Maximum frame size cutoff of 2000 bytes. More...
 
#define ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM   0
 
#define MAX_SYNC_MAN   8
 
#define SIZEOF_SM_REGISTER   8
 
#define TIESC_EEPROM_SIZE   0x800
 
#define MAILBOX_WRITE   0
 
#define MAILBOX_READ   1
 
#define PROCESS_DATA_OUT   2
 
#define PROCESS_DATA_IN   3
 
#define MBX_WRITE_EVENT   ((uint16_t) 0x0100)
 
#define MBX_READ_EVENT   ((uint16_t) 0x0200)
 
#define ESC_ADDR_REV_TYPE   0x000
 
#define ESC_ADDR_BUILD   0x002
 
#define ESC_ADDR_CONFIG_STATION_ALIAS   0x012
 
#define ESC_ADDR_DLSTATUS   0x110
 
#define ESC_ADDR_ALCONTROL   0x120
 
#define ESC_ADDR_ALSTATUS   0x130
 
#define ESC_ADDR_PDI_CONTROL   0x140
 
#define ESC_PDI_CONTROL_ELD_ALL_PORTS_MASK   (1 << 1)
 
#define ESC_ADDR_PDI_CONFIG   0x150
 
#define ESC_ADDR_AL_EVENT_MASK   0x204
 
#define ESC_ADDR_AL_EVENT_REQ   0x220
 
#define ESC_ADDR_SM_WD_STATUS   0x440
 
#define ESC_ADDR_EEPROM_CTRL   0x502
 
#define ESC_ADDR_MI_ECAT_ACCESS   0x516
 
#define ESC_ADDR_MI_PDI_ACCESS   0x517
 
#define ESC_EEPROM_CMD_MASK   0x0700
 
#define ESC_EEPROM_CMD_READ_MASK   0x0100
 
#define ESC_EEPROM_CMD_WRITE_MASK   0x0200
 
#define ESC_EEPROM_CMD_RELOAD_MASK   0x0400
 
#define ESC_EEPROM_ERROR_MASK   0x7800
 
#define ESC_EEPROM_ERROR_CRC   0x0800
 
#define ESC_EEPROM_ERROR_CMD_ACK   0x2000
 
#define ESC_EEPROM_BUSY_MASK   0x8000
 
#define ESC_ADDR_SYNCMAN   0x800
 
#define ESC_ADDR_SM1_STATUS   0x80D
 
#define SM_STATUS_MBX_FULL   0x08
 
#define ESC_ADDR_SM0_STATUS   0x805
 
#define ESC_ADDR_SM0_ACTIVATE   0x806
 
#define ESC_ADDR_SM1_ACTIVATE   0x806+8
 
#define ESC_ADDR_SM2_ACTIVATE   0x806+8*2
 
#define ESC_ADDR_SM3_ACTIVATE   0x806+8*3
 
#define ESC_ADDR_SM4_ACTIVATE   0x806+8*4
 
#define ESC_ADDR_SM5_ACTIVATE   0x806+8*5
 
#define ESC_ADDR_SM6_ACTIVATE   0x806+8*6
 
#define ESC_ADDR_SM7_ACTIVATE   0x806+8*7
 
#define ESC_ADDR_SM0_PDI_CONTROL   0x807
 
#define ESC_ADDR_SM1_PDI_CONTROL   0x807+8
 
#define ESC_ADDR_SM2_PDI_CONTROL   0x807+8*2
 
#define ESC_ADDR_SM3_PDI_CONTROL   0x807+8*3
 
#define ESC_ADDR_SM4_PDI_CONTROL   0x807+8*4
 
#define ESC_ADDR_SM5_PDI_CONTROL   0x807+8*5
 
#define ESC_ADDR_SM6_PDI_CONTROL   0x807+8*6
 
#define ESC_ADDR_SM7_PDI_CONTROL   0x807+8*7
 
#define SM_PDI_CONTROL_SM_DISABLE   1
 
#define ESC_ADDR_SYSTIME   0x910
 
#define ESC_ADDR_SYSTIME_HIGH   0x914
 
#define ESC_ADDR_SYSTIME_OFFSET   0x920
 
#define ESC_ADDR_SYSTIME_DELAY   0x928
 
#define ESC_ADDR_SPEEDCOUNTER_START   0x930
 
#define ESC_ADDR_TIMEDIFF_FILTDEPTH   0x934
 
#define ESC_ADDR_SPEEDDIFF_FILTDEPTH   0x935
 
#define ESC_ADDR_SYNC_PULSE_LENGTH   0x982
 
#define ESC_ADDR_SYNC_STATUS   0x98E
 
#define ESC_ADDR_LATCH0_CONTROL   0x9A8
 
#define ESC_ADDR_LATCH1_CONTROL   0x9A9
 
#define ESC_ADDR_LATCH0_POS_EDGE   0x9B0
 
#define ESC_ADDR_LATCH0_NEG_EDGE   0x9B8
 
#define ESC_ADDR_LATCH1_POS_EDGE   0x9C0
 
#define ESC_ADDR_LATCH1_NEG_EDGE   0x9C8
 
#define ESC_ADDR_TI_PORT0_ACTIVITY   0xE00
 
#define ESC_ADDR_TI_PORT1_ACTIVITY   0xE04
 
#define ESC_ADDR_TI_PORT0_PHYADDR   0xE08
 
#define ESC_ADDR_TI_PORT1_PHYADDR   0xE09
 
#define ESC_ADDR_TI_PDI_ISR_PINSEL   0xE0A
 
#define ESC_ADDR_TI_PHY_LINK_POLARITY   0XE0C
 
#define ESC_ADDR_TI_PORT0_TX_START_DELAY   0xE10
 
#define ESC_ADDR_TI_PORT1_TX_START_DELAY   0xE12
 
#define ESC_ADDR_TI_ESC_RESET   0xE14
 
#define ESC_ADDR_TI_EDMA_LATENCY_ENHANCEMENT   0xE24
 
#define TI_ESC_RST_CMD_U   0x545352
 
#define TI_ESC_RST_CMD_L   0x747372
 
#define ESC_ADDR_MEMORY   0x1000
 
#define CMD_DL_USER_CLEAR_AL_EVENT_HIGH   0x0
 
#define CMD_DL_USER_GET_BUFFER_READ_ADDR   0x1
 
#define CMD_DL_USER_GET_BUFFER_WRITE_ADDR   0x2
 
#define CMD_DL_USER_SET_BUFFER_WRITE_DONE   0x3
 
#define CMD_DL_USER_ACK_MBX_READ   0x4
 CMD_DL_USER_ACK_MBX_READ Mailbox read ACK. More...
 
#define CMD_DL_USER_ACK_MBX_WRITE   0x5
 CMD_DL_USER_ACK_MBX_WRITE Mailbox write ACK. More...
 
#define CMD_DL_USER_EEPROM_CMD_ACK   0x6
 CMD_DL_USER_EEPROM_CMD_ACK User EEPROM ACK. More...
 
#define CMD_DL_USER_READ_SYNC_STATUS   0x7
 CMD_DL_USER_READ_SYNC_STATUS User Read sync status. More...
 
#define SYNC0   0
 
#define SYNC1   1
 
#define CMD_DL_USER_READ_AL_CONTROL   0x8
 CMD_DL_USER_READ_AL_CONTROL User Read AL Control. More...
 
#define CMD_DL_USER_WRITE_AL_STATUS   0x9
 CMD_DL_USER_WRITE_AL_STATUS User Read AL Status. More...
 
#define CMD_DL_USER_READ_PD_WD_STATUS   0xA
 CMD_DL_USER_READ_PD_WD_STATUS User Read PD_WD Status. More...
 
#define CMD_DL_USER_READ_SM_ACTIVATE   0xB
 CMD_DL_USER_READ_SM_ACTIVATE User Read SM Activate. More...
 
#define CMD_DL_USER_WRITE_SM_PDI_CTRL   0xC
 CMD_DL_USER_WRITE_SM_PDI_CTRL User Write SM PDI control. More...
 
#define CMD_DL_USER_READ_LATCH_TIME   0xD
 CMD_DL_USER_READ_LATCH_TIME User Read latch time. More...
 
#define LATCH0_POS_EDGE   0
 
#define LATCH0_NEG_EDGE   1
 
#define LATCH1_POS_EDGE   2
 
#define LATCH1_NEG_EDGE   3
 
#define CMD_DL_USER_READ_SYS_TIME   0xE
 CMD_DL_USER_READ_SYS_TIME User Read sys time. More...
 
#define CMD_DL_USER_CLEAR_AL_EVENT_LOW   0xF
 CMD_DL_USER_CLEAR_AL_EVENT_LOW User clear AL event low. More...
 
#define SWAPWORD
 
#define SWAPDWORD
 
#define ICSS_MDIO_USRPHYSEL_LINKINT_ENABLE   0x40
 
#define ICSS_MDIO_USRPHYSEL_LINKSTAT_MLINK   0x80
 
#define TIESC_PERM_RW   0x0
 
#define TIESC_PERM_WRITE_ONLY   0x1
 
#define TIESC_PERM_READ_ONLY   0x2
 
#define TIESC_PERM_WRITE   TIESC_PERM_WRITE_ONLY
 
#define TIESC_PERM_READ   TIESC_PERM_READ_ONLY
 
#define PDI_PERM_RW   0x0
 
#define PDI_PERM_READ_ONLY   0x1
 
#define PDI_PERM_WRITE   PDI_PERM_RW
 
#define PDI_PERM_READ   PDI_PERM_READ_ONLY
 
#define TIESC_MDIO_CLKDIV   79
 
#define TIESC_MDIO_RX_LINK_DISABLE   0
 
#define TIESC_MDIO_RX_LINK_ENABLE   1
 
#define TIESC_LINK_POL_ACTIVE_LOW   1
 
#define TIESC_LINK_POL_ACTIVE_HIGH   0
 
#define PDI_WD_TRIGGER_RX_SOF   (0 << 4)
 PDI_WD_TRIGGER_RX_SOF Watchdog RX Start of Frame Trigger. More...
 
#define PDI_WD_TRIGGER_LATCH_IN   (1 << 4)
 PDI_WD_TRIGGER_LATCH_IN Watchdog LATCH IN Trigger. More...
 
#define PDI_WD_TRIGGER_SYNC0_OUT   (2 << 4)
 PDI_WD_TRIGGER_SYNC0_OUT Watchdog SYNC0 Trigger. More...
 
#define PDI_WD_TRIGGER_SYNC1_OUT   (3 << 4)
 PDI_WD_TRIGGER_SYNC1_OUT Watchdog SYNC1 Trigger. More...
 
#define TIESC_PORT0_TX_DELAY   0x50
 
#define TIESC_PORT1_TX_DELAY   0x50
 
#define PDI_ISR_EDIO_NUM   7
 
#define USE_ECAT_TIMER
 
#define ENABLE_PDI_TASK
 
#define ENABLE_SYNC_TASK
 
#define ASSERT_DMB()   __asm__(" dmb")
 SUPPORT_CMDACK_POLL_MODE If PDI and SYNC ISR is handled in HWI context (similar to SSC) interrupt mode of CMDACK won't work as they are low priority than SYNC and PDI ISR - use polling instead. More...
 
#define ASSERT_DSB()   __asm__(" dsb")
 
#define ECAT_TIMER_INC_P_MS   1000000
 
#define ESC_SYSTEMTIME_OFFSET_OFFSET   0x0920
 
#define ESC_SPEED_COUNTER_START_OFFSET   0x0930
 
#define ESC_DC_START_TIME_CYCLIC_OFFSET   0x0990
 
#define DRIFTCTRL_TASK_SYNC_ZERO_CROSS_ADJUST   0xE0
 
#define LOCK_PD_BUF_AVAILABLE_FOR_HOST   0
 LOCK_PD_BUF_AVAILABLE_FOR_HOST LOCK available for HOST. More...
 
#define LOCK_PD_BUF_HOST_ACCESS_START   1
 LOCK_PD_BUF_HOST_ACCESS_START Lock available for host access start. More...
 
#define LOCK_PD_BUF_HOST_ACCESS_FINISH   2
 LOCK_PD_BUF_HOST_ACCESS_FINISH Lock available for host access finish. More...
 
#define LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT   (10U)
 LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT Number of times the lock_state of SM is checked for availability in bsp_get_process_data_address function, in case the lock_state is not LOCK_PD_BUF_HOST_ACCESS_START. More...
 

Macro Definition Documentation

◆ TIESC_MAX_FRAME_SIZE

#define TIESC_MAX_FRAME_SIZE   (0x7CF)

TIESC_MAX_FRAME_SIZE Maximum frame size cutoff of 2000 bytes.

◆ ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM

#define ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM   0

◆ MAX_SYNC_MAN

#define MAX_SYNC_MAN   8

◆ SIZEOF_SM_REGISTER

#define SIZEOF_SM_REGISTER   8

◆ TIESC_EEPROM_SIZE

#define TIESC_EEPROM_SIZE   0x800

◆ MAILBOX_WRITE

#define MAILBOX_WRITE   0

◆ MAILBOX_READ

#define MAILBOX_READ   1

◆ PROCESS_DATA_OUT

#define PROCESS_DATA_OUT   2

◆ PROCESS_DATA_IN

#define PROCESS_DATA_IN   3

◆ MBX_WRITE_EVENT

#define MBX_WRITE_EVENT   ((uint16_t) 0x0100)

◆ MBX_READ_EVENT

#define MBX_READ_EVENT   ((uint16_t) 0x0200)

◆ ESC_ADDR_REV_TYPE

#define ESC_ADDR_REV_TYPE   0x000

◆ ESC_ADDR_BUILD

#define ESC_ADDR_BUILD   0x002

◆ ESC_ADDR_CONFIG_STATION_ALIAS

#define ESC_ADDR_CONFIG_STATION_ALIAS   0x012

◆ ESC_ADDR_DLSTATUS

#define ESC_ADDR_DLSTATUS   0x110

◆ ESC_ADDR_ALCONTROL

#define ESC_ADDR_ALCONTROL   0x120

◆ ESC_ADDR_ALSTATUS

#define ESC_ADDR_ALSTATUS   0x130

◆ ESC_ADDR_PDI_CONTROL

#define ESC_ADDR_PDI_CONTROL   0x140

◆ ESC_PDI_CONTROL_ELD_ALL_PORTS_MASK

#define ESC_PDI_CONTROL_ELD_ALL_PORTS_MASK   (1 << 1)

◆ ESC_ADDR_PDI_CONFIG

#define ESC_ADDR_PDI_CONFIG   0x150

◆ ESC_ADDR_AL_EVENT_MASK

#define ESC_ADDR_AL_EVENT_MASK   0x204

◆ ESC_ADDR_AL_EVENT_REQ

#define ESC_ADDR_AL_EVENT_REQ   0x220

◆ ESC_ADDR_SM_WD_STATUS

#define ESC_ADDR_SM_WD_STATUS   0x440

◆ ESC_ADDR_EEPROM_CTRL

#define ESC_ADDR_EEPROM_CTRL   0x502

◆ ESC_ADDR_MI_ECAT_ACCESS

#define ESC_ADDR_MI_ECAT_ACCESS   0x516

◆ ESC_ADDR_MI_PDI_ACCESS

#define ESC_ADDR_MI_PDI_ACCESS   0x517

◆ ESC_EEPROM_CMD_MASK

#define ESC_EEPROM_CMD_MASK   0x0700

◆ ESC_EEPROM_CMD_READ_MASK

#define ESC_EEPROM_CMD_READ_MASK   0x0100

◆ ESC_EEPROM_CMD_WRITE_MASK

#define ESC_EEPROM_CMD_WRITE_MASK   0x0200

◆ ESC_EEPROM_CMD_RELOAD_MASK

#define ESC_EEPROM_CMD_RELOAD_MASK   0x0400

◆ ESC_EEPROM_ERROR_MASK

#define ESC_EEPROM_ERROR_MASK   0x7800

◆ ESC_EEPROM_ERROR_CRC

#define ESC_EEPROM_ERROR_CRC   0x0800

◆ ESC_EEPROM_ERROR_CMD_ACK

#define ESC_EEPROM_ERROR_CMD_ACK   0x2000

◆ ESC_EEPROM_BUSY_MASK

#define ESC_EEPROM_BUSY_MASK   0x8000

◆ ESC_ADDR_SYNCMAN

#define ESC_ADDR_SYNCMAN   0x800

◆ ESC_ADDR_SM1_STATUS

#define ESC_ADDR_SM1_STATUS   0x80D

◆ SM_STATUS_MBX_FULL

#define SM_STATUS_MBX_FULL   0x08

◆ ESC_ADDR_SM0_STATUS

#define ESC_ADDR_SM0_STATUS   0x805

◆ ESC_ADDR_SM0_ACTIVATE

#define ESC_ADDR_SM0_ACTIVATE   0x806

◆ ESC_ADDR_SM1_ACTIVATE

#define ESC_ADDR_SM1_ACTIVATE   0x806+8

◆ ESC_ADDR_SM2_ACTIVATE

#define ESC_ADDR_SM2_ACTIVATE   0x806+8*2

◆ ESC_ADDR_SM3_ACTIVATE

#define ESC_ADDR_SM3_ACTIVATE   0x806+8*3

◆ ESC_ADDR_SM4_ACTIVATE

#define ESC_ADDR_SM4_ACTIVATE   0x806+8*4

◆ ESC_ADDR_SM5_ACTIVATE

#define ESC_ADDR_SM5_ACTIVATE   0x806+8*5

◆ ESC_ADDR_SM6_ACTIVATE

#define ESC_ADDR_SM6_ACTIVATE   0x806+8*6

◆ ESC_ADDR_SM7_ACTIVATE

#define ESC_ADDR_SM7_ACTIVATE   0x806+8*7

◆ ESC_ADDR_SM0_PDI_CONTROL

#define ESC_ADDR_SM0_PDI_CONTROL   0x807

◆ ESC_ADDR_SM1_PDI_CONTROL

#define ESC_ADDR_SM1_PDI_CONTROL   0x807+8

◆ ESC_ADDR_SM2_PDI_CONTROL

#define ESC_ADDR_SM2_PDI_CONTROL   0x807+8*2

◆ ESC_ADDR_SM3_PDI_CONTROL

#define ESC_ADDR_SM3_PDI_CONTROL   0x807+8*3

◆ ESC_ADDR_SM4_PDI_CONTROL

#define ESC_ADDR_SM4_PDI_CONTROL   0x807+8*4

◆ ESC_ADDR_SM5_PDI_CONTROL

#define ESC_ADDR_SM5_PDI_CONTROL   0x807+8*5

◆ ESC_ADDR_SM6_PDI_CONTROL

#define ESC_ADDR_SM6_PDI_CONTROL   0x807+8*6

◆ ESC_ADDR_SM7_PDI_CONTROL

#define ESC_ADDR_SM7_PDI_CONTROL   0x807+8*7

◆ SM_PDI_CONTROL_SM_DISABLE

#define SM_PDI_CONTROL_SM_DISABLE   1

◆ ESC_ADDR_SYSTIME

#define ESC_ADDR_SYSTIME   0x910

◆ ESC_ADDR_SYSTIME_HIGH

#define ESC_ADDR_SYSTIME_HIGH   0x914

◆ ESC_ADDR_SYSTIME_OFFSET

#define ESC_ADDR_SYSTIME_OFFSET   0x920

◆ ESC_ADDR_SYSTIME_DELAY

#define ESC_ADDR_SYSTIME_DELAY   0x928

◆ ESC_ADDR_SPEEDCOUNTER_START

#define ESC_ADDR_SPEEDCOUNTER_START   0x930

◆ ESC_ADDR_TIMEDIFF_FILTDEPTH

#define ESC_ADDR_TIMEDIFF_FILTDEPTH   0x934

◆ ESC_ADDR_SPEEDDIFF_FILTDEPTH

#define ESC_ADDR_SPEEDDIFF_FILTDEPTH   0x935

◆ ESC_ADDR_SYNC_PULSE_LENGTH

#define ESC_ADDR_SYNC_PULSE_LENGTH   0x982

◆ ESC_ADDR_SYNC_STATUS

#define ESC_ADDR_SYNC_STATUS   0x98E

◆ ESC_ADDR_LATCH0_CONTROL

#define ESC_ADDR_LATCH0_CONTROL   0x9A8

◆ ESC_ADDR_LATCH1_CONTROL

#define ESC_ADDR_LATCH1_CONTROL   0x9A9

◆ ESC_ADDR_LATCH0_POS_EDGE

#define ESC_ADDR_LATCH0_POS_EDGE   0x9B0

◆ ESC_ADDR_LATCH0_NEG_EDGE

#define ESC_ADDR_LATCH0_NEG_EDGE   0x9B8

◆ ESC_ADDR_LATCH1_POS_EDGE

#define ESC_ADDR_LATCH1_POS_EDGE   0x9C0

◆ ESC_ADDR_LATCH1_NEG_EDGE

#define ESC_ADDR_LATCH1_NEG_EDGE   0x9C8

◆ ESC_ADDR_TI_PORT0_ACTIVITY

#define ESC_ADDR_TI_PORT0_ACTIVITY   0xE00

◆ ESC_ADDR_TI_PORT1_ACTIVITY

#define ESC_ADDR_TI_PORT1_ACTIVITY   0xE04

◆ ESC_ADDR_TI_PORT0_PHYADDR

#define ESC_ADDR_TI_PORT0_PHYADDR   0xE08

◆ ESC_ADDR_TI_PORT1_PHYADDR

#define ESC_ADDR_TI_PORT1_PHYADDR   0xE09

◆ ESC_ADDR_TI_PDI_ISR_PINSEL

#define ESC_ADDR_TI_PDI_ISR_PINSEL   0xE0A

◆ ESC_ADDR_TI_PHY_LINK_POLARITY

#define ESC_ADDR_TI_PHY_LINK_POLARITY   0XE0C

◆ ESC_ADDR_TI_PORT0_TX_START_DELAY

#define ESC_ADDR_TI_PORT0_TX_START_DELAY   0xE10

◆ ESC_ADDR_TI_PORT1_TX_START_DELAY

#define ESC_ADDR_TI_PORT1_TX_START_DELAY   0xE12

◆ ESC_ADDR_TI_ESC_RESET

#define ESC_ADDR_TI_ESC_RESET   0xE14

◆ ESC_ADDR_TI_EDMA_LATENCY_ENHANCEMENT

#define ESC_ADDR_TI_EDMA_LATENCY_ENHANCEMENT   0xE24

◆ TI_ESC_RST_CMD_U

#define TI_ESC_RST_CMD_U   0x545352

◆ TI_ESC_RST_CMD_L

#define TI_ESC_RST_CMD_L   0x747372

◆ ESC_ADDR_MEMORY

#define ESC_ADDR_MEMORY   0x1000

◆ CMD_DL_USER_CLEAR_AL_EVENT_HIGH

#define CMD_DL_USER_CLEAR_AL_EVENT_HIGH   0x0

◆ CMD_DL_USER_GET_BUFFER_READ_ADDR

#define CMD_DL_USER_GET_BUFFER_READ_ADDR   0x1

◆ CMD_DL_USER_GET_BUFFER_WRITE_ADDR

#define CMD_DL_USER_GET_BUFFER_WRITE_ADDR   0x2

◆ CMD_DL_USER_SET_BUFFER_WRITE_DONE

#define CMD_DL_USER_SET_BUFFER_WRITE_DONE   0x3

◆ CMD_DL_USER_ACK_MBX_READ

#define CMD_DL_USER_ACK_MBX_READ   0x4

CMD_DL_USER_ACK_MBX_READ Mailbox read ACK.

◆ CMD_DL_USER_ACK_MBX_WRITE

#define CMD_DL_USER_ACK_MBX_WRITE   0x5

CMD_DL_USER_ACK_MBX_WRITE Mailbox write ACK.

◆ CMD_DL_USER_EEPROM_CMD_ACK

#define CMD_DL_USER_EEPROM_CMD_ACK   0x6

CMD_DL_USER_EEPROM_CMD_ACK User EEPROM ACK.

◆ CMD_DL_USER_READ_SYNC_STATUS

#define CMD_DL_USER_READ_SYNC_STATUS   0x7

CMD_DL_USER_READ_SYNC_STATUS User Read sync status.

◆ SYNC0

#define SYNC0   0

◆ SYNC1

#define SYNC1   1

◆ CMD_DL_USER_READ_AL_CONTROL

#define CMD_DL_USER_READ_AL_CONTROL   0x8

CMD_DL_USER_READ_AL_CONTROL User Read AL Control.

◆ CMD_DL_USER_WRITE_AL_STATUS

#define CMD_DL_USER_WRITE_AL_STATUS   0x9

CMD_DL_USER_WRITE_AL_STATUS User Read AL Status.

◆ CMD_DL_USER_READ_PD_WD_STATUS

#define CMD_DL_USER_READ_PD_WD_STATUS   0xA

CMD_DL_USER_READ_PD_WD_STATUS User Read PD_WD Status.

◆ CMD_DL_USER_READ_SM_ACTIVATE

#define CMD_DL_USER_READ_SM_ACTIVATE   0xB

CMD_DL_USER_READ_SM_ACTIVATE User Read SM Activate.

◆ CMD_DL_USER_WRITE_SM_PDI_CTRL

#define CMD_DL_USER_WRITE_SM_PDI_CTRL   0xC

CMD_DL_USER_WRITE_SM_PDI_CTRL User Write SM PDI control.

◆ CMD_DL_USER_READ_LATCH_TIME

#define CMD_DL_USER_READ_LATCH_TIME   0xD

CMD_DL_USER_READ_LATCH_TIME User Read latch time.

◆ LATCH0_POS_EDGE

#define LATCH0_POS_EDGE   0

◆ LATCH0_NEG_EDGE

#define LATCH0_NEG_EDGE   1

◆ LATCH1_POS_EDGE

#define LATCH1_POS_EDGE   2

◆ LATCH1_NEG_EDGE

#define LATCH1_NEG_EDGE   3

◆ CMD_DL_USER_READ_SYS_TIME

#define CMD_DL_USER_READ_SYS_TIME   0xE

CMD_DL_USER_READ_SYS_TIME User Read sys time.

◆ CMD_DL_USER_CLEAR_AL_EVENT_LOW

#define CMD_DL_USER_CLEAR_AL_EVENT_LOW   0xF

CMD_DL_USER_CLEAR_AL_EVENT_LOW User clear AL event low.

◆ SWAPWORD

#define SWAPWORD

◆ SWAPDWORD

#define SWAPDWORD

◆ ICSS_MDIO_USRPHYSEL_LINKINT_ENABLE

#define ICSS_MDIO_USRPHYSEL_LINKINT_ENABLE   0x40

◆ ICSS_MDIO_USRPHYSEL_LINKSTAT_MLINK

#define ICSS_MDIO_USRPHYSEL_LINKSTAT_MLINK   0x80

◆ TIESC_PERM_RW

#define TIESC_PERM_RW   0x0

◆ TIESC_PERM_WRITE_ONLY

#define TIESC_PERM_WRITE_ONLY   0x1

◆ TIESC_PERM_READ_ONLY

#define TIESC_PERM_READ_ONLY   0x2

◆ TIESC_PERM_WRITE

#define TIESC_PERM_WRITE   TIESC_PERM_WRITE_ONLY

◆ TIESC_PERM_READ

#define TIESC_PERM_READ   TIESC_PERM_READ_ONLY

◆ PDI_PERM_RW

#define PDI_PERM_RW   0x0

◆ PDI_PERM_READ_ONLY

#define PDI_PERM_READ_ONLY   0x1

◆ PDI_PERM_WRITE

#define PDI_PERM_WRITE   PDI_PERM_RW

◆ PDI_PERM_READ

#define PDI_PERM_READ   PDI_PERM_READ_ONLY

◆ TIESC_MDIO_CLKDIV

#define TIESC_MDIO_CLKDIV   79

◆ TIESC_MDIO_RX_LINK_DISABLE

#define TIESC_MDIO_RX_LINK_DISABLE   0

◆ TIESC_MDIO_RX_LINK_ENABLE

#define TIESC_MDIO_RX_LINK_ENABLE   1

◆ TIESC_LINK_POL_ACTIVE_LOW

#define TIESC_LINK_POL_ACTIVE_LOW   1

◆ TIESC_LINK_POL_ACTIVE_HIGH

#define TIESC_LINK_POL_ACTIVE_HIGH   0

◆ PDI_WD_TRIGGER_RX_SOF

#define PDI_WD_TRIGGER_RX_SOF   (0 << 4)

PDI_WD_TRIGGER_RX_SOF Watchdog RX Start of Frame Trigger.

◆ PDI_WD_TRIGGER_LATCH_IN

#define PDI_WD_TRIGGER_LATCH_IN   (1 << 4)

PDI_WD_TRIGGER_LATCH_IN Watchdog LATCH IN Trigger.

◆ PDI_WD_TRIGGER_SYNC0_OUT

#define PDI_WD_TRIGGER_SYNC0_OUT   (2 << 4)

PDI_WD_TRIGGER_SYNC0_OUT Watchdog SYNC0 Trigger.

◆ PDI_WD_TRIGGER_SYNC1_OUT

#define PDI_WD_TRIGGER_SYNC1_OUT   (3 << 4)

PDI_WD_TRIGGER_SYNC1_OUT Watchdog SYNC1 Trigger.

◆ TIESC_PORT0_TX_DELAY

#define TIESC_PORT0_TX_DELAY   0x50

◆ TIESC_PORT1_TX_DELAY

#define TIESC_PORT1_TX_DELAY   0x50

◆ PDI_ISR_EDIO_NUM

#define PDI_ISR_EDIO_NUM   7

◆ USE_ECAT_TIMER

#define USE_ECAT_TIMER

◆ ENABLE_PDI_TASK

#define ENABLE_PDI_TASK

◆ ENABLE_SYNC_TASK

#define ENABLE_SYNC_TASK

◆ ASSERT_DMB

#define ASSERT_DMB ( )    __asm__(" dmb")

SUPPORT_CMDACK_POLL_MODE If PDI and SYNC ISR is handled in HWI context (similar to SSC) interrupt mode of CMDACK won't work as they are low priority than SYNC and PDI ISR - use polling instead.

◆ ASSERT_DSB

#define ASSERT_DSB ( )    __asm__(" dsb")

◆ ECAT_TIMER_INC_P_MS

#define ECAT_TIMER_INC_P_MS   1000000

◆ ESC_SYSTEMTIME_OFFSET_OFFSET

#define ESC_SYSTEMTIME_OFFSET_OFFSET   0x0920

◆ ESC_SPEED_COUNTER_START_OFFSET

#define ESC_SPEED_COUNTER_START_OFFSET   0x0930

◆ ESC_DC_START_TIME_CYCLIC_OFFSET

#define ESC_DC_START_TIME_CYCLIC_OFFSET   0x0990

◆ DRIFTCTRL_TASK_SYNC_ZERO_CROSS_ADJUST

#define DRIFTCTRL_TASK_SYNC_ZERO_CROSS_ADJUST   0xE0

◆ LOCK_PD_BUF_AVAILABLE_FOR_HOST

#define LOCK_PD_BUF_AVAILABLE_FOR_HOST   0

LOCK_PD_BUF_AVAILABLE_FOR_HOST LOCK available for HOST.

◆ LOCK_PD_BUF_HOST_ACCESS_START

#define LOCK_PD_BUF_HOST_ACCESS_START   1

LOCK_PD_BUF_HOST_ACCESS_START Lock available for host access start.

◆ LOCK_PD_BUF_HOST_ACCESS_FINISH

#define LOCK_PD_BUF_HOST_ACCESS_FINISH   2

LOCK_PD_BUF_HOST_ACCESS_FINISH Lock available for host access finish.

◆ LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT

#define LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT   (10U)

LOCK_PD_BUF_CHECK_AVAILABILITY_RETRY_COUNT Number of times the lock_state of SM is checked for availability in bsp_get_process_data_address function, in case the lock_state is not LOCK_PD_BUF_HOST_ACCESS_START.

Typedef Documentation

◆ bsp_eeprom_read_t

typedef int32_t(* bsp_eeprom_read_t) (uint8_t *buf, uint32_t len)

◆ bsp_eeprom_write_t

typedef int32_t(* bsp_eeprom_write_t) (uint8_t *buf, uint32_t len)

◆ bsp_init_spinlock_t

typedef void(* bsp_init_spinlock_t) (void)

◆ bsp_hwspinlock_lock_t

typedef uint32_t(* bsp_hwspinlock_lock_t) (int num)

◆ bsp_hwspinlock_unlock_t

typedef void(* bsp_hwspinlock_unlock_t) (int num)

◆ bsp_ethphy_init_t

typedef void(* bsp_ethphy_init_t) (PRUICSS_Handle pruIcssHandle, uint8_t phy0addr, uint8_t phy1addr, uint8_t enhancedlink_enable)

◆ bsp_get_phy_address_t

typedef int8_t(* bsp_get_phy_address_t) (uint8_t instance, uint8_t portNumber)

◆ bsp_ethercat_stack_isr_function

typedef void(* bsp_ethercat_stack_isr_function) (void)