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◆ CSL_CORE_ID_M4FSS0_0
#define CSL_CORE_ID_M4FSS0_0 (0U) |
◆ CSL_CORE_ID_R5FSS0_0
#define CSL_CORE_ID_R5FSS0_0 (1U) |
◆ CSL_CORE_ID_R5FSS0_1
#define CSL_CORE_ID_R5FSS0_1 (2U) |
◆ CSL_CORE_ID_R5FSS1_0
#define CSL_CORE_ID_R5FSS1_0 (3U) |
◆ CSL_CORE_ID_R5FSS1_1
#define CSL_CORE_ID_R5FSS1_1 (4U) |
◆ CSL_CORE_ID_A53SS0_0
#define CSL_CORE_ID_A53SS0_0 (5U) |
◆ CSL_CORE_ID_A53SS0_1
#define CSL_CORE_ID_A53SS0_1 (6U) |
◆ CSL_CORE_ID_MAX
#define CSL_CORE_ID_MAX (7U) |
◆ CSL_EPWM_PER_CNT
#define CSL_EPWM_PER_CNT (9U) |
Number of ePWM instances.
◆ MCAN_MSG_RAM_MAX_WORD_COUNT
#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U) |
MCAN Maximum Message RAM words.