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AM64x MCU+ SDK
08.01.00
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Go to the documentation of this file.
80 #define ENETPHY_IS_ADDR_VALID(addr) ((addr) <= 31U)
83 #define ENETPHY_BIT(n) (1U << (n))
86 #define ENETPHY_IS_BIT_SET(val, n) (((val) & ENETPHY_BIT(n)) != 0U)
89 #define ENETPHY_ARRAYSIZE(x) (sizeof(x) / sizeof(x[0]))
103 #define ENETPHY_SOK (CSL_PASS)
106 #define ENETPHY_EFAIL (CSL_EFAIL)
109 #define ENETPHY_EBADARGS (CSL_EBADARGS)
112 #define ENETPHY_EINVALIDPARAMS (CSL_EINVALID_PARAMS)
115 #define ENETPHY_ETIMEOUT (CSL_ETIMEOUT)
118 #define ENETPHY_EALLOC (CSL_EALLOC)
121 #define ENETPHY_EPERM (CSL_EALLOC - 4)
124 #define ENETPHY_ENOTSUPPORTED (CSL_EALLOC - 5)
138 #define ENETPHY_LINK_CAP_HD10 ENETPHY_BIT(1)
141 #define ENETPHY_LINK_CAP_FD10 ENETPHY_BIT(2)
144 #define ENETPHY_LINK_CAP_HD100 ENETPHY_BIT(3)
147 #define ENETPHY_LINK_CAP_FD100 ENETPHY_BIT(4)
150 #define ENETPHY_LINK_CAP_HD1000 ENETPHY_BIT(5)
153 #define ENETPHY_LINK_CAP_FD1000 ENETPHY_BIT(6)
156 #define ENETPHY_LINK_CAP_10 (ENETPHY_LINK_CAP_HD10 | \
157 ENETPHY_LINK_CAP_FD10)
160 #define ENETPHY_LINK_CAP_100 (ENETPHY_LINK_CAP_HD100 | \
161 ENETPHY_LINK_CAP_FD100)
164 #define ENETPHY_LINK_CAP_1000 (ENETPHY_LINK_CAP_HD1000 | \
165 ENETPHY_LINK_CAP_FD1000)
168 #define ENETPHY_LINK_CAP_ALL (ENETPHY_LINK_CAP_HD10 | \
169 ENETPHY_LINK_CAP_FD10 | \
170 ENETPHY_LINK_CAP_HD100 | \
171 ENETPHY_LINK_CAP_FD100 | \
172 ENETPHY_LINK_CAP_HD1000 | \
173 ENETPHY_LINK_CAP_FD1000)
178 #define ENETPHY_EXTENDED_CFG_SIZE_MAX (128U)
181 #define ENETPHY_FSM_TICK_PERIOD_MS (100U)
184 #define ENETPHY_INVALID_PHYADDR (~0U)
193 typedef enum EnetPhy_Magic_e
205 typedef enum EnetPhy_Mii_e
229 typedef enum EnetPhy_Speed_e
247 typedef enum EnetPhy_Duplexity_e
262 typedef struct EnetPhy_Version_s
277 typedef enum EnetPhy_LinkStatus_e
295 typedef struct EnetPhy_LinkCfg_s
307 typedef struct EnetPhy_FsmTimeoutCfg_s
334 typedef struct EnetPhy_Cfg_s
378 typedef struct EnetPhy_Mdio_s
392 int32_t (*isAlive)(uint32_t phyAddr,
408 int32_t (*isLinked)(uint32_t phyAddr,
425 int32_t (*readC22)(uint32_t group,
444 int32_t (*writeC22)(uint32_t group,
464 int32_t (*readC45)(uint32_t group,
485 int32_t (*writeC45)(uint32_t group,
506 typedef enum EnetPhy_FsmState_e
542 typedef struct EnetPhy_State_s
593 typedef struct EnetPhy_Obj_s
671 const void *extendedCfg,
672 uint32_t extendedCfgSize);
694 uint32_t macPortCaps,
bool enableMdix
Definition: enetphy.h:587
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:611
void EnetPhy_setExtendedCfg(EnetPhy_Cfg *phyCfg, const void *extendedCfg, uint32_t extendedCfgSize)
Set PHY extended parameters.
uint32_t nwayStartStateTicks
NWAY_START state timeout (in ticks)
Definition: enetphy.h:319
int32_t EnetPhy_readExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY extended register.
uint32_t findingStateTicks
FINDING state timeout (in ticks)
Definition: enetphy.h:310
bool extClkSource
Definition: enetphy.h:360
bool loopbackEn
Definition: enetphy.h:354
EnetPhy_MdioHandle hMdio
Definition: enetphy.h:596
uint32_t addr
Definition: enetphy.h:620
int32_t EnetPhy_rmwC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register using Clause-45 frame.
EnetPhy_FsmTimeoutCfg timeoutCfg
Definition: enetphy.h:366
@ ENETPHY_SPEED_10MBIT
Definition: enetphy.h:232
uint32_t residenceTime
Definition: enetphy.h:560
@ ENETPHY_FSM_STATE_FOUND
FOUND state.
Definition: enetphy.h:521
uint32_t phyAddr
Definition: enetphy.h:340
@ ENETPHY_FSM_STATE_NWAY_WAIT
NWAY_WAIT state (auto-negotiation path)
Definition: enetphy.h:527
EnetPhy_Speed speed
Definition: enetphy.h:551
int32_t EnetPhy_getLinkCfg(EnetPhy_Handle hPhy, EnetPhy_LinkCfg *linkCfg)
Get link configuration.
int32_t EnetPhy_readC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t *val)
Read PHY register using Clause-45 frame.
int32_t EnetPhy_rmwExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY extended register.
struct EnetPhy_Drv_s * EnetPhyDrv_Handle
PHY specific driver handle.
Definition: enetphy.h:501
void EnetPhy_printRegs(EnetPhy_Handle hPhy)
Print all PHY registers.
@ ENETPHY_FSM_STATE_LINK_WAIT
LINK_WAIT state.
Definition: enetphy.h:530
EnetPhy_Mii
MAC Media-Independent Interface (MII).
Definition: enetphy.h:206
EnetPhyDrv_Handle hDrv
Definition: enetphy.h:626
@ ENETPHY_MAGIC
Definition: enetphy.h:196
@ ENETPHY_LINK_DOWN
Definition: enetphy.h:289
@ ENETPHY_FSM_STATE_ENABLE
ENABLE state.
Definition: enetphy.h:518
uint32_t linkCaps
Definition: enetphy.h:575
@ ENETPHY_MAC_MII_RMII
RMII interface.
Definition: enetphy.h:211
@ ENETPHY_MAC_MII_GMII
GMII interface.
Definition: enetphy.h:214
bool skipExtendedCfg
Definition: enetphy.h:363
@ ENETPHY_SPEED_AUTO
Definition: enetphy.h:241
uint32_t revision
Definition: enetphy.h:271
EnetPhy_Duplexity duplexity
Definition: enetphy.h:301
bool needsManualCfg
Definition: enetphy.h:569
int32_t EnetPhy_readReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t *val)
Read PHY register.
PHY configuration parameters.
Definition: enetphy.h:335
EnetPhy_FsmState
PHY driver state-machine states.
Definition: enetphy.h:507
int32_t EnetPhy_getId(EnetPhy_Handle hPhy, EnetPhy_Version *version)
Get PHY id.
@ ENETPHY_MAC_MII_MII
MII interface.
Definition: enetphy.h:208
bool EnetPhy_isAlive(EnetPhy_Handle hPhy)
Get PHY alive status.
uint32_t mdixTicks
Timeout if MDIX is enabled (in ticks)
Definition: enetphy.h:328
@ ENETPHY_DUPLEX_HALF
Definition: enetphy.h:250
bool needsMdixSwitch
Definition: enetphy.h:584
PHY version (ID).
Definition: enetphy.h:263
uint32_t resetWaitStateTicks
RESET_WAIT state timeout (in ticks)
Definition: enetphy.h:313
@ ENETPHY_DUPLEX_FULL
Definition: enetphy.h:253
EnetPhy_State state
Definition: enetphy.h:614
void EnetPhy_close(EnetPhy_Handle hPhy)
Close the PHY driver.
EnetPhy_LinkCfg linkCfg
Definition: enetphy.h:608
@ ENETPHY_SPEED_1GBIT
Definition: enetphy.h:238
EnetPhy_Mdio * EnetPhy_MdioHandle
MDIO driver handle.
Definition: enetphy.h:496
@ ENETPHY_FSM_STATE_LOOPBACK
LOOPBACK state.
Definition: enetphy.h:536
EnetPhy_Handle EnetPhy_open(const EnetPhy_Cfg *phyCfg, EnetPhy_Mii mii, const EnetPhy_LinkCfg *linkCfg, uint32_t macPortCaps, EnetPhy_MdioHandle hMdio, void *mdioArgs)
Open the PHY driver.
EnetPhy_Speed speed
Definition: enetphy.h:298
PHY State-Machine time-out values.
Definition: enetphy.h:308
struct EnetPhy_Obj_s * EnetPhy_Handle
PHY driver object handle.
Definition: enetphy.h:640
bool EnetPhy_isLinked(EnetPhy_Handle hPhy)
Get link status.
@ ENETPHY_LOST_LINK
Definition: enetphy.h:286
int32_t EnetPhy_writeC45Reg(EnetPhy_Handle hPhy, uint8_t mmd, uint32_t reg, uint16_t val)
Write PHY register using Clause-45 frame.
@ ENETPHY_NO_MAGIC
Definition: enetphy.h:199
@ ENETPHY_GOT_LINK
Definition: enetphy.h:280
EnetPhy_Magic magic
Definition: enetphy.h:629
void * mdioArgs
Definition: enetphy.h:632
uint32_t model
Definition: enetphy.h:268
@ ENETPHY_FSM_STATE_NWAY_START
NWAY_START state (auto-negotiation path)
Definition: enetphy.h:524
int32_t EnetPhy_writeReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY register.
@ ENETPHY_DUPLEX_AUTO
Definition: enetphy.h:256
EnetPhy_Mii mii
Definition: enetphy.h:602
@ ENETPHY_LINK_UP
Definition: enetphy.h:283
PHY driver FSM state.
Definition: enetphy.h:543
uint32_t nwayWaitStateTicks
NWAY_WAIT state timeout (in ticks)
Definition: enetphy.h:322
uint32_t resetWaitStateResidenceTicks
RESET_WAIT state residence time (in ticks)
Definition: enetphy.h:316
@ ENETPHY_SPEED_100MBIT
Definition: enetphy.h:235
@ ENETPHY_FSM_STATE_FINDING
FINDING state.
Definition: enetphy.h:512
@ ENETPHY_MAC_MII_SGMII
SGMII interface.
Definition: enetphy.h:220
bool mdixEn
Definition: enetphy.h:346
uint32_t extendedCfgSize
Definition: enetphy.h:372
bool masterMode
Definition: enetphy.h:357
@ ENETPHY_FSM_STATE_INIT
INIT state.
Definition: enetphy.h:509
bool isNwayCapable
Definition: enetphy.h:563
#define ENETPHY_EXTENDED_CFG_SIZE_MAX
Max extended configuration size, arbitrarily chosen.
Definition: enetphy.h:178
bool needsNwayCfg
Definition: enetphy.h:572
@ ENETPHY_MAC_MII_QSGMII
QSGMII interface.
Definition: enetphy.h:223
uint32_t oui
Definition: enetphy.h:265
Link speed and duplexity configuration.
Definition: enetphy.h:296
void EnetPhy_initCfg(EnetPhy_Cfg *phyCfg)
Initialize PHY config params.
EnetPhy_FsmState fsmState
Definition: enetphy.h:545
EnetPhy_Duplexity duplexity
Definition: enetphy.h:554
bool fsmStateChanged
Definition: enetphy.h:548
uint32_t nwayCaps
Definition: enetphy.h:343
int32_t EnetPhy_writeExtReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t val)
Write PHY extended register.
uint32_t linkWaitStateTicks
LINK_WAIT state timeout (in ticks)
Definition: enetphy.h:325
EnetPhy_Duplexity
MAC interface duplexity.
Definition: enetphy.h:248
@ ENETPHY_MAC_MII_RGMII
RGMII interface.
Definition: enetphy.h:217
int32_t EnetPhy_rmwReg(EnetPhy_Handle hPhy, uint32_t reg, uint16_t mask, uint16_t val)
Read-modify-write PHY register.
bool loopbackEn
Definition: enetphy.h:581
bool enableNway
Definition: enetphy.h:566
PHY driver object.
Definition: enetphy.h:594
uint32_t group
Definition: enetphy.h:617
uint32_t macCaps
Definition: enetphy.h:605
uint32_t phyLinkCaps
Definition: enetphy.h:578
uint32_t reqLinkCaps
Definition: enetphy.h:623
uint32_t phyGroup
Definition: enetphy.h:337
EnetPhy_LinkStatus EnetPhy_tick(EnetPhy_Handle hPhy)
Run PHY state machine.
EnetPhy_Speed
MAC interface speed.
Definition: enetphy.h:230
bool isStrapped
Definition: enetphy.h:351
MDIO driver.
Definition: enetphy.h:379
@ ENETPHY_FSM_STATE_RESET_WAIT
RESET_WAIT state.
Definition: enetphy.h:515
EnetPhy_Cfg phyCfg
Definition: enetphy.h:599
@ ENETPHY_FSM_STATE_LINKED
LINKED state.
Definition: enetphy.h:533
EnetPhy_Magic
EnetPhy driver magic value, used to indicate if driver is open or not.
Definition: enetphy.h:194
uint16_t version
Definition: tisci_core.h:2
uint32_t timeout
Definition: enetphy.h:557
EnetPhy_LinkStatus
PHY link status.
Definition: enetphy.h:278