AM64x MCU+ SDK  08.00.00
EtherNet/IP Adapter


This software is designed for the TI SoCs with PRU-ICSS IP to enable customers add EtherNet/IP Adapter protocol support to their system. It implements EtherNet/IP + PTP + DLR functionality and provides EtherNet/IP ASIC like functionality integrated into TI SoCs.

Software Architecture

EtherNet/IP firmware for PRU-ICSS is a black box product maintained by TI. EtherNet/IP Adapter FWHAL(Firmware and Hardware Abstraction Layer) allows loading and run EtherNet/IP firmware and acts as an interface with the firmware.

PRU-ICSS EtherNet/IP Adapter Firmware

Features Supported

  • Integrated two-port cut-through switch
    • 100 Mbps, 10Mbps
    • Full Duplex, Half Duplex
  • Quality of Service (QoS)
    • Four priority receive queues on host port, each queue 6 KB in size
    • Four priority transmit queues on each physical port, each queue 3 KB in size
  • DLR – Device Level Ring
    • 200us beacon interval
    • 400us beacon timeout
    • Self-Configuring
  • PTP/1588 - Time Synchronization
    • E2E mode supported
    • CIP Sync capable
    • Transparent and Ordinary Clock
  • 1 ms buffering per port
  • 802.1d learning bridge for received source MAC addresses
    • 1024 addresses per port
    • APIs for port state configuration and flushing learning table upon change in network topology
    • Switch address learned table (FDB) is flushed in 2.4 us
  • Multicast and Broadcast storm prevention per port
  • Interrupt for Link loss detection
    • Callback APIs to perform tasks related to change in network topology
  • Statistics
    • Media counters supported per port
    • Interface counters supported per port

Known Issues

Record ID Details Workaround
PINDSW-4982 SQE and Carrier Sense Errors counters not supported in EtherNet/IP


Important Files and Directory Structure

Folder/Files Description
ethernetip_adapter_demo EtherNet/IP Adapter Example
icss_fwhal/firmware Firmware for the PRU cores in PRU-ICSS. Firmware Version : 5.2.7
icss_fwhal/lib/ FWHAL library for EtherNet/IP Adapter
icss_fwhal/*.c FWHAL source files
icss_fwhal/*.h FWHAL interface files

Stack header files and stack library

Terms and Abbreviations

Abbreviation Expansion
PRU-ICSS Programmable Real-Time Unit Industrial Communication Subsystem
DLR Device Level Ring (A redundancy protocol)
PTP Precision Time Protocol
OC Ordinary Clock
TC Transparent Clock
E2E End to End


EtherNet/IP Adapter examples for MII and RGMII mode with evaluation libraries for stack are provided in the SDK. Please see EtherNet/IP Adapter Demos for more details.


Stack functionality and APIs are explained here.

EtherNet/IP Adapter FWHAL (Firmware and Hardware Abstraction Layer)

EtherNet/IP Adapter FWHAL implements the key interface between EtherNet/IP Adapter firmware and EtherNet/IP Adapter firm stack. Please see APIs for EtherNet/IP Adapter FWHAL for API documentation.

Procedure to kick-off the EtherNet/IP Adapter

  • Initialize ICSS-EMAC to work as a switch
  • Initialize the required tasks and interrupts
  • Initialize the EtherNet/IP FWHAL, PTP, DLR and PRU-ICSS INTC
  • Register the callbacks
  • Load EtherNet/IP firmware into PRUs of PRU-ICSS
  • Initialize the EtherNet/IP slave stack
  • Start firmware
  • Handle the events as needed. The Event/ISR definitions are available in developer guide(provide a link here), these have respective callbacks that can be registered to custom stack APIs.

Integration with ICSS-EMAC

Ethernet/IP Adapter examples uses the ICSS-EMAC as its base switch layer. The PRU Firmware provides switch functionality and additional PTP and DLR functionalities. The NRT(non-real time) traffic is handled by ICSS-EMAC, wherein the packets are forwarded either to the TCP stack or a custom callback (configurable in ICSS-EMAC).

Interface with ICSS-EMAC

Ethernet/IP packets are standard ethernet frames and all protocol specific data is embedded in TCP/IP payload. Hence the standard switch model applies. Packets are segregated based on VLAN PCP field. The 8 priorities which map to 4 queues, with highest and next highest priorities going to Queue 0 and Queue 1 and so on. If PCP field does not exist, then frames go to Queue 3. All queues except the highest priority queue forward the frames to TCP/IP stack. Further if packet type does not match PTP or DLR then that frame goes to TCP/IP stack. The highest priority queues are used for PTP and DLR. These packets are directly forwarded to the registered callback in ICSS-EMAC (using rxRTCallBack).


EtherNet/IP firmware generates the following interrupts.

8 Host Interrupts (Host Interrupts 2 through 9) are exported from the PRU_ICSSG internal INTC for signaling the device level interrupt controllers. PRU_EVTOUT0 to PRU_EVTOUT7 correspond to these eight interrupts in the following table. Please check PRUICSS Interrupt Controller section for more details.

Name Host Interrupt Description
Frame Receive PRU_EVTOUT0 Notifies host when firmware has stored a frame in host receive queue
DLR Port 0 Interrupt PRU_EVTOUT1 Raised when there is a state change in DLR on Port 0
DLR Port 1 Interrupt PRU_EVTOUT2 Raised when there is a state change in DLR on Port 1
Tx Callback Interrupt PRU_EVTOUT3 Raised when a PTP/1588 frame which requires Tx Timestamping is sent out
DLR Beacon Timeout Interrupt for Port 0 PRU_EVTOUT4 Raised when the beacon timeout timer on Port 0 expires
DLR Beacon Timeout Interrupt for Port 1 PRU_EVTOUT7 Raised when the beacon timeout timer on Port 1 expires
Link Change PRU_EVTOUT6 Interrupt is raised when the link on Ethernet PHY comes up or goes down

Device Level Ring

Device Level Ring on EtherNet/IP firmware provides redundancy to the switch implementation. It is a beacon based implementation with support for a minimum beacon of 200us and timeout of 400us. More information is available in developer guide(provide a link here).

IEEE PTP-1588 Implementation

PTP/1588 on EtherNet/IP provides time synchronization support. The implementation is driven by CIP Sync requirements which require End to End clock support over UDP (Annex D). EtherNet/IP adapter application supports both OC and TC implementations along with syntonization.

Additional References

Please refer to below documents to understand more about EtherNet/IP Adapter on TI platforms and EtherNet/IP Adapter protocol specifications.

Document Description
EtherNet/IP on TI's Sitara processors Application note by TI on the EtherNet/IP Adapter implementation on TI's Sitara Processors.

See also