sciclient_fmwMsgParams.h

Go to the documentation of this file.

/*
 *  Copyright (C) 2022-26 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */
 
#ifndef SCICLIENT_FMWMSGPARAMS_H_
#define SCICLIENT_FMWMSGPARAMS_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
 
#define TISCI_PARAM_UNDEF                                        (0xFFFFFFFFU)
 
/* ABI Major revision - Major revision changes
*       indicate backward compatibility breakage */
#define SCICLIENT_FIRMWARE_ABI_MAJOR                     (4U)
/* ABI Minor revision - Minor revision changes
*       indicate backward compatibility is maintained,
*       however, new messages OR extensions to existing
*       messages might have been adde */
#define SCICLIENT_FIRMWARE_ABI_MINOR                     (0U)
 
#define SCICLIENT_CONTEXT_R5_SEC_0                     (0U)
 
#define SCICLIENT_CONTEXT_R5_NONSEC_0                  (1U)
 
#define SCICLIENT_CONTEXT_R5_SEC_1                     (2U)
 
#define SCICLIENT_CONTEXT_R5_NONSEC_1                  (3U)
 
#define SCICLIENT_CONTEXT_A53_SEC_0                    (4U)
 
#define SCICLIENT_CONTEXT_A53_SEC_1                    (5U)
 
#define SCICLIENT_CONTEXT_A53_NONSEC_0                 (6U)
 
#define SCICLIENT_CONTEXT_A53_NONSEC_1                 (7U)
 
#define SCICLIENT_CONTEXT_M4_NONSEC_0                  (8U)
 
#define SCICLIENT_CONTEXT_GPU_NONSEC_0                 (9U)
 
#define SCICLIENT_CONTEXT_A53_NONSEC_2                 (10U)
 
#define SCICLIENT_CONTEXT_DM2TIFS                      (11U)
 
#define SCICLIENT_CONTEXT_MAX_NUM                      (12U)
 
#define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)
 
#define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)
 
#define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)
 
#define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)
 
#define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)
/*** AM62_MAIN_SEC_MMR_MAIN_0: (Cluster 16 Processor 0) */
#define SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0 (0x18U)
/*** AM62A_HSM_SEC_MMR_0: (Cluster 28 Processor 0) */
#define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)
 
#define SOC_NUM_SCICLIENT_PROCESSORS (0x07U)
 
 
 
#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE     (0xFFFFu)
#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX    (0xFFFFFFFFu)
#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR     (0xFFFFFFFFu)
#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT    (0xFFFFFFFFu)
 
#define TISCI_MSG_VALUE_RM_NULL_RING_MODE      (0xFFu)
#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE      (0xFFu)
#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID       (0xFFu)
#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE  (0xFFu)
#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
 
#include <drivers/sciclient/include/tisci/am62x/tisci_devices.h>
#include <drivers/sciclient/include/tisci/am62x/tisci_clocks.h>
#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START         (20U)
#define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START        (32U)
#define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START         (0U)
#define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START      (4096U)
#define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START  (4608U)
#define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START      (5120U)
#define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START  (5632U)
#define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)
#define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)
#define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START       (8192U)
#define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START     (8704U)
#define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START     (9216U)
#define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START       (9728U)
#define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START     (10240U)
#define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START     (10752U)
#define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START       (11264U)
#define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START     (11776U)
#define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START     (12288U)
 
#define SCICLIENT_DEV_WKUP_R5FSS0_CORE0  (TISCI_DEV_WKUP_R5FSS0_CORE0)
#define SCICLIENT_DEV_WKUP_R5FSS0_CORE1  (TISCI_DEV_WKUP_R5FSS0_CORE0)
 
#define SCICLIENT_DEV_WKUP_R5FSS0_CORE0_PROCID  \
    (SCICLIENT_PROC_ID_R5FSS0_CORE0)
#define SCICLIENT_DEV_WKUP_R5FSS0_CORE1_PROCID  \
    (SCICLIENT_PROC_ID_R5FSS0_CORE0)
 
#define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1U
 
#define SCICLIENT_ALLOWED_BOARDCFG_BASE_END   0xFFFFFFFFU
 
/* ========================================================================== */
/*                         Structure Declarations                             */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif /* #ifndef SCICLIENT_FMWMSGPARAMS_H_ */