Introduction

Files
file	sciclient_fmwMsgParams.h
	This file contains the definition of all the parameter IDs for PM, RM, Security.

Macros
#define	TISCI_PARAM_UNDEF (0xFFFFFFFFU)

#define	TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)

#define	TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)

#define	TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)

#define	TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)

#define	TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)

#define	SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1U

#define	SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFFU

Sciclient Firmware ABI revisions
ABI revisions for compatibility check.
#define	SCICLIENT_FIRMWARE_ABI_MAJOR (3U)

#define	SCICLIENT_FIRMWARE_ABI_MINOR (5U)

Sciclient Context Ids
Context IDs for Sciclient_ConfigPrms_t .
#define	SCICLIENT_CONTEXT_R5_SEC_0 (0U)

#define	SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)

#define	SCICLIENT_CONTEXT_R5_SEC_1 (2U)

#define	SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)

#define	SCICLIENT_CONTEXT_A53_SEC_0 (4U)

#define	SCICLIENT_CONTEXT_A53_SEC_1 (5U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)

#define	SCICLIENT_CONTEXT_M4_NONSEC_0 (8U)

#define	SCICLIENT_CONTEXT_GPU_NONSEC_0 (9U)

#define	SCICLIENT_CONTEXT_A53_NONSEC_2 (10U)

#define	SCICLIENT_CONTEXT_MAX_NUM (11U)

Sciclient Processor Ids
Processor IDs for the Processor Boot Configuration APIs.
#define	SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)

#define	SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)

#define	SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)

#define	SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)

#define	SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)

#define	SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0 (0x18U)

#define	SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)

#define	SOC_NUM_SCICLIENT_PROCESSORS (0x07U)

IRQ source index start
Start offset of IRQ source index.
#define	TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (20U)

#define	TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (32U)

#define	TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START (0U)

#define	TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)

#define	TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)

#define	TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)

#define	TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)

#define	TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)

#define	TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)

#define	TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)

#define	TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)

#define	TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)

#define	TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)

#define	TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)

#define	TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)

#define	TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)

#define	TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)

#define	TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)

MCU Pulsar IDs
MCU Device CPU IDs.
#define	SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)

#define	SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)

MCU Pulsar Processor IDs
MCU Device Processor IDs.
#define	SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID (SCICLIENT_PROC_ID_R5FSS0_CORE0)

#define	SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID (SCICLIENT_PROC_ID_R5FSS0_CORE0)

Macro Definition Documentation

◆ TISCI_PARAM_UNDEF

#define TISCI_PARAM_UNDEF (0xFFFFFFFFU)

Undefined Param Undefined

◆ SCICLIENT_FIRMWARE_ABI_MAJOR

#define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)

◆ SCICLIENT_FIRMWARE_ABI_MINOR

#define SCICLIENT_FIRMWARE_ABI_MINOR (5U)

◆ SCICLIENT_CONTEXT_R5_SEC_0

#define SCICLIENT_CONTEXT_R5_SEC_0 (0U)

r5(Secure): Cortex R5 Context 0

◆ SCICLIENT_CONTEXT_R5_NONSEC_0

#define SCICLIENT_CONTEXT_R5_NONSEC_0 (1U)

r5(Non Secure): Cortex R5 Context 1

◆ SCICLIENT_CONTEXT_R5_SEC_1

#define SCICLIENT_CONTEXT_R5_SEC_1 (2U)

r5(Secure): Cortex R5 Context 2

◆ SCICLIENT_CONTEXT_R5_NONSEC_1

#define SCICLIENT_CONTEXT_R5_NONSEC_1 (3U)

r5(Non Secure): Cortex R5 Context 3

◆ SCICLIENT_CONTEXT_A53_SEC_0

#define SCICLIENT_CONTEXT_A53_SEC_0 (4U)

a53(Secure): Cortex A53 context 0

◆ SCICLIENT_CONTEXT_A53_SEC_1

#define SCICLIENT_CONTEXT_A53_SEC_1 (5U)

a53(Non Secure): Cortex A53 context 1

◆ SCICLIENT_CONTEXT_A53_NONSEC_0

#define SCICLIENT_CONTEXT_A53_NONSEC_0 (6U)

a53(Non Secure): Cortex A53 context 2

◆ SCICLIENT_CONTEXT_A53_NONSEC_1

#define SCICLIENT_CONTEXT_A53_NONSEC_1 (7U)

a53(Non Secure): Cortex A53 context 3

◆ SCICLIENT_CONTEXT_M4_NONSEC_0

#define SCICLIENT_CONTEXT_M4_NONSEC_0 (8U)

M4 (Non Secure): Cortex M4 context 1

◆ SCICLIENT_CONTEXT_GPU_NONSEC_0

#define SCICLIENT_CONTEXT_GPU_NONSEC_0 (9U)

r5(Secure): GPU Context 0

◆ SCICLIENT_CONTEXT_A53_NONSEC_2

#define SCICLIENT_CONTEXT_A53_NONSEC_2 (10U)

r5(Non Secure): ICSSG_0 Context 1

◆ SCICLIENT_CONTEXT_MAX_NUM

#define SCICLIENT_CONTEXT_MAX_NUM (11U)

Total number of possible contexts for application.

◆ SCICLIENT_PROC_ID_A53SS0_CORE_0

#define SCICLIENT_PROC_ID_A53SS0_CORE_0 (0x20U)

AM62_MAIN_SEC_MMR_MAIN_0: (Cluster 9 Processor 0)

◆ SCICLIENT_PROC_ID_A53SS0_CORE_1

#define SCICLIENT_PROC_ID_A53SS0_CORE_1 (0x21U)

AM62_MAIN_SEC_MMR_MAIN_0: (Cluster 9 Processor 1)

◆ SCICLIENT_PROC_ID_A53SS0_CORE_2

#define SCICLIENT_PROC_ID_A53SS0_CORE_2 (0x22U)

AM62_MAIN_SEC_MMR_MAIN_0: (Cluster 9 Processor 2)

◆ SCICLIENT_PROC_ID_A53SS0_CORE_3

#define SCICLIENT_PROC_ID_A53SS0_CORE_3 (0x23U)

AM62_MAIN_SEC_MMR_MAIN_0: (Cluster 9 Processor 3)

◆ SCICLIENT_PROC_ID_R5FSS0_CORE0

#define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x01U)

AM62_WKUP_SEC_MMR_WKUP_0: (Cluster 28 Processor 0)

◆ SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0

#define SCICLIENT_PROC_ID_MCU_M4FSS0_CORE0 (0x18U)

◆ SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0

#define SCICLIENT_PROC_ID_HSM_M4FSS0_CORE0 (0x80U)

◆ SOC_NUM_SCICLIENT_PROCESSORS

#define SOC_NUM_SCICLIENT_PROCESSORS (0x07U)

Total Number of processors in AM62A

◆ TISCI_MSG_VALUE_RM_NULL_RING_TYPE

#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)

-----------------— Resource Management Parameters ------------------—

◆ TISCI_MSG_VALUE_RM_NULL_RING_INDEX

#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_ADDR

#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_COUNT

#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)

◆ TISCI_MSG_VALUE_RM_NULL_RING_MODE

#define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)

The ring mode field of the RING_SIZE register is not modified if this value is used for: tisci_msg_rm_ring_cfg_req::mode

◆ TISCI_MSG_VALUE_RM_NULL_RING_SIZE

#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)

◆ TISCI_MSG_VALUE_RM_NULL_ORDER_ID

#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)

◆ TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)

◆ TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX

#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)

◆ TISCI_RINGACC0_OES_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (20U)

◆ TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START

#define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (32U)

◆ TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START

#define TISCI_TIMERMGR_OES_IRQ_SRC_IDX_START (0U)

◆ TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U)

◆ TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U)

◆ TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U)

◆ TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U)

◆ TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U)

◆ TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START

#define TISCI_PKTDMA0_RX_FLOW_FOES_IRQ_SRC_IDX_START (6656U)

◆ TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U)

◆ TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U)

◆ TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U)

◆ TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U)

◆ TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U)

◆ TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U)

◆ TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U)

◆ TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U)

◆ TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START

#define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE0

#define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE1

#define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID

#define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID (SCICLIENT_PROC_ID_R5FSS0_CORE0)

◆ SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID

#define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID (SCICLIENT_PROC_ID_R5FSS0_CORE0)

◆ SCICLIENT_ALLOWED_BOARDCFG_BASE_START

#define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1U

Board config Base start address

◆ SCICLIENT_ALLOWED_BOARDCFG_BASE_END

#define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFFU

Board config Base end address