Macros | |
#define | SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS (CSL_WKUP_PSC0_BASE) |
WKUP PSC base address. More... | |
#define | SAFETY_CHECKERS_PM_PSC_PD_STAT_OFFSET (0x200U) |
PSC Power Domain(PD) STAT register offset. More... | |
#define | SAFETY_CHECKERS_PM_PSC_MD_STAT_OFFSET (0x800U) |
PSC Module Domain(MD) STAT register offset. More... | |
#define | SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS(i) (SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS + (0x1000U * (uint32_t)i)) |
Each PLL base addresses. More... | |
#define | SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS(i) (SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS + (0x1000U * (uint32_t)i)) |
#define | SAFETY_CHECKERS_PM_KICK_LOCK (0x00000000U) |
KICK lock values. More... | |
#define | SAFETY_CHECKERS_PM_LOCK_KEY0_OFFSET (0x10U) |
#define | SAFETY_CHECKERS_PM_LOCK_KEY1_OFFSET (0x14U) |
#define SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS (CSL_WKUP_PSC0_BASE) |
WKUP PSC base address.
#define SAFETY_CHECKERS_PM_PSC_PD_STAT_OFFSET (0x200U) |
PSC Power Domain(PD) STAT register offset.
#define SAFETY_CHECKERS_PM_PSC_MD_STAT_OFFSET (0x800U) |
PSC Module Domain(MD) STAT register offset.
#define SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS | ( | i | ) | (SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS + (0x1000U * (uint32_t)i)) |
Each PLL base addresses.
#define SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS | ( | i | ) | (SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS + (0x1000U * (uint32_t)i)) |
#define SAFETY_CHECKERS_PM_KICK_LOCK (0x00000000U) |
KICK lock values.
#define SAFETY_CHECKERS_PM_LOCK_KEY0_OFFSET (0x10U) |
#define SAFETY_CHECKERS_PM_LOCK_KEY1_OFFSET (0x14U) |