enet_udma.h

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/*
 *  Copyright (c) Texas Instruments Incorporated 2020
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef ENET_UDMA_H_
#define ENET_UDMA_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
 
#include <stdint.h>
#include <include/core/enet_types.h>
#include <include/core/enet_queue.h>
#include <include/dma/udma/enet_udma_types.h>
 
#include <drivers/udma.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                                 Macros                                     */
/* ========================================================================== */
 
#define ENET_UDMA_HPD_SIZE                                   (128U)
 
#define ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE               (16U)
 
#define ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE          (16U)
 
#define ENET_UDMA_PKT_DESC_RESERVED_SIZE ( ENET_UDMA_HPD_SIZE - \
                                           sizeof(CSL_UdmapCppi5HMPD) - \
                                           (ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE + \
                                           ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE))
 
#define ENET_UDMA_RING_MEM_SIZE                              (sizeof(uint64_t))
 
#define ENET_UDMA_RXMTU_ALIGN                                (1U << 5U)
 
#define ENET_UDMA_CPSW_MAX_SG_LIST                           (4U)
 
#define ENET_UDMA_CPSW_HOSTPKTDESC_INDEX                     (0U)
 
#define ENET_UDMA_CPSW_HOSTBUFDESC_INDEX                     (1U)
 
#define ENET_UDMA_CPSW_MAX_HOSTBUFDESC_COUNT                 (ENET_UDMA_CPSW_MAX_SG_LIST - ENET_UDMA_CPSW_HOSTBUFDESC_INDEX)
 
#define ENET_UDMA_HPD_SRC_TAG_LOW_MASK                       (0xFF)
 
#if ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
 
#define ENETDMA_CACHELINE_ALIGNMENT            (32U)
#elif (__aarch64__)
#define ENETDMA_CACHELINE_ALIGNMENT            (64U)
#else
#error "Enet library compilation not supported on non cortex R cores. Update correct cache line size"
#endif
 
#define ENET_UDMA_DESC_ALIGNMENT               (64U)
 
typedef struct EnetUdma_Cfg_s EnetDma_Cfg;
 
typedef struct EnetUdma_DmaDescQ_s *EnetUdma_DmaDescQHandle;
 
typedef uint8_t *(*EnetUdma_AllocRingMemFxn)(void *appPriv,
                                            uint32_t numRingEle,
                                            uint32_t alignSize);
 
typedef void (*EnetUdma_FreeRingMemFxn)(void *appPriv,
                                       void *pRingMem,
                                       uint32_t numRingEle);
 
typedef struct EnetUdma_DmaDesc_s *(*EnetUdma_AllocDmaDescFxn)(void *appPriv,
                                                             uint32_t alignSize);
 
typedef void (*EnetUdma_FreeDmaDescFxn)(void *appPriv,
                                       struct EnetUdma_DmaDesc_s *dmaDescPtr);
 
typedef void (*EnetDma_PktNotifyCb)(void *cbArg);
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
typedef struct EnetUdma_PktTsInfo_s
{
    bool enableHostTxTs;
 
    uint32_t txPktSeqId;
 
    uint8_t txPktMsgType;
 
    uint8_t txPktDomain;
 
    uint64_t rxPktTs;
} EnetUdma_PktTsInfo;
 
typedef struct EnetUdma_SGListEntry_s
{
    uint8_t *bufPtr;
 
    uint8_t *origBufPtr;
 
    uint32_t segmentFilledLen;
 
    uint32_t segmentAllocLen;
 
    bool disableCacheOps;
} EnetUdma_SGListEntry;
 
typedef struct EnetUdma_SGList_s
{
    uint32_t numScatterSegments;
    EnetUdma_SGListEntry list[ENET_UDMA_CPSW_MAX_SG_LIST];
} EnetUdma_SGList;
 
typedef EnetUdma_SGListEntry EnetDma_SGListEntry;
typedef struct EnetUdma_PktInfo_s
{
    EnetQ_Node node;
 
    void *appPriv;
 
    uint32_t pktState;
 
    uint32_t chkSumInfo;
 
    EnetUdma_PktTsInfo tsInfo;
 
    Enet_MacPort txPortNum;
 
    Enet_MacPort rxPortNum;
 
    uint32_t txPktTc;
 
    uint32_t txTsId;
    
    uint32_t perDmaFlags;
 
    EnetUdma_SGList sgList;
 
}EnetUdma_PktInfo;
 
typedef struct EnetUdma_CpswHpdDesc_s
{
    CSL_UdmapCppi5HMPD hostDesc  __attribute__ ((aligned(ENET_UDMA_DESC_ALIGNMENT)));
 
    uint8_t extendedPktInfo[ENET_UDMA_EXTENDED_PKT_INFO_BLOCK_SIZE];
 
    uint8_t psInfo[ENET_UDMA_PROTOCOL_SPECIFIC_INFO_BLOCK_SIZE];
 
    uint8_t reserved[ENET_UDMA_PKT_DESC_RESERVED_SIZE];
} EnetUdma_CpswHpdDesc;
 
typedef struct EnetUdma_DmaDesc_s
{
    EnetUdma_CpswHpdDesc hpdDesc;
 
    struct EnetUdma_HBDDesc_s
    {
        CSL_UdmapCppi5HMPD desc __attribute__ ((aligned(ENET_UDMA_DESC_ALIGNMENT)));
    } hostBufDesc[ENET_UDMA_CPSW_MAX_HOSTBUFDESC_COUNT];
 
    struct EnetUdma_DmaDesc_s *pNextDesc;
 
    EnetDma_Pkt *dmaPkt;
} EnetUdma_DmaDesc;
 
typedef struct EnetUdma_RingMonCfg_s
{
    uint8_t mode;
 
    uint32_t data0;
 
    uint32_t data1;
} EnetUdma_RingMonCfg;
 
typedef struct EnetUdma_UdmaRingPrms_s
{
    uint8_t orderId;
 
    uint8_t mode;
 
    bool useRingMon;
 
    EnetUdma_RingMonCfg ringMonCfg;
} EnetUdma_UdmaRingPrms;
 
typedef struct EnetUdma_UdmaChPrms_s
{
#if (UDMA_SOC_CFG_UDMAP_PRESENT == 1)
 
    EnetUdma_UdmaRingPrms fqRingPrms;
#endif
 
    EnetUdma_UdmaRingPrms cqRingPrms;
} EnetUdma_UdmaChPrms;
 
typedef struct EnetUdma_UdmaFlowPrms_s
{
    uint8_t einfoPresent;
 
    uint8_t psInfoPresent;
 
    uint16_t sopOffset;
 
    uint16_t defaultRxCQ;
 
    uint8_t srcTagHi;
 
    uint8_t srcTagLo;
 
    uint8_t srcTagHiSel;
 
    uint8_t srcTagLoSel;
 
    uint8_t destTagHi;
 
    uint8_t destTagLo;
 
    uint8_t destTagHiSel;
 
    uint8_t destTagLoSel;
 
    uint8_t sizeThreshEn;
 
} EnetUdma_UdmaFlowPrms;
 
typedef struct EnetUdma_UdmaChTxPrms_s
{
    uint8_t filterEinfo;
 
    uint8_t filterPsWords;
 
    uint8_t addrType;
 
    uint8_t chanType;
 
    uint8_t busPriority;
 
    uint8_t busQos;
 
    uint8_t busOrderId;
 
    uint8_t dmaPriority;
 
    uint8_t txCredit;
 
    uint16_t fifoDepth;
} EnetUdma_UdmaChTxPrms;
 
typedef struct EnetUdma_AutoReclaimPrms_s
{
    bool enableFlag;
 
    EnetUdma_DmaDescQHandle hDmaDescPool;
 
    Udma_RingHandle hReclaimRing;
} EnetUdma_AutoReclaimPrms;
 
typedef struct EnetUdma_OpenRxFlowPrms_s
{
    Udma_DrvHandle hUdmaDrv;
 
    uint32_t chIdx;
 
    uint32_t startIdx;
 
    uint32_t flowIdx;
 
    EnetUdma_UdmaChPrms udmaChPrms;
 
    bool useGlobalEvt;
 
    EnetDma_PktNotifyCb notifyCb;
 
    EnetUdma_UdmaFlowPrms flowPrms;
 
    uint32_t numRxPkts;
 
    bool disableCacheOpsFlag;
 
    uint32_t rxFlowMtu;
 
    EnetUdma_AllocRingMemFxn ringMemAllocFxn;
 
    EnetUdma_FreeRingMemFxn ringMemFreeFxn;
 
    EnetUdma_AllocDmaDescFxn dmaDescAllocFxn;
 
    EnetUdma_FreeDmaDescFxn dmaDescFreeFxn;
 
    void *cbArg;
 
    bool useProxy;
 
    EnetUdma_AutoReclaimPrms autoReclaimPrms;
} EnetUdma_OpenRxFlowPrms;
 
typedef EnetUdma_OpenRxFlowPrms EnetDma_OpenRxChPrms;
 
typedef struct EnetUdma_OpenTxChPrms_s
{
    Udma_DrvHandle hUdmaDrv;
 
    uint32_t chNum;
 
    EnetUdma_UdmaChPrms udmaChPrms;
 
    EnetUdma_UdmaChTxPrms udmaTxChPrms;
 
    bool useGlobalEvt;
 
    EnetDma_PktNotifyCb notifyCb;
 
    uint32_t numTxPkts;
 
    bool disableCacheOpsFlag;
 
    EnetUdma_AllocRingMemFxn ringMemAllocFxn;
 
    EnetUdma_FreeRingMemFxn ringMemFreeFxn;
 
    EnetUdma_AllocDmaDescFxn dmaDescAllocFxn;
 
    EnetUdma_FreeDmaDescFxn dmaDescFreeFxn;
 
    void *cbArg;
 
    bool useProxy;
 
    EnetUdma_AutoReclaimPrms autoReclaimPrms;
} EnetUdma_OpenTxChPrms;
 
typedef struct EnetUdma_RxChInitPrms_s
{
    uint8_t dmaPriority;
} EnetUdma_RxChInitPrms;
 
typedef struct EnetUdma_Cfg_s
{
    Udma_DrvHandle hUdmaDrv;
 
    EnetUdma_RxChInitPrms rxChInitPrms;
} EnetUdma_Cfg;
 
typedef struct EnetUdma_DmaCfg_s
{
    Udma_DrvHandle hUdmaDrv;
} EnetDma_initCfg;
 
/* ========================================================================== */
/*                         Global Variables Declarations                      */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
void EnetUdma_initDataPathParams(EnetDma_initCfg *pDmaConfig);
EnetDma_Handle EnetUdma_initDataPath(Enet_Type enetType,
                                     uint32_t instId,
                                     const EnetDma_initCfg *pDmaInitCfg);
int32_t EnetUdma_deInitDataPath(EnetDma_Handle hEnetUdma);
 
int32_t EnetUdma_checkRxFlowSanity(EnetDma_RxChHandle hRxFlow,
                                   uint32_t margin);
 
int32_t EnetUdma_checkTxChSanity(EnetDma_TxChHandle hTxCh,
                                uint32_t margin);
 
Udma_RingHandle EnetUdma_getTxChFqHandle(EnetDma_TxChHandle hTxCh);
 
EnetUdma_DmaDescQHandle EnetUdma_getTxChDescPoolHandle(EnetDma_TxChHandle hTxCh);
 
Udma_RingHandle EnetUdma_getRxFlowFqHandle(EnetDma_RxChHandle hRxFlow);
 
EnetUdma_DmaDescQHandle EnetUdma_getRxFlowDescPoolHandle(EnetDma_RxChHandle hRxFlow);
 
/* ========================================================================== */
/*                        Deprecated Function Declarations                    */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                       Static Function Definitions                          */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif /* ENET_UDMA_H_ */