AM62x MCU+ SDK  10.01.00
cslr_dss.h
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31  *
32  * Name : cslr_dss.h
33 */
34 #ifndef CSLR_DSS_H_
35 #define CSLR_DSS_H_
36 
37 #ifdef __cplusplus
38 extern "C"
39 {
40 #endif
41 #include <drivers/hw_include/cslr.h>
42 #include <stdint.h>
43 
44 /**************************************************************************
45 * Hardware Region : COMMON Registers
46 **************************************************************************/
47 
48 
49 /**************************************************************************
50 * Register Overlay Structure
51 **************************************************************************/
52 
53 typedef struct {
54  volatile uint8_t Resv_4[4];
55  volatile uint32_t DSS_REVISION; /* DSS_REVISION */
56  volatile uint32_t DSS_SYSCONFIG; /* DSS_SYSCONFIG */
57  volatile uint8_t Resv_32[20];
58  volatile uint32_t DSS_SYSSTATUS; /* DSS_SYSSTATUS */
59  volatile uint32_t DISPC_IRQ_EOI; /* DISPC_IRQ_EOI */
60  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
61  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
62  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
63  volatile uint8_t Resv_64[12];
64  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
65  volatile uint32_t VID_IRQENABLE_0; /* VID_IRQENABLE_0 */
66  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
67  volatile uint8_t Resv_88[12];
68  volatile uint32_t VID_IRQSTATUS_0; /* VID_IRQSTATUS_0 */
69  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
70  volatile uint8_t Resv_112[16];
71  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
72  volatile uint32_t VP_IRQENABLE_1; /* VP_IRQENABLE_1 */
73  volatile uint8_t Resv_124[4];
74  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
75  volatile uint32_t VP_IRQSTATUS_1; /* VP_IRQSTATUS_1 */
76  volatile uint8_t Resv_144[12];
77  volatile uint32_t DISPC_GLOBAL_MFLAG_ATTRIBUTE; /* DISPC_GLOBAL_MFLAG_ATTRIBUTE */
78  volatile uint32_t DISPC_GLOBAL_OUTPUT_ENABLE; /* DISPC_GLOBAL_OUTPUT_ENABLE */
79  volatile uint32_t DISPC_GLOBAL_BUFFER; /* DISPC_GLOBAL_BUFFER */
80  volatile uint32_t DSS_CBA_CFG; /* DSS_CBA_CFG */
81  volatile uint32_t DISPC_DBG_CONTROL; /* DISPC_DBG_CONTROL */
82  volatile uint32_t DISPC_DBG_STATUS; /* DISPC_DBG_STATUS */
83  volatile uint32_t DISPC_CLKGATING_DISABLE; /* DISPC_CLKGATING_DISABLE */
84  volatile uint32_t DISPC_SECURE_DISABLE; /* DISPC_SECURE_DISABLE */
86 
87 
88 /**************************************************************************
89 * Register Macros
90 **************************************************************************/
91 
92 #define CSL_DSS_COMMON_DSS_REVISION (0x00000004U)
93 #define CSL_DSS_COMMON_DSS_SYSCONFIG (0x00000008U)
94 #define CSL_DSS_COMMON_DSS_SYSSTATUS (0x00000020U)
95 #define CSL_DSS_COMMON_DISPC_IRQ_EOI (0x00000024U)
96 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW (0x00000028U)
97 #define CSL_DSS_COMMON_DISPC_IRQSTATUS (0x0000002CU)
98 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET (0x00000030U)
99 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR (0x00000040U)
100 #define CSL_DSS_COMMON_VID_IRQENABLE_0 (0x00000044U)
101 #define CSL_DSS_COMMON_VID_IRQENABLE_1 (0x00000048U)
102 #define CSL_DSS_COMMON_VID_IRQSTATUS_0 (0x00000058U)
103 #define CSL_DSS_COMMON_VID_IRQSTATUS_1 (0x0000005CU)
104 #define CSL_DSS_COMMON_VP_IRQENABLE_0 (0x00000070U)
105 #define CSL_DSS_COMMON_VP_IRQENABLE_1 (0x00000074U)
106 #define CSL_DSS_COMMON_VP_IRQSTATUS_0 (0x0000007CU)
107 #define CSL_DSS_COMMON_VP_IRQSTATUS_1 (0x00000080U)
108 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE (0x00000090U)
109 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE (0x00000094U)
110 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER (0x00000098U)
111 #define CSL_DSS_COMMON_DSS_CBA_CFG (0x0000009CU)
112 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL (0x000000A0U)
113 #define CSL_DSS_COMMON_DISPC_DBG_STATUS (0x000000A4U)
114 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE (0x000000A8U)
115 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE (0x000000ACU)
116 
117 /**************************************************************************
118 * Field Definition Macros
119 **************************************************************************/
120 
121 
122 /* DSS_REVISION */
123 
124 #define CSL_DSS_COMMON_DSS_REVISION_REVMIN_MASK (0x0000003FU)
125 #define CSL_DSS_COMMON_DSS_REVISION_REVMIN_SHIFT (0x00000000U)
126 #define CSL_DSS_COMMON_DSS_REVISION_REVMIN_MAX (0x0000003FU)
127 
128 #define CSL_DSS_COMMON_DSS_REVISION_CUSTOM_MASK (0x000000C0U)
129 #define CSL_DSS_COMMON_DSS_REVISION_CUSTOM_SHIFT (0x00000006U)
130 #define CSL_DSS_COMMON_DSS_REVISION_CUSTOM_MAX (0x00000003U)
131 
132 #define CSL_DSS_COMMON_DSS_REVISION_REVMAJOR_MASK (0x00000700U)
133 #define CSL_DSS_COMMON_DSS_REVISION_REVMAJOR_SHIFT (0x00000008U)
134 #define CSL_DSS_COMMON_DSS_REVISION_REVMAJOR_MAX (0x00000007U)
135 
136 #define CSL_DSS_COMMON_DSS_REVISION_REVRTL_MASK (0x0000F800U)
137 #define CSL_DSS_COMMON_DSS_REVISION_REVRTL_SHIFT (0x0000000BU)
138 #define CSL_DSS_COMMON_DSS_REVISION_REVRTL_MAX (0x0000001FU)
139 
140 #define CSL_DSS_COMMON_DSS_REVISION_MODID_MASK (0xFFFF0000U)
141 #define CSL_DSS_COMMON_DSS_REVISION_MODID_SHIFT (0x00000010U)
142 #define CSL_DSS_COMMON_DSS_REVISION_MODID_MAX (0x0000FFFFU)
143 
144 /* DSS_SYSCONFIG */
145 
146 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_MASK (0x00000001U)
147 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_SHIFT (0x00000000U)
148 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_MAX (0x00000001U)
149 
150 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_VAL_CLKFREE (0x0U)
151 #define CSL_DSS_COMMON_DSS_SYSCONFIG_AUTOCLKGATING_VAL_CLKGATED (0x1U)
152 
153 #define CSL_DSS_COMMON_DSS_SYSCONFIG_SOFTRESET_MASK (0x00000002U)
154 #define CSL_DSS_COMMON_DSS_SYSCONFIG_SOFTRESET_SHIFT (0x00000001U)
155 #define CSL_DSS_COMMON_DSS_SYSCONFIG_SOFTRESET_MAX (0x00000001U)
156 
157 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED1_MASK (0x00000004U)
158 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED1_SHIFT (0x00000002U)
159 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED1_MAX (0x00000001U)
160 
161 #define CSL_DSS_COMMON_DSS_SYSCONFIG_IDLEMODE_MASK (0x00000018U)
162 #define CSL_DSS_COMMON_DSS_SYSCONFIG_IDLEMODE_SHIFT (0x00000003U)
163 #define CSL_DSS_COMMON_DSS_SYSCONFIG_IDLEMODE_MAX (0x00000003U)
164 
165 #define CSL_DSS_COMMON_DSS_SYSCONFIG_WARMRESET_MASK (0x00000020U)
166 #define CSL_DSS_COMMON_DSS_SYSCONFIG_WARMRESET_SHIFT (0x00000005U)
167 #define CSL_DSS_COMMON_DSS_SYSCONFIG_WARMRESET_MAX (0x00000001U)
168 
169 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED2_MASK (0x000000C0U)
170 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED2_SHIFT (0x00000006U)
171 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED2_MAX (0x00000003U)
172 
173 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED3_MASK (0x00003F00U)
174 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED3_SHIFT (0x00000008U)
175 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED3_MAX (0x0000003FU)
176 
177 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED4_MASK (0xFFFFC000U)
178 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED4_SHIFT (0x0000000EU)
179 #define CSL_DSS_COMMON_DSS_SYSCONFIG_RESERVED4_MAX (0x0003FFFFU)
180 
181 /* DSS_SYSSTATUS */
182 
183 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_MASK (0x00000001U)
184 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_SHIFT (0x00000000U)
185 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_MAX (0x00000001U)
186 
187 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_VAL_RSTONGOING (0x0U)
188 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_FUNC_RESETDONE_VAL_RSTCOMP (0x1U)
189 
190 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_MASK (0x00000006U)
191 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_SHIFT (0x00000001U)
192 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_MAX (0x00000003U)
193 
194 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_VAL_RSTONGOING (0x0U)
195 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_VP_RESETDONE_VAL_RSTCOMP (0x1U)
196 
197 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED1_MASK (0x00000010U)
198 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED1_SHIFT (0x00000004U)
199 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED1_MAX (0x00000001U)
200 
201 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_MASK (0x00000020U)
202 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_SHIFT (0x00000005U)
203 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_MAX (0x00000001U)
204 
205 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_VAL_RSTONGOING (0x0U)
206 #define CSL_DSS_COMMON_DSS_SYSSTATUS_OLDI_RESETDONE_VAL_RSTCOMP (0x1U)
207 
208 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED2_MASK (0x00000100U)
209 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED2_SHIFT (0x00000008U)
210 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED2_MAX (0x00000001U)
211 
212 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_MASK (0x00000200U)
213 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_SHIFT (0x00000009U)
214 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_MAX (0x00000001U)
215 
216 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_VAL_NOTIDLE (0x0U)
217 #define CSL_DSS_COMMON_DSS_SYSSTATUS_DISPC_IDLE_STATUS_VAL_IDLE (0x1U)
218 
219 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED_MASK (0xFFFFFC00U)
220 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED_SHIFT (0x0000000AU)
221 #define CSL_DSS_COMMON_DSS_SYSSTATUS_RESERVED_MAX (0x003FFFFFU)
222 
223 /* DISPC_IRQ_EOI */
224 
225 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_MASK (0x00000001U)
226 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_SHIFT (0x00000000U)
227 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_MAX (0x00000001U)
228 
229 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_VAL_NOACTION (0x0U)
230 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_EOI_VAL_EOI (0x1U)
231 
232 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_RESERVED_MASK (0xFFFFFFFEU)
233 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_RESERVED_SHIFT (0x00000001U)
234 #define CSL_DSS_COMMON_DISPC_IRQ_EOI_RESERVED_MAX (0x7FFFFFFFU)
235 
236 /* DISPC_IRQSTATUS_RAW */
237 
238 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x00000003U)
239 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
240 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x00000003U)
241 
242 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
243 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
244 
245 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x00000030U)
246 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
247 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x00000003U)
248 
249 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
250 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
251 
252 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFF8000U)
253 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x0000000FU)
254 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x0001FFFFU)
255 
256 /* DISPC_IRQSTATUS */
257 
258 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_MASK (0x00000003U)
259 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
260 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_MAX (0x00000003U)
261 
262 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
263 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
264 
265 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_MASK (0x00000030U)
266 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
267 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_MAX (0x00000003U)
268 
269 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
270 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
271 
272 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFF8000U)
273 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RESERVED_SHIFT (0x0000000FU)
274 #define CSL_DSS_COMMON_DISPC_IRQSTATUS_RESERVED_MAX (0x0001FFFFU)
275 
276 /* DISPC_IRQENABLE_SET */
277 
278 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x00000003U)
279 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
280 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x00000003U)
281 
282 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
283 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
284 
285 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x00000030U)
286 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
287 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x00000003U)
288 
289 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
290 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
291 
292 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFF8000U)
293 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x0000000FU)
294 #define CSL_DSS_COMMON_DISPC_IRQENABLE_SET_RESERVED_MAX (0x0001FFFFU)
295 
296 /* DISPC_IRQENABLE_CLR */
297 
298 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x00000003U)
299 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
300 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x00000003U)
301 
302 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
303 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
304 
305 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x00000030U)
306 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
307 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x00000003U)
308 
309 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
310 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
311 
312 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFF8000U)
313 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x0000000FU)
314 #define CSL_DSS_COMMON_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x0001FFFFU)
315 
316 /* VID_IRQENABLE_0 */
317 
318 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
319 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
320 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
321 
322 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
323 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
324 
325 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK (0x00000002U)
326 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDENDWINDOW_EN_SHIFT (0x00000001U)
327 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDENDWINDOW_EN_MAX (0x00000001U)
328 
329 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
330 #define CSL_DSS_COMMON_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
331 
332 #define CSL_DSS_COMMON_VID_IRQENABLE_0_SAFETYREGION_EN_MASK (0x00000004U)
333 #define CSL_DSS_COMMON_VID_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000002U)
334 #define CSL_DSS_COMMON_VID_IRQENABLE_0_SAFETYREGION_EN_MAX (0x00000001U)
335 
336 #define CSL_DSS_COMMON_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
337 #define CSL_DSS_COMMON_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
338 
339 #define CSL_DSS_COMMON_VID_IRQENABLE_0_RESERVED_MASK (0xFFFFFFF8U)
340 #define CSL_DSS_COMMON_VID_IRQENABLE_0_RESERVED_SHIFT (0x00000003U)
341 #define CSL_DSS_COMMON_VID_IRQENABLE_0_RESERVED_MAX (0x1FFFFFFFU)
342 
343 /* VID_IRQENABLE_1 */
344 
345 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
346 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
347 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
348 
349 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
350 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
351 
352 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
353 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
354 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
355 
356 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
357 #define CSL_DSS_COMMON_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
358 
359 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
360 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
361 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
362 
363 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
364 #define CSL_DSS_COMMON_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
365 
366 #define CSL_DSS_COMMON_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFF8U)
367 #define CSL_DSS_COMMON_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000003U)
368 #define CSL_DSS_COMMON_VID_IRQENABLE_1_RESERVED_MAX (0x1FFFFFFFU)
369 
370 /* VID_IRQSTATUS_0 */
371 
372 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
373 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
374 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
375 
376 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
377 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
378 
379 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MASK (0x00000002U)
380 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
381 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MAX (0x00000001U)
382 
383 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
384 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
385 
386 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x00000004U)
387 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000002U)
388 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x00000001U)
389 
390 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
391 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
392 
393 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_RESERVED_MASK (0xFFFFFFF8U)
394 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_RESERVED_SHIFT (0x00000003U)
395 #define CSL_DSS_COMMON_VID_IRQSTATUS_0_RESERVED_MAX (0x1FFFFFFFU)
396 
397 /* VID_IRQSTATUS_1 */
398 
399 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
400 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
401 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
402 
403 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
404 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
405 
406 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
407 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
408 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
409 
410 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
411 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
412 
413 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
414 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
415 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
416 
417 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
418 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
419 
420 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFF8U)
421 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000003U)
422 #define CSL_DSS_COMMON_VID_IRQSTATUS_1_RESERVED_MAX (0x1FFFFFFFU)
423 
424 /* VP_IRQENABLE_0 */
425 
426 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
427 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
428 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
429 
430 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
431 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
432 
433 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
434 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
435 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
436 
437 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
438 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
439 
440 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
441 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
442 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
443 
444 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
445 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
446 
447 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
448 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
449 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
450 
451 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
452 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
453 
454 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
455 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
456 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
457 
458 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
459 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
460 
461 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
462 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
463 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
464 
465 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
466 #define CSL_DSS_COMMON_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
467 
468 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
469 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
470 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
471 
472 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
473 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
474 
475 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
476 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
477 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
478 
479 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
480 #define CSL_DSS_COMMON_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
481 
482 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
483 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
484 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
485 
486 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
487 #define CSL_DSS_COMMON_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
488 
489 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
490 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
491 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
492 
493 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
494 #define CSL_DSS_COMMON_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
495 
496 #define CSL_DSS_COMMON_VP_IRQENABLE_0_RESERVED_MASK (0xFFFFE000U)
497 #define CSL_DSS_COMMON_VP_IRQENABLE_0_RESERVED_SHIFT (0x0000000DU)
498 #define CSL_DSS_COMMON_VP_IRQENABLE_0_RESERVED_MAX (0x0007FFFFU)
499 
500 /* VP_IRQENABLE_1 */
501 
502 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPFRAMEDONE_EN_MASK (0x00000001U)
503 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPFRAMEDONE_EN_SHIFT (0x00000000U)
504 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPFRAMEDONE_EN_MAX (0x00000001U)
505 
506 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
507 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
508 
509 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_EN_MASK (0x00000002U)
510 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_EN_SHIFT (0x00000001U)
511 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_EN_MAX (0x00000001U)
512 
513 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_EN_VAL_MASKED (0x0U)
514 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_EN_VAL_GENINT (0x1U)
515 
516 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MASK (0x00000004U)
517 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
518 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MAX (0x00000001U)
519 
520 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
521 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
522 
523 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
524 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
525 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
526 
527 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
528 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
529 
530 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNCLOST_EN_MASK (0x00000010U)
531 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNCLOST_EN_SHIFT (0x00000004U)
532 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNCLOST_EN_MAX (0x00000001U)
533 
534 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_MASKED (0x0U)
535 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_GENINT (0x1U)
536 
537 #define CSL_DSS_COMMON_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
538 #define CSL_DSS_COMMON_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
539 #define CSL_DSS_COMMON_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
540 
541 #define CSL_DSS_COMMON_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
542 #define CSL_DSS_COMMON_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
543 
544 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SAFETYREGION_EN_MASK (0x000003C0U)
545 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000006U)
546 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SAFETYREGION_EN_MAX (0x0000000FU)
547 
548 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
549 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
550 
551 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MASK (0x00000400U)
552 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
553 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MAX (0x00000001U)
554 
555 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
556 #define CSL_DSS_COMMON_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
557 
558 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNC_EN_MASK (0x00000800U)
559 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNC_EN_SHIFT (0x0000000BU)
560 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNC_EN_MAX (0x00000001U)
561 
562 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNC_EN_VAL_MASKED (0x0U)
563 #define CSL_DSS_COMMON_VP_IRQENABLE_1_VPSYNC_EN_VAL_GENINT (0x1U)
564 
565 #define CSL_DSS_COMMON_VP_IRQENABLE_1_DUMMY_EN_MASK (0x00001000U)
566 #define CSL_DSS_COMMON_VP_IRQENABLE_1_DUMMY_EN_SHIFT (0x0000000CU)
567 #define CSL_DSS_COMMON_VP_IRQENABLE_1_DUMMY_EN_MAX (0x00000001U)
568 
569 #define CSL_DSS_COMMON_VP_IRQENABLE_1_DUMMY_EN_VAL_MASKED (0x0U)
570 #define CSL_DSS_COMMON_VP_IRQENABLE_1_DUMMY_EN_VAL_GENINT (0x1U)
571 
572 #define CSL_DSS_COMMON_VP_IRQENABLE_1_RESERVED_MASK (0xFFFFE000U)
573 #define CSL_DSS_COMMON_VP_IRQENABLE_1_RESERVED_SHIFT (0x0000000DU)
574 #define CSL_DSS_COMMON_VP_IRQENABLE_1_RESERVED_MAX (0x0007FFFFU)
575 
576 /* VP_IRQSTATUS_0 */
577 
578 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
579 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
580 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
581 
582 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
583 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
584 
585 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
586 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
587 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
588 
589 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
590 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
591 
592 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
593 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
594 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
595 
596 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
597 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
598 
599 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
600 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
601 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
602 
603 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
604 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
605 
606 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
607 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
608 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
609 
610 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
611 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
612 
613 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
614 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
615 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
616 
617 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
618 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
619 
620 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
621 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
622 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
623 
624 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
625 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
626 
627 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
628 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
629 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
630 
631 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
632 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
633 
634 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
635 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
636 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
637 
638 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
639 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
640 
641 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
642 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
643 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
644 
645 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
646 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
647 
648 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFFE000U)
649 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_RESERVED_SHIFT (0x0000000DU)
650 #define CSL_DSS_COMMON_VP_IRQSTATUS_0_RESERVED_MAX (0x0007FFFFU)
651 
652 /* VP_IRQSTATUS_1 */
653 
654 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MASK (0x00000001U)
655 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
656 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MAX (0x00000001U)
657 
658 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
659 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
660 
661 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_IRQ_MASK (0x00000002U)
662 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_IRQ_SHIFT (0x00000001U)
663 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_IRQ_MAX (0x00000001U)
664 
665 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
666 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_PEND (0x1U)
667 
668 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
669 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
670 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
671 
672 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
673 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
674 
675 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
676 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
677 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
678 
679 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
680 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
681 
682 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MASK (0x00000010U)
683 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
684 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MAX (0x00000001U)
685 
686 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
687 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
688 
689 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
690 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
691 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
692 
693 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
694 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
695 
696 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x000003C0U)
697 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000006U)
698 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x0000000FU)
699 
700 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
701 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
702 
703 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
704 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
705 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
706 
707 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
708 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
709 
710 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNC_IRQ_MASK (0x00000800U)
711 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNC_IRQ_SHIFT (0x0000000BU)
712 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNC_IRQ_MAX (0x00000001U)
713 
714 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_NOPEND (0x0U)
715 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_PEND (0x1U)
716 
717 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_DUMMY_IRQ_MASK (0x00001000U)
718 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_DUMMY_IRQ_SHIFT (0x0000000CU)
719 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_DUMMY_IRQ_MAX (0x00000001U)
720 
721 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_NOPEND (0x0U)
722 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_PEND (0x1U)
723 
724 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_RESERVED_MASK (0xFFFFE000U)
725 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_RESERVED_SHIFT (0x0000000DU)
726 #define CSL_DSS_COMMON_VP_IRQSTATUS_1_RESERVED_MAX (0x0007FFFFU)
727 
728 /* DISPC_GLOBAL_MFLAG_ATTRIBUTE */
729 
730 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK (0x00000003U)
731 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_SHIFT (0x00000000U)
732 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MAX (0x00000003U)
733 
734 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGDIS (0x0U)
735 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGFORCE (0x1U)
736 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGEN (0x2U)
737 
738 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_MASK (0x0000003CU)
739 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_SHIFT (0x00000002U)
740 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED1_MAX (0x0000000FU)
741 
742 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK (0x00000040U)
743 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_SHIFT (0x00000006U)
744 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MAX (0x00000001U)
745 
746 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGNORMALSTARTMODE (0x0U)
747 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGFORCESTARTMODE (0x1U)
748 
749 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_MASK (0x00000180U)
750 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_SHIFT (0x00000007U)
751 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED2_MAX (0x00000003U)
752 
753 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_MASK (0xFFFFFE00U)
754 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_SHIFT (0x00000009U)
755 #define CSL_DSS_COMMON_DISPC_GLOBAL_MFLAG_ATTRIBUTE_RESERVED_MAX (0x007FFFFFU)
756 
757 /* DISPC_GLOBAL_OUTPUT_ENABLE */
758 
759 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_MASK (0x00000007U)
760 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_SHIFT (0x00000000U)
761 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_MAX (0x00000007U)
762 
763 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_VAL_DISABLE (0x0U)
764 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_ENABLE_VAL_ENABLE (0x1U)
765 
766 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED3_MASK (0x00000008U)
767 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED3_SHIFT (0x00000003U)
768 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED3_MAX (0x00000001U)
769 
770 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_MASK (0x0000FFF0U)
771 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_SHIFT (0x00000004U)
772 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED1_MAX (0x00000FFFU)
773 
774 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_MASK (0x00070000U)
775 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_SHIFT (0x00000010U)
776 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_MAX (0x00000007U)
777 
778 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_VAL_HFUISR (0x0U)
779 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_VP_GO_VAL_UFPSR (0x1U)
780 
781 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED4_MASK (0x00080000U)
782 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED4_SHIFT (0x00000013U)
783 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED4_MAX (0x00000001U)
784 
785 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_MASK (0xFFF00000U)
786 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_SHIFT (0x00000014U)
787 #define CSL_DSS_COMMON_DISPC_GLOBAL_OUTPUT_ENABLE_RESERVED2_MAX (0x00000FFFU)
788 
789 /* DISPC_GLOBAL_BUFFER */
790 
791 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_MASK (0x00000007U)
792 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_SHIFT (0x00000000U)
793 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_MAX (0x00000007U)
794 
795 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_VAL_VID (0x0U)
796 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VID_BUFFER_VAL_VIDL1 (0x1U)
797 
798 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_MASK (0x00000038U)
799 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_SHIFT (0x00000003U)
800 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_MAX (0x00000007U)
801 
802 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_VID (0x0U)
803 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_VIDL1_BUFFER_VAL_VIDL1 (0x1U)
804 
805 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED1_MASK (0x000001C0U)
806 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED1_SHIFT (0x00000006U)
807 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED1_MAX (0x00000007U)
808 
809 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED2_MASK (0x00000E00U)
810 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED2_SHIFT (0x00000009U)
811 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED2_MAX (0x00000007U)
812 
813 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED3_MASK (0x00007000U)
814 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED3_SHIFT (0x0000000CU)
815 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED3_MAX (0x00000007U)
816 
817 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED_MASK (0x7FFF8000U)
818 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED_SHIFT (0x0000000FU)
819 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_RESERVED_MAX (0x0000FFFFU)
820 
821 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_MASK (0x80000000U)
822 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_SHIFT (0x0000001FU)
823 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_MAX (0x00000001U)
824 
825 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_VAL_INDIVIDUALPIPE (0x0U)
826 #define CSL_DSS_COMMON_DISPC_GLOBAL_BUFFER_BUFFERFILLING_VAL_ALLPIPES (0x1U)
827 
828 /* DSS_CBA_CFG */
829 
830 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_LO_MASK (0x00000007U)
831 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_LO_SHIFT (0x00000000U)
832 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_LO_MAX (0x00000007U)
833 
834 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_HI_MASK (0x00000038U)
835 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_HI_SHIFT (0x00000003U)
836 #define CSL_DSS_COMMON_DSS_CBA_CFG_PRI_HI_MAX (0x00000007U)
837 
838 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED1_MASK (0x000001C0U)
839 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED1_SHIFT (0x00000006U)
840 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED1_MAX (0x00000007U)
841 
842 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED_MASK (0xFFFFFE00U)
843 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED_SHIFT (0x00000009U)
844 #define CSL_DSS_COMMON_DSS_CBA_CFG_RESERVED_MAX (0x007FFFFFU)
845 
846 /* DISPC_DBG_CONTROL */
847 
848 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_MASK (0x00000001U)
849 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_SHIFT (0x00000000U)
850 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_MAX (0x00000001U)
851 
852 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_VAL_DBGDIS (0x0U)
853 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGEN_VAL_DBGEN (0x1U)
854 
855 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_MASK (0x000001FEU)
856 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_SHIFT (0x00000001U)
857 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_MAX (0x000000FFU)
858 
859 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VIDSEL (0x0U)
860 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VIDL1SEL (0x8U)
861 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR1SEL (0x11U)
862 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_OVR2SEL (0x12U)
863 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP1SEL (0x13U)
864 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_VP2SEL (0x15U)
865 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_DBGMUXSEL_VAL_MISCSEL (0x17U)
866 
867 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_RESERVED_MASK (0xFFFFFE00U)
868 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_RESERVED_SHIFT (0x00000009U)
869 #define CSL_DSS_COMMON_DISPC_DBG_CONTROL_RESERVED_MAX (0x007FFFFFU)
870 
871 /* DISPC_DBG_STATUS */
872 
873 #define CSL_DSS_COMMON_DISPC_DBG_STATUS_DBGOUT_MASK (0xFFFFFFFFU)
874 #define CSL_DSS_COMMON_DISPC_DBG_STATUS_DBGOUT_SHIFT (0x00000000U)
875 #define CSL_DSS_COMMON_DISPC_DBG_STATUS_DBGOUT_MAX (0xFFFFFFFFU)
876 
877 /* DISPC_CLKGATING_DISABLE */
878 
879 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_MASK (0x00000001U)
880 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_SHIFT (0x00000000U)
881 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_MAX (0x00000001U)
882 
883 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_VAL_CLKGATINGEN (0x0U)
884 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_DMA_VAL_CLKGATINGDIS (0x1U)
885 
886 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED1_MASK (0x00000006U)
887 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED1_SHIFT (0x00000001U)
888 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED1_MAX (0x00000003U)
889 
890 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_MASK (0x00000018U)
891 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_SHIFT (0x00000003U)
892 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_MAX (0x00000003U)
893 
894 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_VAL_CLKGATINGEN (0x0U)
895 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VID_VAL_CLKGATINGDIS (0x1U)
896 
897 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED2_MASK (0x00000F80U)
898 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED2_SHIFT (0x00000007U)
899 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED2_MAX (0x0000001FU)
900 
901 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_MASK (0x00001000U)
902 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_SHIFT (0x0000000CU)
903 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_MAX (0x00000001U)
904 
905 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_VAL_CLKGATINGEN (0x0U)
906 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED3_VAL_CLKGATINGDIS (0x1U)
907 
908 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_MASK (0x0000C000U)
909 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_SHIFT (0x0000000EU)
910 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_MAX (0x00000003U)
911 
912 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_VAL_CLKGATINGEN (0x0U)
913 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_OVR_VAL_CLKGATINGDIS (0x1U)
914 
915 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED4_MASK (0x00020000U)
916 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED4_SHIFT (0x00000011U)
917 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED4_MAX (0x00000001U)
918 
919 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP_MASK (0x000C0000U)
920 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP_SHIFT (0x00000012U)
921 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP_MAX (0x00000003U)
922 
923 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP_VAL_CLKGATINGEN (0x0U)
924 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_VP_VAL_CLKGATINGDIS (0x1U)
925 
926 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED5_MASK (0x00200000U)
927 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED5_SHIFT (0x00000015U)
928 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED5_MAX (0x00000001U)
929 
930 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED_MASK (0xFFC00000U)
931 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED_SHIFT (0x00000016U)
932 #define CSL_DSS_COMMON_DISPC_CLKGATING_DISABLE_RESERVED_MAX (0x000003FFU)
933 
934 /* DISPC_SECURE_DISABLE */
935 
936 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_MASK (0x00000001U)
937 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_SHIFT (0x00000000U)
938 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_MAX (0x00000001U)
939 
940 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_VAL_SECUREEN (0x0U)
941 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_SECURE_DISABLE_VAL_SECUREDIS (0x1U)
942 
943 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_RESERVED_MASK (0xFFFFFFFEU)
944 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_RESERVED_SHIFT (0x00000001U)
945 #define CSL_DSS_COMMON_DISPC_SECURE_DISABLE_RESERVED_MAX (0x7FFFFFFFU)
946 
947 /**************************************************************************
948 * Hardware Region : COMMON1 Registers
949 **************************************************************************/
950 
951 
952 /**************************************************************************
953 * Register Overlay Structure
954 **************************************************************************/
955 
956 typedef struct {
957  volatile uint8_t Resv_36[36];
958  volatile uint32_t DISPC_IRQ_EOI; /* DISPC_IRQ_EOI */
959  volatile uint32_t DISPC_IRQSTATUS_RAW; /* DISPC_IRQSTATUS_RAW */
960  volatile uint32_t DISPC_IRQSTATUS; /* DISPC_IRQSTATUS */
961  volatile uint32_t DISPC_IRQENABLE_SET; /* DISPC_IRQENABLE_SET */
962  volatile uint8_t Resv_64[12];
963  volatile uint32_t DISPC_IRQENABLE_CLR; /* DISPC_IRQENABLE_CLR */
964  volatile uint32_t VID_IRQENABLE_0; /* VID_IRQENABLE_0 */
965  volatile uint32_t VID_IRQENABLE_1; /* VID_IRQENABLE_1 */
966  volatile uint8_t Resv_84[8];
967  volatile uint32_t DISPC_SECURE; /* DISPC_SECURE */
968  volatile uint32_t VID_IRQSTATUS_0; /* VID_IRQSTATUS_0 */
969  volatile uint32_t VID_IRQSTATUS_1; /* VID_IRQSTATUS_1 */
970  volatile uint8_t Resv_112[16];
971  volatile uint32_t VP_IRQENABLE_0; /* VP_IRQENABLE_0 */
972  volatile uint32_t VP_IRQENABLE_1; /* VP_IRQENABLE_1 */
973  volatile uint8_t Resv_124[4];
974  volatile uint32_t VP_IRQSTATUS_0; /* VP_IRQSTATUS_0 */
975  volatile uint32_t VP_IRQSTATUS_1; /* VP_IRQSTATUS_1 */
977 
978 
979 /**************************************************************************
980 * Register Macros
981 **************************************************************************/
982 
983 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI (0x00000024U)
984 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW (0x00000028U)
985 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS (0x0000002CU)
986 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET (0x00000030U)
987 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR (0x00000040U)
988 #define CSL_DSS_COMMON1_VID_IRQENABLE_0 (0x00000044U)
989 #define CSL_DSS_COMMON1_VID_IRQENABLE_1 (0x00000048U)
990 #define CSL_DSS_COMMON1_DISPC_SECURE (0x00000054U)
991 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0 (0x00000058U)
992 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1 (0x0000005CU)
993 #define CSL_DSS_COMMON1_VP_IRQENABLE_0 (0x00000070U)
994 #define CSL_DSS_COMMON1_VP_IRQENABLE_1 (0x00000074U)
995 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0 (0x0000007CU)
996 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1 (0x00000080U)
997 
998 /**************************************************************************
999 * Field Definition Macros
1000 **************************************************************************/
1001 
1002 
1003 /* DISPC_IRQ_EOI */
1004 
1005 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_MASK (0x00000001U)
1006 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_SHIFT (0x00000000U)
1007 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_MAX (0x00000001U)
1008 
1009 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_VAL_NOACTION (0x0U)
1010 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_EOI_VAL_EOI (0x1U)
1011 
1012 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_RESERVED_MASK (0xFFFFFFFEU)
1013 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_RESERVED_SHIFT (0x00000001U)
1014 #define CSL_DSS_COMMON1_DISPC_IRQ_EOI_RESERVED_MAX (0x7FFFFFFFU)
1015 
1016 /* DISPC_IRQSTATUS_RAW */
1017 
1018 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_MASK (0x00000003U)
1019 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_SHIFT (0x00000000U)
1020 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_MAX (0x00000003U)
1021 
1022 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_NOACTION (0x0U)
1023 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VP_IRQ_VAL_SET_EVENT (0x1U)
1024 
1025 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_MASK (0x00000030U)
1026 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_SHIFT (0x00000004U)
1027 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_MAX (0x00000003U)
1028 
1029 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_NOACTION (0x0U)
1030 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_VID_IRQ_VAL_SET_EVENT (0x1U)
1031 
1032 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_RESERVED_MASK (0xFFFF8000U)
1033 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_RESERVED_SHIFT (0x0000000FU)
1034 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RAW_RESERVED_MAX (0x0001FFFFU)
1035 
1036 /* DISPC_IRQSTATUS */
1037 
1038 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_MASK (0x00000003U)
1039 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_SHIFT (0x00000000U)
1040 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_MAX (0x00000003U)
1041 
1042 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_VAL_NOACTION (0x0U)
1043 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VP_IRQ_VAL_CLEAR (0x1U)
1044 
1045 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_MASK (0x00000030U)
1046 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_SHIFT (0x00000004U)
1047 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_MAX (0x00000003U)
1048 
1049 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_VAL_NOACTION (0x0U)
1050 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_VID_IRQ_VAL_CLEAR (0x1U)
1051 
1052 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RESERVED_MASK (0xFFFF8000U)
1053 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RESERVED_SHIFT (0x0000000FU)
1054 #define CSL_DSS_COMMON1_DISPC_IRQSTATUS_RESERVED_MAX (0x0001FFFFU)
1055 
1056 /* DISPC_IRQENABLE_SET */
1057 
1058 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_MASK (0x00000003U)
1059 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_SHIFT (0x00000000U)
1060 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_MAX (0x00000003U)
1061 
1062 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_NOACTION (0x0U)
1063 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VP_IRQ_VAL_ENABLE (0x1U)
1064 
1065 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_MASK (0x00000030U)
1066 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_SHIFT (0x00000004U)
1067 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_MAX (0x00000003U)
1068 
1069 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_NOACTION (0x0U)
1070 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_SET_VID_IRQ_VAL_ENABLE (0x1U)
1071 
1072 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_RESERVED_MASK (0xFFFF8000U)
1073 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_RESERVED_SHIFT (0x0000000FU)
1074 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_SET_RESERVED_MAX (0x0001FFFFU)
1075 
1076 /* DISPC_IRQENABLE_CLR */
1077 
1078 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MASK (0x00000003U)
1079 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_SHIFT (0x00000000U)
1080 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_MAX (0x00000003U)
1081 
1082 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_NOACTION (0x0U)
1083 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VP_IRQ_VAL_CLEAR (0x1U)
1084 
1085 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MASK (0x00000030U)
1086 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_SHIFT (0x00000004U)
1087 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_MAX (0x00000003U)
1088 
1089 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_NOACTION (0x0U)
1090 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_CLR_VID_IRQ_VAL_CLEAR (0x1U)
1091 
1092 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_RESERVED_MASK (0xFFFF8000U)
1093 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_RESERVED_SHIFT (0x0000000FU)
1094 #define CSL_DSS_COMMON1_DISPC_IRQENABLE_CLR_RESERVED_MAX (0x0001FFFFU)
1095 
1096 /* VID_IRQENABLE_0 */
1097 
1098 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
1099 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
1100 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
1101 
1102 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
1103 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
1104 
1105 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK (0x00000002U)
1106 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDENDWINDOW_EN_SHIFT (0x00000001U)
1107 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDENDWINDOW_EN_MAX (0x00000001U)
1108 
1109 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
1110 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
1111 
1112 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_SAFETYREGION_EN_MASK (0x00000004U)
1113 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000002U)
1114 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_SAFETYREGION_EN_MAX (0x00000001U)
1115 
1116 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
1117 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
1118 
1119 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_RESERVED_MASK (0xFFFFFFF8U)
1120 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_RESERVED_SHIFT (0x00000003U)
1121 #define CSL_DSS_COMMON1_VID_IRQENABLE_0_RESERVED_MAX (0x1FFFFFFFU)
1122 
1123 /* VID_IRQENABLE_1 */
1124 
1125 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MASK (0x00000001U)
1126 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_SHIFT (0x00000000U)
1127 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_MAX (0x00000001U)
1128 
1129 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_MASKED (0x0U)
1130 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDBUFFERUNDERFLOW_EN_VAL_GENINT (0x1U)
1131 
1132 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_MASK (0x00000002U)
1133 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_SHIFT (0x00000001U)
1134 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_MAX (0x00000001U)
1135 
1136 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_MASKED (0x0U)
1137 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_VIDENDWINDOW_EN_VAL_GENINT (0x1U)
1138 
1139 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_MASK (0x00000004U)
1140 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000002U)
1141 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_MAX (0x00000001U)
1142 
1143 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
1144 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
1145 
1146 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_RESERVED_MASK (0xFFFFFFF8U)
1147 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_RESERVED_SHIFT (0x00000003U)
1148 #define CSL_DSS_COMMON1_VID_IRQENABLE_1_RESERVED_MAX (0x1FFFFFFFU)
1149 
1150 /* DISPC_SECURE */
1151 
1152 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_MASK (0x00000003U)
1153 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_SHIFT (0x00000000U)
1154 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_MAX (0x00000003U)
1155 
1156 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_VAL_SECUREDIS (0x0U)
1157 #define CSL_DSS_COMMON1_DISPC_SECURE_VP_SECURE_VAL_SECUREEN (0x1U)
1158 
1159 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED1_MASK (0x00000008U)
1160 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED1_SHIFT (0x00000003U)
1161 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED1_MAX (0x00000001U)
1162 
1163 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_MASK (0x00000030U)
1164 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_SHIFT (0x00000004U)
1165 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_MAX (0x00000003U)
1166 
1167 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_VAL_SECUREDIS (0x0U)
1168 #define CSL_DSS_COMMON1_DISPC_SECURE_VID_SECURE_VAL_SECUREEN (0x1U)
1169 
1170 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED2_MASK (0x00001F00U)
1171 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED2_SHIFT (0x00000008U)
1172 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED2_MAX (0x0000001FU)
1173 
1174 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED3_MASK (0x00002000U)
1175 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED3_SHIFT (0x0000000DU)
1176 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED3_MAX (0x00000001U)
1177 
1178 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_MASK (0x00018000U)
1179 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_SHIFT (0x0000000FU)
1180 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_MAX (0x00000003U)
1181 
1182 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_VAL_SECUREDIS (0x0U)
1183 #define CSL_DSS_COMMON1_DISPC_SECURE_OVR_SECURE_VAL_SECUREEN (0x1U)
1184 
1185 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED5_MASK (0x00040000U)
1186 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED5_SHIFT (0x00000012U)
1187 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED5_MAX (0x00000001U)
1188 
1189 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED_MASK (0xFFF80000U)
1190 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED_SHIFT (0x00000013U)
1191 #define CSL_DSS_COMMON1_DISPC_SECURE_RESERVED_MAX (0x00001FFFU)
1192 
1193 /* VID_IRQSTATUS_0 */
1194 
1195 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
1196 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
1197 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
1198 
1199 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
1200 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
1201 
1202 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MASK (0x00000002U)
1203 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
1204 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_MAX (0x00000001U)
1205 
1206 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
1207 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
1208 
1209 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x00000004U)
1210 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000002U)
1211 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x00000001U)
1212 
1213 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1214 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1215 
1216 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_RESERVED_MASK (0xFFFFFFF8U)
1217 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_RESERVED_SHIFT (0x00000003U)
1218 #define CSL_DSS_COMMON1_VID_IRQSTATUS_0_RESERVED_MAX (0x1FFFFFFFU)
1219 
1220 /* VID_IRQSTATUS_1 */
1221 
1222 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MASK (0x00000001U)
1223 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_SHIFT (0x00000000U)
1224 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_MAX (0x00000001U)
1225 
1226 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_NOPEND (0x0U)
1227 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDBUFFERUNDERFLOW_IRQ_VAL_PEND (0x1U)
1228 
1229 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MASK (0x00000002U)
1230 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_SHIFT (0x00000001U)
1231 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_MAX (0x00000001U)
1232 
1233 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_NOPEND (0x0U)
1234 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_VIDENDWINDOW_IRQ_VAL_PEND (0x1U)
1235 
1236 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x00000004U)
1237 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000002U)
1238 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x00000001U)
1239 
1240 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1241 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1242 
1243 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_RESERVED_MASK (0xFFFFFFF8U)
1244 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_RESERVED_SHIFT (0x00000003U)
1245 #define CSL_DSS_COMMON1_VID_IRQSTATUS_1_RESERVED_MAX (0x1FFFFFFFU)
1246 
1247 /* VP_IRQENABLE_0 */
1248 
1249 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK (0x00000001U)
1250 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_SHIFT (0x00000000U)
1251 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_MAX (0x00000001U)
1252 
1253 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
1254 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
1255 
1256 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_MASK (0x00000002U)
1257 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_SHIFT (0x00000001U)
1258 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_MAX (0x00000001U)
1259 
1260 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_VAL_MASKED (0x0U)
1261 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_EN_VAL_GENINT (0x1U)
1262 
1263 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK (0x00000004U)
1264 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
1265 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MAX (0x00000001U)
1266 
1267 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
1268 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
1269 
1270 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
1271 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
1272 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
1273 
1274 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
1275 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
1276 
1277 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK (0x00000010U)
1278 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_SHIFT (0x00000004U)
1279 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_MAX (0x00000001U)
1280 
1281 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_MASKED (0x0U)
1282 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNCLOST_EN_VAL_GENINT (0x1U)
1283 
1284 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
1285 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
1286 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
1287 
1288 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
1289 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
1290 
1291 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_MASK (0x000003C0U)
1292 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_SHIFT (0x00000006U)
1293 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_MAX (0x0000000FU)
1294 
1295 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_MASKED (0x0U)
1296 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SAFETYREGION_EN_VAL_GENINT (0x1U)
1297 
1298 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK (0x00000400U)
1299 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
1300 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MAX (0x00000001U)
1301 
1302 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
1303 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
1304 
1305 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_MASK (0x00000800U)
1306 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_SHIFT (0x0000000BU)
1307 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_MAX (0x00000001U)
1308 
1309 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_VAL_MASKED (0x0U)
1310 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_VPSYNC_EN_VAL_GENINT (0x1U)
1311 
1312 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_MASK (0x00001000U)
1313 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_SHIFT (0x0000000CU)
1314 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_MAX (0x00000001U)
1315 
1316 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_VAL_MASKED (0x0U)
1317 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_DUMMY_EN_VAL_GENINT (0x1U)
1318 
1319 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_RESERVED_MASK (0xFFFFE000U)
1320 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_RESERVED_SHIFT (0x0000000DU)
1321 #define CSL_DSS_COMMON1_VP_IRQENABLE_0_RESERVED_MAX (0x0007FFFFU)
1322 
1323 /* VP_IRQENABLE_1 */
1324 
1325 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPFRAMEDONE_EN_MASK (0x00000001U)
1326 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPFRAMEDONE_EN_SHIFT (0x00000000U)
1327 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPFRAMEDONE_EN_MAX (0x00000001U)
1328 
1329 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_MASKED (0x0U)
1330 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPFRAMEDONE_EN_VAL_GENINT (0x1U)
1331 
1332 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_EN_MASK (0x00000002U)
1333 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_EN_SHIFT (0x00000001U)
1334 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_EN_MAX (0x00000001U)
1335 
1336 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_EN_VAL_MASKED (0x0U)
1337 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_EN_VAL_GENINT (0x1U)
1338 
1339 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MASK (0x00000004U)
1340 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_SHIFT (0x00000002U)
1341 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_MAX (0x00000001U)
1342 
1343 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_MASKED (0x0U)
1344 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPVSYNC_ODD_EN_VAL_GENINT (0x1U)
1345 
1346 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MASK (0x00000008U)
1347 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_SHIFT (0x00000003U)
1348 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_MAX (0x00000001U)
1349 
1350 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_MASKED (0x0U)
1351 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPPROGRAMMEDLINENUMBER_EN_VAL_GENINT (0x1U)
1352 
1353 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNCLOST_EN_MASK (0x00000010U)
1354 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNCLOST_EN_SHIFT (0x00000004U)
1355 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNCLOST_EN_MAX (0x00000001U)
1356 
1357 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_MASKED (0x0U)
1358 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNCLOST_EN_VAL_GENINT (0x1U)
1359 
1360 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MASK (0x00000020U)
1361 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_SHIFT (0x00000005U)
1362 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_MAX (0x00000001U)
1363 
1364 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_MASKED (0x0U)
1365 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_ACBIASCOUNTSTATUS_EN_VAL_GENINT (0x1U)
1366 
1367 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SAFETYREGION_EN_MASK (0x000003C0U)
1368 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SAFETYREGION_EN_SHIFT (0x00000006U)
1369 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SAFETYREGION_EN_MAX (0x0000000FU)
1370 
1371 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_MASKED (0x0U)
1372 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SAFETYREGION_EN_VAL_GENINT (0x1U)
1373 
1374 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MASK (0x00000400U)
1375 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_SHIFT (0x0000000AU)
1376 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_MAX (0x00000001U)
1377 
1378 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_MASKED (0x0U)
1379 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_SECURITYVIOLATION_EN_VAL_GENINT (0x1U)
1380 
1381 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNC_EN_MASK (0x00000800U)
1382 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNC_EN_SHIFT (0x0000000BU)
1383 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNC_EN_MAX (0x00000001U)
1384 
1385 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNC_EN_VAL_MASKED (0x0U)
1386 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_VPSYNC_EN_VAL_GENINT (0x1U)
1387 
1388 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_DUMMY_EN_MASK (0x00001000U)
1389 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_DUMMY_EN_SHIFT (0x0000000CU)
1390 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_DUMMY_EN_MAX (0x00000001U)
1391 
1392 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_DUMMY_EN_VAL_MASKED (0x0U)
1393 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_DUMMY_EN_VAL_GENINT (0x1U)
1394 
1395 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_RESERVED_MASK (0xFFFFE000U)
1396 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_RESERVED_SHIFT (0x0000000DU)
1397 #define CSL_DSS_COMMON1_VP_IRQENABLE_1_RESERVED_MAX (0x0007FFFFU)
1398 
1399 /* VP_IRQSTATUS_0 */
1400 
1401 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1402 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1403 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1404 
1405 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1406 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1407 
1408 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_MASK (0x00000002U)
1409 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_SHIFT (0x00000001U)
1410 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_MAX (0x00000001U)
1411 
1412 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1413 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_IRQ_VAL_PEND (0x1U)
1414 
1415 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1416 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1417 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1418 
1419 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1420 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1421 
1422 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1423 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1424 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1425 
1426 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1427 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1428 
1429 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MASK (0x00000010U)
1430 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1431 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_MAX (0x00000001U)
1432 
1433 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1434 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1435 
1436 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1437 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1438 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1439 
1440 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1441 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1442 
1443 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MASK (0x000003C0U)
1444 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1445 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_MAX (0x0000000FU)
1446 
1447 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1448 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1449 
1450 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1451 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1452 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1453 
1454 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1455 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1456 
1457 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_MASK (0x00000800U)
1458 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_SHIFT (0x0000000BU)
1459 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_MAX (0x00000001U)
1460 
1461 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1462 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_VPSYNC_IRQ_VAL_PEND (0x1U)
1463 
1464 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_MASK (0x00001000U)
1465 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_SHIFT (0x0000000CU)
1466 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_MAX (0x00000001U)
1467 
1468 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_NOPEND (0x0U)
1469 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_DUMMY_IRQ_VAL_PEND (0x1U)
1470 
1471 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_RESERVED_MASK (0xFFFFE000U)
1472 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_RESERVED_SHIFT (0x0000000DU)
1473 #define CSL_DSS_COMMON1_VP_IRQSTATUS_0_RESERVED_MAX (0x0007FFFFU)
1474 
1475 /* VP_IRQSTATUS_1 */
1476 
1477 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MASK (0x00000001U)
1478 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_SHIFT (0x00000000U)
1479 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_MAX (0x00000001U)
1480 
1481 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_NOPEND (0x0U)
1482 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPFRAMEDONE_IRQ_VAL_PEND (0x1U)
1483 
1484 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_IRQ_MASK (0x00000002U)
1485 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_IRQ_SHIFT (0x00000001U)
1486 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_IRQ_MAX (0x00000001U)
1487 
1488 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_NOPEND (0x0U)
1489 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_IRQ_VAL_PEND (0x1U)
1490 
1491 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MASK (0x00000004U)
1492 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_SHIFT (0x00000002U)
1493 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_MAX (0x00000001U)
1494 
1495 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_NOPEND (0x0U)
1496 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPVSYNC_ODD_IRQ_VAL_PEND (0x1U)
1497 
1498 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MASK (0x00000008U)
1499 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_SHIFT (0x00000003U)
1500 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_MAX (0x00000001U)
1501 
1502 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_NOPEND (0x0U)
1503 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPPROGRAMMEDLINENUMBER_IRQ_VAL_PEND (0x1U)
1504 
1505 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MASK (0x00000010U)
1506 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_SHIFT (0x00000004U)
1507 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_MAX (0x00000001U)
1508 
1509 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_NOPEND (0x0U)
1510 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNCLOST_IRQ_VAL_PEND (0x1U)
1511 
1512 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MASK (0x00000020U)
1513 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_SHIFT (0x00000005U)
1514 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_MAX (0x00000001U)
1515 
1516 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_NOPEND (0x0U)
1517 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_ACBIASCOUNTSTATUS_IRQ_VAL_PEND (0x1U)
1518 
1519 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MASK (0x000003C0U)
1520 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_SHIFT (0x00000006U)
1521 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_MAX (0x0000000FU)
1522 
1523 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_NOPEND (0x0U)
1524 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SAFETYREGION_IRQ_VAL_PEND (0x1U)
1525 
1526 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MASK (0x00000400U)
1527 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_SHIFT (0x0000000AU)
1528 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_MAX (0x00000001U)
1529 
1530 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_NOPEND (0x0U)
1531 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_SECURITYVIOLATION_IRQ_VAL_PEND (0x1U)
1532 
1533 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNC_IRQ_MASK (0x00000800U)
1534 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNC_IRQ_SHIFT (0x0000000BU)
1535 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNC_IRQ_MAX (0x00000001U)
1536 
1537 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_NOPEND (0x0U)
1538 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_VPSYNC_IRQ_VAL_PEND (0x1U)
1539 
1540 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_DUMMY_IRQ_MASK (0x00001000U)
1541 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_DUMMY_IRQ_SHIFT (0x0000000CU)
1542 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_DUMMY_IRQ_MAX (0x00000001U)
1543 
1544 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_NOPEND (0x0U)
1545 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_DUMMY_IRQ_VAL_PEND (0x1U)
1546 
1547 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_RESERVED_MASK (0xFFFFE000U)
1548 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_RESERVED_SHIFT (0x0000000DU)
1549 #define CSL_DSS_COMMON1_VP_IRQSTATUS_1_RESERVED_MAX (0x0007FFFFU)
1550 
1551 /**************************************************************************
1552 * Hardware Region : VIDL1 Registers
1553 **************************************************************************/
1554 
1555 
1556 /**************************************************************************
1557 * Register Overlay Structure
1558 **************************************************************************/
1559 
1560 typedef struct {
1561  volatile uint8_t Resv_32[32];
1562  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
1563  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
1564  volatile uint32_t BA_0; /* BA_0 */
1565  volatile uint32_t BA_1; /* BA_1 */
1566  volatile uint32_t BA_UV_0; /* BA_UV_0 */
1567  volatile uint32_t BA_UV_1; /* BA_UV_1 */
1568  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
1569  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
1570  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
1571  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
1572  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
1573  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
1574  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
1575  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
1576  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
1577  volatile uint8_t Resv_508[416];
1578  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
1579  volatile uint8_t Resv_520[8];
1580  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
1581  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
1582  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
1583  volatile uint8_t Resv_536[4];
1584  volatile uint32_t PRELOAD; /* PRELOAD */
1585  volatile uint32_t ROW_INC; /* ROW_INC */
1586  volatile uint8_t Resv_556[12];
1587  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
1588  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
1589  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
1590  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
1591  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
1592  volatile uint8_t Resv_584[8];
1593  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
1594  volatile uint8_t Resv_608[20];
1595  volatile uint32_t CLUT_0; /* CLUT_0 */
1596  volatile uint32_t CLUT_1; /* CLUT_1 */
1597  volatile uint32_t CLUT_2; /* CLUT_2 */
1598  volatile uint32_t CLUT_3; /* CLUT_3 */
1599  volatile uint32_t CLUT_4; /* CLUT_4 */
1600  volatile uint32_t CLUT_5; /* CLUT_5 */
1601  volatile uint32_t CLUT_6; /* CLUT_6 */
1602  volatile uint32_t CLUT_7; /* CLUT_7 */
1603  volatile uint32_t CLUT_8; /* CLUT_8 */
1604  volatile uint32_t CLUT_9; /* CLUT_9 */
1605  volatile uint32_t CLUT_10; /* CLUT_10 */
1606  volatile uint32_t CLUT_11; /* CLUT_11 */
1607  volatile uint32_t CLUT_12; /* CLUT_12 */
1608  volatile uint32_t CLUT_13; /* CLUT_13 */
1609  volatile uint32_t CLUT_14; /* CLUT_14 */
1610  volatile uint32_t CLUT_15; /* CLUT_15 */
1611  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
1612  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
1613  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
1614  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
1615  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
1616  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
1617  volatile uint32_t LUMAKEY; /* LUMAKEY */
1619 
1620 
1621 /**************************************************************************
1622 * Register Macros
1623 **************************************************************************/
1624 
1625 #define CSL_DSS_VIDL1_ATTRIBUTES (0x00000020U)
1626 #define CSL_DSS_VIDL1_ATTRIBUTES2 (0x00000024U)
1627 #define CSL_DSS_VIDL1_BA_0 (0x00000028U)
1628 #define CSL_DSS_VIDL1_BA_1 (0x0000002CU)
1629 #define CSL_DSS_VIDL1_BA_UV_0 (0x00000030U)
1630 #define CSL_DSS_VIDL1_BA_UV_1 (0x00000034U)
1631 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS (0x00000038U)
1632 #define CSL_DSS_VIDL1_BUF_THRESHOLD (0x0000003CU)
1633 #define CSL_DSS_VIDL1_CSC_COEF0 (0x00000040U)
1634 #define CSL_DSS_VIDL1_CSC_COEF1 (0x00000044U)
1635 #define CSL_DSS_VIDL1_CSC_COEF2 (0x00000048U)
1636 #define CSL_DSS_VIDL1_CSC_COEF3 (0x0000004CU)
1637 #define CSL_DSS_VIDL1_CSC_COEF4 (0x00000050U)
1638 #define CSL_DSS_VIDL1_CSC_COEF5 (0x00000054U)
1639 #define CSL_DSS_VIDL1_CSC_COEF6 (0x00000058U)
1640 #define CSL_DSS_VIDL1_GLOBAL_ALPHA (0x000001FCU)
1641 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD (0x00000208U)
1642 #define CSL_DSS_VIDL1_PICTURE_SIZE (0x0000020CU)
1643 #define CSL_DSS_VIDL1_PIXEL_INC (0x00000210U)
1644 #define CSL_DSS_VIDL1_PRELOAD (0x00000218U)
1645 #define CSL_DSS_VIDL1_ROW_INC (0x0000021CU)
1646 #define CSL_DSS_VIDL1_BA_EXT_0 (0x0000022CU)
1647 #define CSL_DSS_VIDL1_BA_EXT_1 (0x00000230U)
1648 #define CSL_DSS_VIDL1_BA_UV_EXT_0 (0x00000234U)
1649 #define CSL_DSS_VIDL1_BA_UV_EXT_1 (0x00000238U)
1650 #define CSL_DSS_VIDL1_CSC_COEF7 (0x0000023CU)
1651 #define CSL_DSS_VIDL1_ROW_INC_UV (0x00000248U)
1652 #define CSL_DSS_VIDL1_CLUT_0 (0x00000260U)
1653 #define CSL_DSS_VIDL1_CLUT_1 (0x00000264U)
1654 #define CSL_DSS_VIDL1_CLUT_2 (0x00000268U)
1655 #define CSL_DSS_VIDL1_CLUT_3 (0x0000026CU)
1656 #define CSL_DSS_VIDL1_CLUT_4 (0x00000270U)
1657 #define CSL_DSS_VIDL1_CLUT_5 (0x00000274U)
1658 #define CSL_DSS_VIDL1_CLUT_6 (0x00000278U)
1659 #define CSL_DSS_VIDL1_CLUT_7 (0x0000027CU)
1660 #define CSL_DSS_VIDL1_CLUT_8 (0x00000280U)
1661 #define CSL_DSS_VIDL1_CLUT_9 (0x00000284U)
1662 #define CSL_DSS_VIDL1_CLUT_10 (0x00000288U)
1663 #define CSL_DSS_VIDL1_CLUT_11 (0x0000028CU)
1664 #define CSL_DSS_VIDL1_CLUT_12 (0x00000290U)
1665 #define CSL_DSS_VIDL1_CLUT_13 (0x00000294U)
1666 #define CSL_DSS_VIDL1_CLUT_14 (0x00000298U)
1667 #define CSL_DSS_VIDL1_CLUT_15 (0x0000029CU)
1668 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES (0x000002A0U)
1669 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE (0x000002A4U)
1670 #define CSL_DSS_VIDL1_SAFETY_POSITION (0x000002A8U)
1671 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE (0x000002ACU)
1672 #define CSL_DSS_VIDL1_SAFETY_SIZE (0x000002B0U)
1673 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED (0x000002B4U)
1674 #define CSL_DSS_VIDL1_LUMAKEY (0x000002B8U)
1675 
1676 /**************************************************************************
1677 * Field Definition Macros
1678 **************************************************************************/
1679 
1680 
1681 /* ATTRIBUTES */
1682 
1683 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_MASK (0x00000001U)
1684 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
1685 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_MAX (0x00000001U)
1686 
1687 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
1688 #define CSL_DSS_VIDL1_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
1689 
1690 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
1691 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
1692 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
1693 
1694 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
1695 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
1696 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
1697 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
1698 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
1699 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
1700 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
1701 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
1702 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
1703 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
1704 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
1705 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
1706 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
1707 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
1708 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
1709 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
1710 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
1711 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
1712 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
1713 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
1714 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
1715 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
1716 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
1717 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
1718 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
1719 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
1720 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
1721 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
1722 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
1723 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
1724 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
1725 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
1726 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
1727 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
1728 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
1729 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
1730 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
1731 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
1732 #define CSL_DSS_VIDL1_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
1733 
1734 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_MASK (0x00000180U)
1735 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_SHIFT (0x00000007U)
1736 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED8_MAX (0x00000003U)
1737 
1738 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
1739 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
1740 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
1741 
1742 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
1743 #define CSL_DSS_VIDL1_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
1744 
1745 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
1746 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
1747 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
1748 
1749 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
1750 #define CSL_DSS_VIDL1_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
1751 
1752 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
1753 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
1754 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
1755 
1756 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
1757 #define CSL_DSS_VIDL1_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
1758 
1759 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_MASK (0x00001000U)
1760 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
1761 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_MAX (0x00000001U)
1762 
1763 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
1764 #define CSL_DSS_VIDL1_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
1765 
1766 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED1_MASK (0x00002000U)
1767 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED1_SHIFT (0x0000000DU)
1768 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED1_MAX (0x00000001U)
1769 
1770 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
1771 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
1772 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
1773 
1774 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
1775 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
1776 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
1777 
1778 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
1779 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
1780 
1781 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
1782 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
1783 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
1784 
1785 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
1786 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
1787 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
1788 
1789 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
1790 #define CSL_DSS_VIDL1_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
1791 
1792 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
1793 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
1794 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
1795 
1796 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_MASK (0x00200000U)
1797 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_SHIFT (0x00000015U)
1798 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED3_MAX (0x00000001U)
1799 
1800 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
1801 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
1802 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
1803 
1804 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
1805 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
1806 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
1807 
1808 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
1809 #define CSL_DSS_VIDL1_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
1810 
1811 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
1812 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
1813 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
1814 
1815 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
1816 #define CSL_DSS_VIDL1_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
1817 
1818 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
1819 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
1820 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
1821 
1822 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
1823 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
1824 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
1825 
1826 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
1827 #define CSL_DSS_VIDL1_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
1828 
1829 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED4_MASK (0x20000000U)
1830 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED4_SHIFT (0x0000001DU)
1831 #define CSL_DSS_VIDL1_ATTRIBUTES_RESERVED4_MAX (0x00000001U)
1832 
1833 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
1834 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
1835 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
1836 
1837 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
1838 #define CSL_DSS_VIDL1_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
1839 
1840 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
1841 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
1842 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
1843 
1844 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
1845 #define CSL_DSS_VIDL1_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
1846 
1847 /* ATTRIBUTES2 */
1848 
1849 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
1850 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
1851 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
1852 
1853 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
1854 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
1855 
1856 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
1857 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
1858 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
1859 
1860 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
1861 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
1862 #define CSL_DSS_VIDL1_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
1863 
1864 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
1865 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
1866 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
1867 
1868 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
1869 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
1870 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
1871 
1872 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
1873 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
1874 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
1875 
1876 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
1877 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
1878 
1879 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
1880 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
1881 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
1882 
1883 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
1884 #define CSL_DSS_VIDL1_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
1885 
1886 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED_MASK (0x03FFF800U)
1887 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED_SHIFT (0x0000000BU)
1888 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED_MAX (0x00007FFFU)
1889 
1890 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
1891 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
1892 #define CSL_DSS_VIDL1_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
1893 
1894 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
1895 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
1896 #define CSL_DSS_VIDL1_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
1897 
1898 /* BA_0 */
1899 
1900 #define CSL_DSS_VIDL1_BA_0_BA_MASK (0xFFFFFFFFU)
1901 #define CSL_DSS_VIDL1_BA_0_BA_SHIFT (0x00000000U)
1902 #define CSL_DSS_VIDL1_BA_0_BA_MAX (0xFFFFFFFFU)
1903 
1904 /* BA_1 */
1905 
1906 #define CSL_DSS_VIDL1_BA_1_BA_MASK (0xFFFFFFFFU)
1907 #define CSL_DSS_VIDL1_BA_1_BA_SHIFT (0x00000000U)
1908 #define CSL_DSS_VIDL1_BA_1_BA_MAX (0xFFFFFFFFU)
1909 
1910 /* BA_UV_0 */
1911 
1912 #define CSL_DSS_VIDL1_BA_UV_0_BA_MASK (0xFFFFFFFFU)
1913 #define CSL_DSS_VIDL1_BA_UV_0_BA_SHIFT (0x00000000U)
1914 #define CSL_DSS_VIDL1_BA_UV_0_BA_MAX (0xFFFFFFFFU)
1915 
1916 /* BA_UV_1 */
1917 
1918 #define CSL_DSS_VIDL1_BA_UV_1_BA_MASK (0xFFFFFFFFU)
1919 #define CSL_DSS_VIDL1_BA_UV_1_BA_SHIFT (0x00000000U)
1920 #define CSL_DSS_VIDL1_BA_UV_1_BA_MAX (0xFFFFFFFFU)
1921 
1922 /* BUF_SIZE_STATUS */
1923 
1924 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
1925 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
1926 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
1927 
1928 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
1929 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
1930 #define CSL_DSS_VIDL1_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
1931 
1932 /* BUF_THRESHOLD */
1933 
1934 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
1935 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
1936 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
1937 
1938 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
1939 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
1940 #define CSL_DSS_VIDL1_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
1941 
1942 /* CSC_COEF0 */
1943 
1944 #define CSL_DSS_VIDL1_CSC_COEF0_C00_MASK (0x000007FFU)
1945 #define CSL_DSS_VIDL1_CSC_COEF0_C00_SHIFT (0x00000000U)
1946 #define CSL_DSS_VIDL1_CSC_COEF0_C00_MAX (0x000007FFU)
1947 
1948 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
1949 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
1950 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
1951 
1952 #define CSL_DSS_VIDL1_CSC_COEF0_C01_MASK (0x07FF0000U)
1953 #define CSL_DSS_VIDL1_CSC_COEF0_C01_SHIFT (0x00000010U)
1954 #define CSL_DSS_VIDL1_CSC_COEF0_C01_MAX (0x000007FFU)
1955 
1956 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
1957 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
1958 #define CSL_DSS_VIDL1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
1959 
1960 /* CSC_COEF1 */
1961 
1962 #define CSL_DSS_VIDL1_CSC_COEF1_C02_MASK (0x000007FFU)
1963 #define CSL_DSS_VIDL1_CSC_COEF1_C02_SHIFT (0x00000000U)
1964 #define CSL_DSS_VIDL1_CSC_COEF1_C02_MAX (0x000007FFU)
1965 
1966 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
1967 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
1968 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
1969 
1970 #define CSL_DSS_VIDL1_CSC_COEF1_C10_MASK (0x07FF0000U)
1971 #define CSL_DSS_VIDL1_CSC_COEF1_C10_SHIFT (0x00000010U)
1972 #define CSL_DSS_VIDL1_CSC_COEF1_C10_MAX (0x000007FFU)
1973 
1974 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
1975 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
1976 #define CSL_DSS_VIDL1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
1977 
1978 /* CSC_COEF2 */
1979 
1980 #define CSL_DSS_VIDL1_CSC_COEF2_C11_MASK (0x000007FFU)
1981 #define CSL_DSS_VIDL1_CSC_COEF2_C11_SHIFT (0x00000000U)
1982 #define CSL_DSS_VIDL1_CSC_COEF2_C11_MAX (0x000007FFU)
1983 
1984 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
1985 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
1986 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
1987 
1988 #define CSL_DSS_VIDL1_CSC_COEF2_C12_MASK (0x07FF0000U)
1989 #define CSL_DSS_VIDL1_CSC_COEF2_C12_SHIFT (0x00000010U)
1990 #define CSL_DSS_VIDL1_CSC_COEF2_C12_MAX (0x000007FFU)
1991 
1992 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
1993 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
1994 #define CSL_DSS_VIDL1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
1995 
1996 /* CSC_COEF3 */
1997 
1998 #define CSL_DSS_VIDL1_CSC_COEF3_C20_MASK (0x000007FFU)
1999 #define CSL_DSS_VIDL1_CSC_COEF3_C20_SHIFT (0x00000000U)
2000 #define CSL_DSS_VIDL1_CSC_COEF3_C20_MAX (0x000007FFU)
2001 
2002 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
2003 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
2004 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
2005 
2006 #define CSL_DSS_VIDL1_CSC_COEF3_C21_MASK (0x07FF0000U)
2007 #define CSL_DSS_VIDL1_CSC_COEF3_C21_SHIFT (0x00000010U)
2008 #define CSL_DSS_VIDL1_CSC_COEF3_C21_MAX (0x000007FFU)
2009 
2010 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
2011 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
2012 #define CSL_DSS_VIDL1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
2013 
2014 /* CSC_COEF4 */
2015 
2016 #define CSL_DSS_VIDL1_CSC_COEF4_C22_MASK (0x000007FFU)
2017 #define CSL_DSS_VIDL1_CSC_COEF4_C22_SHIFT (0x00000000U)
2018 #define CSL_DSS_VIDL1_CSC_COEF4_C22_MAX (0x000007FFU)
2019 
2020 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
2021 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
2022 #define CSL_DSS_VIDL1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
2023 
2024 /* CSC_COEF5 */
2025 
2026 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_MASK (0x00000007U)
2027 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
2028 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED_MAX (0x00000007U)
2029 
2030 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
2031 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
2032 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
2033 
2034 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
2035 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
2036 #define CSL_DSS_VIDL1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
2037 
2038 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
2039 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
2040 #define CSL_DSS_VIDL1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
2041 
2042 /* CSC_COEF6 */
2043 
2044 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_MASK (0x00000007U)
2045 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
2046 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED_MAX (0x00000007U)
2047 
2048 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
2049 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
2050 #define CSL_DSS_VIDL1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
2051 
2052 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
2053 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
2054 #define CSL_DSS_VIDL1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
2055 
2056 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
2057 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
2058 #define CSL_DSS_VIDL1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
2059 
2060 /* GLOBAL_ALPHA */
2061 
2062 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
2063 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
2064 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
2065 
2066 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
2067 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
2068 #define CSL_DSS_VIDL1_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
2069 
2070 /* MFLAG_THRESHOLD */
2071 
2072 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
2073 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
2074 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
2075 
2076 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
2077 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
2078 #define CSL_DSS_VIDL1_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
2079 
2080 /* PICTURE_SIZE */
2081 
2082 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_MASK (0x00000FFFU)
2083 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
2084 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEX_MAX (0x00000FFFU)
2085 
2086 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED1_MASK (0x0000F000U)
2087 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED1_SHIFT (0x0000000CU)
2088 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED1_MAX (0x0000000FU)
2089 
2090 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_MASK (0x0FFF0000U)
2091 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
2092 #define CSL_DSS_VIDL1_PICTURE_SIZE_MEMSIZEY_MAX (0x00000FFFU)
2093 
2094 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED_MASK (0xF0000000U)
2095 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED_SHIFT (0x0000001CU)
2096 #define CSL_DSS_VIDL1_PICTURE_SIZE_RESERVED_MAX (0x0000000FU)
2097 
2098 /* PIXEL_INC */
2099 
2100 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
2101 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
2102 #define CSL_DSS_VIDL1_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
2103 
2104 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
2105 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
2106 #define CSL_DSS_VIDL1_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
2107 
2108 /* PRELOAD */
2109 
2110 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_MASK (0x00000FFFU)
2111 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_SHIFT (0x00000000U)
2112 #define CSL_DSS_VIDL1_PRELOAD_PRELOAD_MAX (0x00000FFFU)
2113 
2114 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
2115 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
2116 #define CSL_DSS_VIDL1_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
2117 
2118 /* ROW_INC */
2119 
2120 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
2121 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_SHIFT (0x00000000U)
2122 #define CSL_DSS_VIDL1_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
2123 
2124 /* BA_EXT_0 */
2125 
2126 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
2127 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
2128 #define CSL_DSS_VIDL1_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
2129 
2130 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
2131 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
2132 #define CSL_DSS_VIDL1_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
2133 
2134 /* BA_EXT_1 */
2135 
2136 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
2137 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
2138 #define CSL_DSS_VIDL1_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
2139 
2140 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
2141 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
2142 #define CSL_DSS_VIDL1_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
2143 
2144 /* BA_UV_EXT_0 */
2145 
2146 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
2147 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
2148 #define CSL_DSS_VIDL1_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
2149 
2150 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
2151 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
2152 #define CSL_DSS_VIDL1_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
2153 
2154 /* BA_UV_EXT_1 */
2155 
2156 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
2157 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
2158 #define CSL_DSS_VIDL1_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
2159 
2160 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
2161 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
2162 #define CSL_DSS_VIDL1_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
2163 
2164 /* CSC_COEF7 */
2165 
2166 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_MASK (0x00000007U)
2167 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
2168 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED_MAX (0x00000007U)
2169 
2170 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
2171 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
2172 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
2173 
2174 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
2175 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
2176 #define CSL_DSS_VIDL1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
2177 
2178 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
2179 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
2180 #define CSL_DSS_VIDL1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
2181 
2182 /* ROW_INC_UV */
2183 
2184 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
2185 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
2186 #define CSL_DSS_VIDL1_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
2187 
2188 /* CLUT_0 */
2189 
2190 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_MASK (0x000000FFU)
2191 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_SHIFT (0x00000000U)
2192 #define CSL_DSS_VIDL1_CLUT_0_VALUE_B_MAX (0x000000FFU)
2193 
2194 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_MASK (0x0000FF00U)
2195 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_SHIFT (0x00000008U)
2196 #define CSL_DSS_VIDL1_CLUT_0_VALUE_G_MAX (0x000000FFU)
2197 
2198 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_MASK (0x00FF0000U)
2199 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_SHIFT (0x00000010U)
2200 #define CSL_DSS_VIDL1_CLUT_0_VALUE_R_MAX (0x000000FFU)
2201 
2202 #define CSL_DSS_VIDL1_CLUT_0_INDEX_MASK (0xFF000000U)
2203 #define CSL_DSS_VIDL1_CLUT_0_INDEX_SHIFT (0x00000018U)
2204 #define CSL_DSS_VIDL1_CLUT_0_INDEX_MAX (0x000000FFU)
2205 
2206 /* CLUT_1 */
2207 
2208 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_MASK (0x000000FFU)
2209 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_SHIFT (0x00000000U)
2210 #define CSL_DSS_VIDL1_CLUT_1_VALUE_B_MAX (0x000000FFU)
2211 
2212 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_MASK (0x0000FF00U)
2213 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_SHIFT (0x00000008U)
2214 #define CSL_DSS_VIDL1_CLUT_1_VALUE_G_MAX (0x000000FFU)
2215 
2216 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_MASK (0x00FF0000U)
2217 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_SHIFT (0x00000010U)
2218 #define CSL_DSS_VIDL1_CLUT_1_VALUE_R_MAX (0x000000FFU)
2219 
2220 #define CSL_DSS_VIDL1_CLUT_1_INDEX_MASK (0xFF000000U)
2221 #define CSL_DSS_VIDL1_CLUT_1_INDEX_SHIFT (0x00000018U)
2222 #define CSL_DSS_VIDL1_CLUT_1_INDEX_MAX (0x000000FFU)
2223 
2224 /* CLUT_2 */
2225 
2226 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_MASK (0x000000FFU)
2227 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_SHIFT (0x00000000U)
2228 #define CSL_DSS_VIDL1_CLUT_2_VALUE_B_MAX (0x000000FFU)
2229 
2230 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_MASK (0x0000FF00U)
2231 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_SHIFT (0x00000008U)
2232 #define CSL_DSS_VIDL1_CLUT_2_VALUE_G_MAX (0x000000FFU)
2233 
2234 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_MASK (0x00FF0000U)
2235 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_SHIFT (0x00000010U)
2236 #define CSL_DSS_VIDL1_CLUT_2_VALUE_R_MAX (0x000000FFU)
2237 
2238 #define CSL_DSS_VIDL1_CLUT_2_INDEX_MASK (0xFF000000U)
2239 #define CSL_DSS_VIDL1_CLUT_2_INDEX_SHIFT (0x00000018U)
2240 #define CSL_DSS_VIDL1_CLUT_2_INDEX_MAX (0x000000FFU)
2241 
2242 /* CLUT_3 */
2243 
2244 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_MASK (0x000000FFU)
2245 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_SHIFT (0x00000000U)
2246 #define CSL_DSS_VIDL1_CLUT_3_VALUE_B_MAX (0x000000FFU)
2247 
2248 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_MASK (0x0000FF00U)
2249 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_SHIFT (0x00000008U)
2250 #define CSL_DSS_VIDL1_CLUT_3_VALUE_G_MAX (0x000000FFU)
2251 
2252 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_MASK (0x00FF0000U)
2253 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_SHIFT (0x00000010U)
2254 #define CSL_DSS_VIDL1_CLUT_3_VALUE_R_MAX (0x000000FFU)
2255 
2256 #define CSL_DSS_VIDL1_CLUT_3_INDEX_MASK (0xFF000000U)
2257 #define CSL_DSS_VIDL1_CLUT_3_INDEX_SHIFT (0x00000018U)
2258 #define CSL_DSS_VIDL1_CLUT_3_INDEX_MAX (0x000000FFU)
2259 
2260 /* CLUT_4 */
2261 
2262 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_MASK (0x000000FFU)
2263 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_SHIFT (0x00000000U)
2264 #define CSL_DSS_VIDL1_CLUT_4_VALUE_B_MAX (0x000000FFU)
2265 
2266 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_MASK (0x0000FF00U)
2267 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_SHIFT (0x00000008U)
2268 #define CSL_DSS_VIDL1_CLUT_4_VALUE_G_MAX (0x000000FFU)
2269 
2270 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_MASK (0x00FF0000U)
2271 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_SHIFT (0x00000010U)
2272 #define CSL_DSS_VIDL1_CLUT_4_VALUE_R_MAX (0x000000FFU)
2273 
2274 #define CSL_DSS_VIDL1_CLUT_4_INDEX_MASK (0xFF000000U)
2275 #define CSL_DSS_VIDL1_CLUT_4_INDEX_SHIFT (0x00000018U)
2276 #define CSL_DSS_VIDL1_CLUT_4_INDEX_MAX (0x000000FFU)
2277 
2278 /* CLUT_5 */
2279 
2280 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_MASK (0x000000FFU)
2281 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_SHIFT (0x00000000U)
2282 #define CSL_DSS_VIDL1_CLUT_5_VALUE_B_MAX (0x000000FFU)
2283 
2284 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_MASK (0x0000FF00U)
2285 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_SHIFT (0x00000008U)
2286 #define CSL_DSS_VIDL1_CLUT_5_VALUE_G_MAX (0x000000FFU)
2287 
2288 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_MASK (0x00FF0000U)
2289 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_SHIFT (0x00000010U)
2290 #define CSL_DSS_VIDL1_CLUT_5_VALUE_R_MAX (0x000000FFU)
2291 
2292 #define CSL_DSS_VIDL1_CLUT_5_INDEX_MASK (0xFF000000U)
2293 #define CSL_DSS_VIDL1_CLUT_5_INDEX_SHIFT (0x00000018U)
2294 #define CSL_DSS_VIDL1_CLUT_5_INDEX_MAX (0x000000FFU)
2295 
2296 /* CLUT_6 */
2297 
2298 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_MASK (0x000000FFU)
2299 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_SHIFT (0x00000000U)
2300 #define CSL_DSS_VIDL1_CLUT_6_VALUE_B_MAX (0x000000FFU)
2301 
2302 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_MASK (0x0000FF00U)
2303 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_SHIFT (0x00000008U)
2304 #define CSL_DSS_VIDL1_CLUT_6_VALUE_G_MAX (0x000000FFU)
2305 
2306 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_MASK (0x00FF0000U)
2307 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_SHIFT (0x00000010U)
2308 #define CSL_DSS_VIDL1_CLUT_6_VALUE_R_MAX (0x000000FFU)
2309 
2310 #define CSL_DSS_VIDL1_CLUT_6_INDEX_MASK (0xFF000000U)
2311 #define CSL_DSS_VIDL1_CLUT_6_INDEX_SHIFT (0x00000018U)
2312 #define CSL_DSS_VIDL1_CLUT_6_INDEX_MAX (0x000000FFU)
2313 
2314 /* CLUT_7 */
2315 
2316 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_MASK (0x000000FFU)
2317 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_SHIFT (0x00000000U)
2318 #define CSL_DSS_VIDL1_CLUT_7_VALUE_B_MAX (0x000000FFU)
2319 
2320 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_MASK (0x0000FF00U)
2321 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_SHIFT (0x00000008U)
2322 #define CSL_DSS_VIDL1_CLUT_7_VALUE_G_MAX (0x000000FFU)
2323 
2324 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_MASK (0x00FF0000U)
2325 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_SHIFT (0x00000010U)
2326 #define CSL_DSS_VIDL1_CLUT_7_VALUE_R_MAX (0x000000FFU)
2327 
2328 #define CSL_DSS_VIDL1_CLUT_7_INDEX_MASK (0xFF000000U)
2329 #define CSL_DSS_VIDL1_CLUT_7_INDEX_SHIFT (0x00000018U)
2330 #define CSL_DSS_VIDL1_CLUT_7_INDEX_MAX (0x000000FFU)
2331 
2332 /* CLUT_8 */
2333 
2334 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_MASK (0x000000FFU)
2335 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_SHIFT (0x00000000U)
2336 #define CSL_DSS_VIDL1_CLUT_8_VALUE_B_MAX (0x000000FFU)
2337 
2338 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_MASK (0x0000FF00U)
2339 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_SHIFT (0x00000008U)
2340 #define CSL_DSS_VIDL1_CLUT_8_VALUE_G_MAX (0x000000FFU)
2341 
2342 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_MASK (0x00FF0000U)
2343 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_SHIFT (0x00000010U)
2344 #define CSL_DSS_VIDL1_CLUT_8_VALUE_R_MAX (0x000000FFU)
2345 
2346 #define CSL_DSS_VIDL1_CLUT_8_INDEX_MASK (0xFF000000U)
2347 #define CSL_DSS_VIDL1_CLUT_8_INDEX_SHIFT (0x00000018U)
2348 #define CSL_DSS_VIDL1_CLUT_8_INDEX_MAX (0x000000FFU)
2349 
2350 /* CLUT_9 */
2351 
2352 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_MASK (0x000000FFU)
2353 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_SHIFT (0x00000000U)
2354 #define CSL_DSS_VIDL1_CLUT_9_VALUE_B_MAX (0x000000FFU)
2355 
2356 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_MASK (0x0000FF00U)
2357 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_SHIFT (0x00000008U)
2358 #define CSL_DSS_VIDL1_CLUT_9_VALUE_G_MAX (0x000000FFU)
2359 
2360 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_MASK (0x00FF0000U)
2361 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_SHIFT (0x00000010U)
2362 #define CSL_DSS_VIDL1_CLUT_9_VALUE_R_MAX (0x000000FFU)
2363 
2364 #define CSL_DSS_VIDL1_CLUT_9_INDEX_MASK (0xFF000000U)
2365 #define CSL_DSS_VIDL1_CLUT_9_INDEX_SHIFT (0x00000018U)
2366 #define CSL_DSS_VIDL1_CLUT_9_INDEX_MAX (0x000000FFU)
2367 
2368 /* CLUT_10 */
2369 
2370 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_MASK (0x000000FFU)
2371 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_SHIFT (0x00000000U)
2372 #define CSL_DSS_VIDL1_CLUT_10_VALUE_B_MAX (0x000000FFU)
2373 
2374 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_MASK (0x0000FF00U)
2375 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_SHIFT (0x00000008U)
2376 #define CSL_DSS_VIDL1_CLUT_10_VALUE_G_MAX (0x000000FFU)
2377 
2378 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_MASK (0x00FF0000U)
2379 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_SHIFT (0x00000010U)
2380 #define CSL_DSS_VIDL1_CLUT_10_VALUE_R_MAX (0x000000FFU)
2381 
2382 #define CSL_DSS_VIDL1_CLUT_10_INDEX_MASK (0xFF000000U)
2383 #define CSL_DSS_VIDL1_CLUT_10_INDEX_SHIFT (0x00000018U)
2384 #define CSL_DSS_VIDL1_CLUT_10_INDEX_MAX (0x000000FFU)
2385 
2386 /* CLUT_11 */
2387 
2388 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_MASK (0x000000FFU)
2389 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_SHIFT (0x00000000U)
2390 #define CSL_DSS_VIDL1_CLUT_11_VALUE_B_MAX (0x000000FFU)
2391 
2392 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_MASK (0x0000FF00U)
2393 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_SHIFT (0x00000008U)
2394 #define CSL_DSS_VIDL1_CLUT_11_VALUE_G_MAX (0x000000FFU)
2395 
2396 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_MASK (0x00FF0000U)
2397 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_SHIFT (0x00000010U)
2398 #define CSL_DSS_VIDL1_CLUT_11_VALUE_R_MAX (0x000000FFU)
2399 
2400 #define CSL_DSS_VIDL1_CLUT_11_INDEX_MASK (0xFF000000U)
2401 #define CSL_DSS_VIDL1_CLUT_11_INDEX_SHIFT (0x00000018U)
2402 #define CSL_DSS_VIDL1_CLUT_11_INDEX_MAX (0x000000FFU)
2403 
2404 /* CLUT_12 */
2405 
2406 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_MASK (0x000000FFU)
2407 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_SHIFT (0x00000000U)
2408 #define CSL_DSS_VIDL1_CLUT_12_VALUE_B_MAX (0x000000FFU)
2409 
2410 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_MASK (0x0000FF00U)
2411 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_SHIFT (0x00000008U)
2412 #define CSL_DSS_VIDL1_CLUT_12_VALUE_G_MAX (0x000000FFU)
2413 
2414 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_MASK (0x00FF0000U)
2415 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_SHIFT (0x00000010U)
2416 #define CSL_DSS_VIDL1_CLUT_12_VALUE_R_MAX (0x000000FFU)
2417 
2418 #define CSL_DSS_VIDL1_CLUT_12_INDEX_MASK (0xFF000000U)
2419 #define CSL_DSS_VIDL1_CLUT_12_INDEX_SHIFT (0x00000018U)
2420 #define CSL_DSS_VIDL1_CLUT_12_INDEX_MAX (0x000000FFU)
2421 
2422 /* CLUT_13 */
2423 
2424 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_MASK (0x000000FFU)
2425 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_SHIFT (0x00000000U)
2426 #define CSL_DSS_VIDL1_CLUT_13_VALUE_B_MAX (0x000000FFU)
2427 
2428 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_MASK (0x0000FF00U)
2429 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_SHIFT (0x00000008U)
2430 #define CSL_DSS_VIDL1_CLUT_13_VALUE_G_MAX (0x000000FFU)
2431 
2432 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_MASK (0x00FF0000U)
2433 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_SHIFT (0x00000010U)
2434 #define CSL_DSS_VIDL1_CLUT_13_VALUE_R_MAX (0x000000FFU)
2435 
2436 #define CSL_DSS_VIDL1_CLUT_13_INDEX_MASK (0xFF000000U)
2437 #define CSL_DSS_VIDL1_CLUT_13_INDEX_SHIFT (0x00000018U)
2438 #define CSL_DSS_VIDL1_CLUT_13_INDEX_MAX (0x000000FFU)
2439 
2440 /* CLUT_14 */
2441 
2442 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_MASK (0x000000FFU)
2443 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_SHIFT (0x00000000U)
2444 #define CSL_DSS_VIDL1_CLUT_14_VALUE_B_MAX (0x000000FFU)
2445 
2446 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_MASK (0x0000FF00U)
2447 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_SHIFT (0x00000008U)
2448 #define CSL_DSS_VIDL1_CLUT_14_VALUE_G_MAX (0x000000FFU)
2449 
2450 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_MASK (0x00FF0000U)
2451 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_SHIFT (0x00000010U)
2452 #define CSL_DSS_VIDL1_CLUT_14_VALUE_R_MAX (0x000000FFU)
2453 
2454 #define CSL_DSS_VIDL1_CLUT_14_INDEX_MASK (0xFF000000U)
2455 #define CSL_DSS_VIDL1_CLUT_14_INDEX_SHIFT (0x00000018U)
2456 #define CSL_DSS_VIDL1_CLUT_14_INDEX_MAX (0x000000FFU)
2457 
2458 /* CLUT_15 */
2459 
2460 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_MASK (0x000000FFU)
2461 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_SHIFT (0x00000000U)
2462 #define CSL_DSS_VIDL1_CLUT_15_VALUE_B_MAX (0x000000FFU)
2463 
2464 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_MASK (0x0000FF00U)
2465 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_SHIFT (0x00000008U)
2466 #define CSL_DSS_VIDL1_CLUT_15_VALUE_G_MAX (0x000000FFU)
2467 
2468 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_MASK (0x00FF0000U)
2469 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_SHIFT (0x00000010U)
2470 #define CSL_DSS_VIDL1_CLUT_15_VALUE_R_MAX (0x000000FFU)
2471 
2472 #define CSL_DSS_VIDL1_CLUT_15_INDEX_MASK (0xFF000000U)
2473 #define CSL_DSS_VIDL1_CLUT_15_INDEX_SHIFT (0x00000018U)
2474 #define CSL_DSS_VIDL1_CLUT_15_INDEX_MAX (0x000000FFU)
2475 
2476 /* SAFETY_ATTRIBUTES */
2477 
2478 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
2479 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
2480 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
2481 
2482 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
2483 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
2484 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
2485 
2486 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
2487 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
2488 
2489 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
2490 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
2491 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
2492 
2493 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
2494 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
2495 
2496 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
2497 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
2498 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
2499 
2500 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
2501 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
2502 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
2503 
2504 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
2505 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
2506 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
2507 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
2508 
2509 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
2510 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
2511 #define CSL_DSS_VIDL1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
2512 
2513 /* SAFETY_CAPT_SIGNATURE */
2514 
2515 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
2516 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
2517 #define CSL_DSS_VIDL1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
2518 
2519 /* SAFETY_POSITION */
2520 
2521 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_MASK (0x00000FFFU)
2522 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
2523 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSX_MAX (0x00000FFFU)
2524 
2525 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED1_MASK (0x0000F000U)
2526 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED1_SHIFT (0x0000000CU)
2527 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED1_MAX (0x0000000FU)
2528 
2529 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_MASK (0x0FFF0000U)
2530 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
2531 #define CSL_DSS_VIDL1_SAFETY_POSITION_POSY_MAX (0x00000FFFU)
2532 
2533 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED_MASK (0xF0000000U)
2534 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED_SHIFT (0x0000001CU)
2535 #define CSL_DSS_VIDL1_SAFETY_POSITION_RESERVED_MAX (0x0000000FU)
2536 
2537 /* SAFETY_REF_SIGNATURE */
2538 
2539 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
2540 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
2541 #define CSL_DSS_VIDL1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
2542 
2543 /* SAFETY_SIZE */
2544 
2545 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_MASK (0x00000FFFU)
2546 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
2547 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEX_MAX (0x00000FFFU)
2548 
2549 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED1_MASK (0x0000F000U)
2550 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED1_SHIFT (0x0000000CU)
2551 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED1_MAX (0x0000000FU)
2552 
2553 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_MASK (0x0FFF0000U)
2554 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
2555 #define CSL_DSS_VIDL1_SAFETY_SIZE_SIZEY_MAX (0x00000FFFU)
2556 
2557 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED_MASK (0xF0000000U)
2558 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED_SHIFT (0x0000001CU)
2559 #define CSL_DSS_VIDL1_SAFETY_SIZE_RESERVED_MAX (0x0000000FU)
2560 
2561 /* SAFETY_LFSR_SEED */
2562 
2563 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
2564 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
2565 #define CSL_DSS_VIDL1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
2566 
2567 /* LUMAKEY */
2568 
2569 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_MASK (0xF0000000U)
2570 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
2571 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED1_MAX (0x0000000FU)
2572 
2573 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
2574 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
2575 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
2576 
2577 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_MASK (0x0000F000U)
2578 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
2579 #define CSL_DSS_VIDL1_LUMAKEY_RESERVED_MAX (0x0000000FU)
2580 
2581 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
2582 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
2583 #define CSL_DSS_VIDL1_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
2584 
2585 /**************************************************************************
2586 * Hardware Region : VID Registers
2587 **************************************************************************/
2588 
2589 
2590 /**************************************************************************
2591 * Register Overlay Structure
2592 **************************************************************************/
2593 
2594 typedef struct {
2595  volatile uint32_t ACCUH_0; /* ACCUH_0 */
2596  volatile uint32_t ACCUH_1; /* ACCUH_1 */
2597  volatile uint32_t ACCUH2_0; /* ACCUH2_0 */
2598  volatile uint32_t ACCUH2_1; /* ACCUH2_1 */
2599  volatile uint32_t ACCUV_0; /* ACCUV_0 */
2600  volatile uint32_t ACCUV_1; /* ACCUV_1 */
2601  volatile uint32_t ACCUV2_0; /* ACCUV2_0 */
2602  volatile uint32_t ACCUV2_1; /* ACCUV2_1 */
2603  volatile uint32_t ATTRIBUTES; /* ATTRIBUTES */
2604  volatile uint32_t ATTRIBUTES2; /* ATTRIBUTES2 */
2605  volatile uint32_t BA_0; /* BA_0 */
2606  volatile uint32_t BA_1; /* BA_1 */
2607  volatile uint32_t BA_UV_0; /* BA_UV_0 */
2608  volatile uint32_t BA_UV_1; /* BA_UV_1 */
2609  volatile uint32_t BUF_SIZE_STATUS; /* BUF_SIZE_STATUS */
2610  volatile uint32_t BUF_THRESHOLD; /* BUF_THRESHOLD */
2611  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
2612  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
2613  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
2614  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
2615  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
2616  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
2617  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
2618  volatile uint32_t FIRH; /* FIRH */
2619  volatile uint32_t FIRH2; /* FIRH2 */
2620  volatile uint32_t FIRV; /* FIRV */
2621  volatile uint32_t FIRV2; /* FIRV2 */
2622  volatile uint32_t FIR_COEF_H0[9U]; /* FIR_COEF_H0 0..8 */
2623  volatile uint32_t FIR_COEF_H0_C[9U]; /* FIR_COEF_H0_C 0..8 */
2624  volatile uint32_t FIR_COEF_H12[16U]; /* FIR_COEF_H12 0..15 */
2625  volatile uint32_t FIR_COEF_H12_C[16U]; /* FIR_COEF_H12_C 0..15 */
2626  volatile uint32_t FIR_COEF_V0[9U]; /* FIR_COEF_V0 0..8 */
2627  volatile uint32_t FIR_COEF_V0_C[9U]; /* FIR_COEF_V0_C 0..8 */
2628  volatile uint32_t FIR_COEF_V12[16U]; /* FIR_COEF_V12 0..15 */
2629  volatile uint32_t FIR_COEF_V12_C[16U]; /* FIR_COEF_V12_C 0..15 */
2630  volatile uint32_t GLOBAL_ALPHA; /* GLOBAL_ALPHA */
2631  volatile uint8_t Resv_520[8];
2632  volatile uint32_t MFLAG_THRESHOLD; /* MFLAG_THRESHOLD */
2633  volatile uint32_t PICTURE_SIZE; /* PICTURE_SIZE */
2634  volatile uint32_t PIXEL_INC; /* PIXEL_INC */
2635  volatile uint8_t Resv_536[4];
2636  volatile uint32_t PRELOAD; /* PRELOAD */
2637  volatile uint32_t ROW_INC; /* ROW_INC */
2638  volatile uint32_t SIZE; /* SIZE */
2639  volatile uint8_t Resv_556[8];
2640  volatile uint32_t BA_EXT_0; /* BA_EXT_0 */
2641  volatile uint32_t BA_EXT_1; /* BA_EXT_1 */
2642  volatile uint32_t BA_UV_EXT_0; /* BA_UV_EXT_0 */
2643  volatile uint32_t BA_UV_EXT_1; /* BA_UV_EXT_1 */
2644  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
2645  volatile uint8_t Resv_584[8];
2646  volatile uint32_t ROW_INC_UV; /* ROW_INC_UV */
2647  volatile uint8_t Resv_608[20];
2648  volatile uint32_t CLUT_0; /* CLUT_0 */
2649  volatile uint32_t CLUT_1; /* CLUT_1 */
2650  volatile uint32_t CLUT_2; /* CLUT_2 */
2651  volatile uint32_t CLUT_3; /* CLUT_3 */
2652  volatile uint32_t CLUT_4; /* CLUT_4 */
2653  volatile uint32_t CLUT_5; /* CLUT_5 */
2654  volatile uint32_t CLUT_6; /* CLUT_6 */
2655  volatile uint32_t CLUT_7; /* CLUT_7 */
2656  volatile uint32_t CLUT_8; /* CLUT_8 */
2657  volatile uint32_t CLUT_9; /* CLUT_9 */
2658  volatile uint32_t CLUT_10; /* CLUT_10 */
2659  volatile uint32_t CLUT_11; /* CLUT_11 */
2660  volatile uint32_t CLUT_12; /* CLUT_12 */
2661  volatile uint32_t CLUT_13; /* CLUT_13 */
2662  volatile uint32_t CLUT_14; /* CLUT_14 */
2663  volatile uint32_t CLUT_15; /* CLUT_15 */
2664  volatile uint32_t SAFETY_ATTRIBUTES; /* SAFETY_ATTRIBUTES */
2665  volatile uint32_t SAFETY_CAPT_SIGNATURE; /* SAFETY_CAPT_SIGNATURE */
2666  volatile uint32_t SAFETY_POSITION; /* SAFETY_POSITION */
2667  volatile uint32_t SAFETY_REF_SIGNATURE; /* SAFETY_REF_SIGNATURE */
2668  volatile uint32_t SAFETY_SIZE; /* SAFETY_SIZE */
2669  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
2670  volatile uint32_t LUMAKEY; /* LUMAKEY */
2671 } CSL_dss_vidRegs;
2672 
2673 
2674 /**************************************************************************
2675 * Register Macros
2676 **************************************************************************/
2677 
2678 #define CSL_DSS_VID_ACCUH_0 (0x00000000U)
2679 #define CSL_DSS_VID_ACCUH_1 (0x00000004U)
2680 #define CSL_DSS_VID_ACCUH2_0 (0x00000008U)
2681 #define CSL_DSS_VID_ACCUH2_1 (0x0000000CU)
2682 #define CSL_DSS_VID_ACCUV_0 (0x00000010U)
2683 #define CSL_DSS_VID_ACCUV_1 (0x00000014U)
2684 #define CSL_DSS_VID_ACCUV2_0 (0x00000018U)
2685 #define CSL_DSS_VID_ACCUV2_1 (0x0000001CU)
2686 #define CSL_DSS_VID_ATTRIBUTES (0x00000020U)
2687 #define CSL_DSS_VID_ATTRIBUTES2 (0x00000024U)
2688 #define CSL_DSS_VID_BA_0 (0x00000028U)
2689 #define CSL_DSS_VID_BA_1 (0x0000002CU)
2690 #define CSL_DSS_VID_BA_UV_0 (0x00000030U)
2691 #define CSL_DSS_VID_BA_UV_1 (0x00000034U)
2692 #define CSL_DSS_VID_BUF_SIZE_STATUS (0x00000038U)
2693 #define CSL_DSS_VID_BUF_THRESHOLD (0x0000003CU)
2694 #define CSL_DSS_VID_CSC_COEF0 (0x00000040U)
2695 #define CSL_DSS_VID_CSC_COEF1 (0x00000044U)
2696 #define CSL_DSS_VID_CSC_COEF2 (0x00000048U)
2697 #define CSL_DSS_VID_CSC_COEF3 (0x0000004CU)
2698 #define CSL_DSS_VID_CSC_COEF4 (0x00000050U)
2699 #define CSL_DSS_VID_CSC_COEF5 (0x00000054U)
2700 #define CSL_DSS_VID_CSC_COEF6 (0x00000058U)
2701 #define CSL_DSS_VID_FIRH (0x0000005CU)
2702 #define CSL_DSS_VID_FIRH2 (0x00000060U)
2703 #define CSL_DSS_VID_FIRV (0x00000064U)
2704 #define CSL_DSS_VID_FIRV2 (0x00000068U)
2705 #define CSL_DSS_VID_FIR_COEF_H0(index) (0x0000006CU+((uint32_t)(index)*0x4U))
2706 #define CSL_DSS_VID_FIR_COEF_H0_C(index) (0x00000090U+((uint32_t)(index)*0x4U))
2707 #define CSL_DSS_VID_FIR_COEF_H12(index) (0x000000B4U+((uint32_t)(index)*0x4U))
2708 #define CSL_DSS_VID_FIR_COEF_H12_C(index) (0x000000F4U+((uint32_t)(index)*0x4U))
2709 #define CSL_DSS_VID_FIR_COEF_V0(index) (0x00000134U+((uint32_t)(index)*0x4U))
2710 #define CSL_DSS_VID_FIR_COEF_V0_C(index) (0x00000158U+((uint32_t)(index)*0x4U))
2711 #define CSL_DSS_VID_FIR_COEF_V12(index) (0x0000017CU+((uint32_t)(index)*0x4U))
2712 #define CSL_DSS_VID_FIR_COEF_V12_C(index) (0x000001BCU+((uint32_t)(index)*0x4U))
2713 #define CSL_DSS_VID_GLOBAL_ALPHA (0x000001FCU)
2714 #define CSL_DSS_VID_MFLAG_THRESHOLD (0x00000208U)
2715 #define CSL_DSS_VID_PICTURE_SIZE (0x0000020CU)
2716 #define CSL_DSS_VID_PIXEL_INC (0x00000210U)
2717 #define CSL_DSS_VID_PRELOAD (0x00000218U)
2718 #define CSL_DSS_VID_ROW_INC (0x0000021CU)
2719 #define CSL_DSS_VID_SIZE (0x00000220U)
2720 #define CSL_DSS_VID_BA_EXT_0 (0x0000022CU)
2721 #define CSL_DSS_VID_BA_EXT_1 (0x00000230U)
2722 #define CSL_DSS_VID_BA_UV_EXT_0 (0x00000234U)
2723 #define CSL_DSS_VID_BA_UV_EXT_1 (0x00000238U)
2724 #define CSL_DSS_VID_CSC_COEF7 (0x0000023CU)
2725 #define CSL_DSS_VID_ROW_INC_UV (0x00000248U)
2726 #define CSL_DSS_VID_CLUT_0 (0x00000260U)
2727 #define CSL_DSS_VID_CLUT_1 (0x00000264U)
2728 #define CSL_DSS_VID_CLUT_2 (0x00000268U)
2729 #define CSL_DSS_VID_CLUT_3 (0x0000026CU)
2730 #define CSL_DSS_VID_CLUT_4 (0x00000270U)
2731 #define CSL_DSS_VID_CLUT_5 (0x00000274U)
2732 #define CSL_DSS_VID_CLUT_6 (0x00000278U)
2733 #define CSL_DSS_VID_CLUT_7 (0x0000027CU)
2734 #define CSL_DSS_VID_CLUT_8 (0x00000280U)
2735 #define CSL_DSS_VID_CLUT_9 (0x00000284U)
2736 #define CSL_DSS_VID_CLUT_10 (0x00000288U)
2737 #define CSL_DSS_VID_CLUT_11 (0x0000028CU)
2738 #define CSL_DSS_VID_CLUT_12 (0x00000290U)
2739 #define CSL_DSS_VID_CLUT_13 (0x00000294U)
2740 #define CSL_DSS_VID_CLUT_14 (0x00000298U)
2741 #define CSL_DSS_VID_CLUT_15 (0x0000029CU)
2742 #define CSL_DSS_VID_SAFETY_ATTRIBUTES (0x000002A0U)
2743 #define CSL_DSS_VID_SAFETY_CAPT_SIGNATURE (0x000002A4U)
2744 #define CSL_DSS_VID_SAFETY_POSITION (0x000002A8U)
2745 #define CSL_DSS_VID_SAFETY_REF_SIGNATURE (0x000002ACU)
2746 #define CSL_DSS_VID_SAFETY_SIZE (0x000002B0U)
2747 #define CSL_DSS_VID_SAFETY_LFSR_SEED (0x000002B4U)
2748 #define CSL_DSS_VID_LUMAKEY (0x000002B8U)
2749 
2750 /**************************************************************************
2751 * Field Definition Macros
2752 **************************************************************************/
2753 
2754 
2755 /* ACCUH_0 */
2756 
2757 #define CSL_DSS_VID_ACCUH_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
2758 #define CSL_DSS_VID_ACCUH_0_HORIZONTALACCU_SHIFT (0x00000000U)
2759 #define CSL_DSS_VID_ACCUH_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
2760 
2761 #define CSL_DSS_VID_ACCUH_0_RESERVED_MASK (0xFF000000U)
2762 #define CSL_DSS_VID_ACCUH_0_RESERVED_SHIFT (0x00000018U)
2763 #define CSL_DSS_VID_ACCUH_0_RESERVED_MAX (0x000000FFU)
2764 
2765 /* ACCUH_1 */
2766 
2767 #define CSL_DSS_VID_ACCUH_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
2768 #define CSL_DSS_VID_ACCUH_1_HORIZONTALACCU_SHIFT (0x00000000U)
2769 #define CSL_DSS_VID_ACCUH_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
2770 
2771 #define CSL_DSS_VID_ACCUH_1_RESERVED_MASK (0xFF000000U)
2772 #define CSL_DSS_VID_ACCUH_1_RESERVED_SHIFT (0x00000018U)
2773 #define CSL_DSS_VID_ACCUH_1_RESERVED_MAX (0x000000FFU)
2774 
2775 /* ACCUH2_0 */
2776 
2777 #define CSL_DSS_VID_ACCUH2_0_HORIZONTALACCU_MASK (0x00FFFFFFU)
2778 #define CSL_DSS_VID_ACCUH2_0_HORIZONTALACCU_SHIFT (0x00000000U)
2779 #define CSL_DSS_VID_ACCUH2_0_HORIZONTALACCU_MAX (0x00FFFFFFU)
2780 
2781 #define CSL_DSS_VID_ACCUH2_0_RESERVED_MASK (0xFF000000U)
2782 #define CSL_DSS_VID_ACCUH2_0_RESERVED_SHIFT (0x00000018U)
2783 #define CSL_DSS_VID_ACCUH2_0_RESERVED_MAX (0x000000FFU)
2784 
2785 /* ACCUH2_1 */
2786 
2787 #define CSL_DSS_VID_ACCUH2_1_HORIZONTALACCU_MASK (0x00FFFFFFU)
2788 #define CSL_DSS_VID_ACCUH2_1_HORIZONTALACCU_SHIFT (0x00000000U)
2789 #define CSL_DSS_VID_ACCUH2_1_HORIZONTALACCU_MAX (0x00FFFFFFU)
2790 
2791 #define CSL_DSS_VID_ACCUH2_1_RESERVED_MASK (0xFF000000U)
2792 #define CSL_DSS_VID_ACCUH2_1_RESERVED_SHIFT (0x00000018U)
2793 #define CSL_DSS_VID_ACCUH2_1_RESERVED_MAX (0x000000FFU)
2794 
2795 /* ACCUV_0 */
2796 
2797 #define CSL_DSS_VID_ACCUV_0_VERTICALACCU_MASK (0x00FFFFFFU)
2798 #define CSL_DSS_VID_ACCUV_0_VERTICALACCU_SHIFT (0x00000000U)
2799 #define CSL_DSS_VID_ACCUV_0_VERTICALACCU_MAX (0x00FFFFFFU)
2800 
2801 #define CSL_DSS_VID_ACCUV_0_RESERVED_MASK (0xFF000000U)
2802 #define CSL_DSS_VID_ACCUV_0_RESERVED_SHIFT (0x00000018U)
2803 #define CSL_DSS_VID_ACCUV_0_RESERVED_MAX (0x000000FFU)
2804 
2805 /* ACCUV_1 */
2806 
2807 #define CSL_DSS_VID_ACCUV_1_VERTICALACCU_MASK (0x00FFFFFFU)
2808 #define CSL_DSS_VID_ACCUV_1_VERTICALACCU_SHIFT (0x00000000U)
2809 #define CSL_DSS_VID_ACCUV_1_VERTICALACCU_MAX (0x00FFFFFFU)
2810 
2811 #define CSL_DSS_VID_ACCUV_1_RESERVED_MASK (0xFF000000U)
2812 #define CSL_DSS_VID_ACCUV_1_RESERVED_SHIFT (0x00000018U)
2813 #define CSL_DSS_VID_ACCUV_1_RESERVED_MAX (0x000000FFU)
2814 
2815 /* ACCUV2_0 */
2816 
2817 #define CSL_DSS_VID_ACCUV2_0_VERTICALACCU_MASK (0x00FFFFFFU)
2818 #define CSL_DSS_VID_ACCUV2_0_VERTICALACCU_SHIFT (0x00000000U)
2819 #define CSL_DSS_VID_ACCUV2_0_VERTICALACCU_MAX (0x00FFFFFFU)
2820 
2821 #define CSL_DSS_VID_ACCUV2_0_RESERVED_MASK (0xFF000000U)
2822 #define CSL_DSS_VID_ACCUV2_0_RESERVED_SHIFT (0x00000018U)
2823 #define CSL_DSS_VID_ACCUV2_0_RESERVED_MAX (0x000000FFU)
2824 
2825 /* ACCUV2_1 */
2826 
2827 #define CSL_DSS_VID_ACCUV2_1_VERTICALACCU_MASK (0x00FFFFFFU)
2828 #define CSL_DSS_VID_ACCUV2_1_VERTICALACCU_SHIFT (0x00000000U)
2829 #define CSL_DSS_VID_ACCUV2_1_VERTICALACCU_MAX (0x00FFFFFFU)
2830 
2831 #define CSL_DSS_VID_ACCUV2_1_RESERVED_MASK (0xFF000000U)
2832 #define CSL_DSS_VID_ACCUV2_1_RESERVED_SHIFT (0x00000018U)
2833 #define CSL_DSS_VID_ACCUV2_1_RESERVED_MAX (0x000000FFU)
2834 
2835 /* ATTRIBUTES */
2836 
2837 #define CSL_DSS_VID_ATTRIBUTES_ENABLE_MASK (0x00000001U)
2838 #define CSL_DSS_VID_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
2839 #define CSL_DSS_VID_ATTRIBUTES_ENABLE_MAX (0x00000001U)
2840 
2841 #define CSL_DSS_VID_ATTRIBUTES_ENABLE_VAL_VIDEOENB (0x1U)
2842 #define CSL_DSS_VID_ATTRIBUTES_ENABLE_VAL_VIDEODIS (0x0U)
2843 
2844 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_MASK (0x0000007EU)
2845 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_SHIFT (0x00000001U)
2846 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_MAX (0x0000003FU)
2847 
2848 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ARGB16_4444 (0x0U)
2849 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ABGR16_4444 (0x1U)
2850 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGBA16_4444 (0x2U)
2851 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGB16_565 (0x3U)
2852 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BGR16_565 (0x4U)
2853 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ARGB16_1555 (0x5U)
2854 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ABGR16_1555 (0x6U)
2855 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ARGB32_8888 (0x7U)
2856 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ABGR32_8888 (0x8U)
2857 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGBA32_8888 (0x9U)
2858 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BGRA32_8888 (0xAU)
2859 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGB24P_888 (0xBU)
2860 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BGR24P_888 (0xCU)
2861 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ARGB32_2101010 (0xEU)
2862 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ABGR32_2101010 (0xFU)
2863 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_ARGB64_16161616 (0x10U)
2864 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGBA64_16161616 (0x11U)
2865 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BITMAP1 (0x12U)
2866 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BITMAP2 (0x13U)
2867 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BITMAP4 (0x14U)
2868 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BITMAP8 (0x15U)
2869 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGB565A8 (0x16U)
2870 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BGR565A8 (0x17U)
2871 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XRGB16_4444 (0x20U)
2872 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XBGR16_4444 (0x21U)
2873 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGBX16_4444 (0x22U)
2874 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XRGB16_1555 (0x25U)
2875 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XBGR16_1555 (0x26U)
2876 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XRGB32_8888 (0x27U)
2877 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XBGR32_8888 (0x28U)
2878 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGBX32_8888 (0x29U)
2879 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_BGRX32_8888 (0x2AU)
2880 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XRGB32_2101010 (0x2EU)
2881 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XBGR32_2101010 (0x2FU)
2882 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_XRGB64_16161616 (0x30U)
2883 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_RGBX64_16161616 (0x31U)
2884 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_YUV420_NV12 (0x3DU)
2885 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_YUV422_YUV2 (0x3EU)
2886 #define CSL_DSS_VID_ATTRIBUTES_FORMAT_VAL_YUV422_UYVY (0x3FU)
2887 
2888 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_MASK (0x00000180U)
2889 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_SHIFT (0x00000007U)
2890 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_MAX (0x00000003U)
2891 
2892 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_VAL_RESIZEPROC (0x0U)
2893 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_VAL_HRESIZE (0x1U)
2894 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_VAL_VRESIZE (0x2U)
2895 #define CSL_DSS_VID_ATTRIBUTES_RESIZEENABLE_VAL_HVRESIZE (0x3U)
2896 
2897 #define CSL_DSS_VID_ATTRIBUTES_COLORCONVENABLE_MASK (0x00000200U)
2898 #define CSL_DSS_VID_ATTRIBUTES_COLORCONVENABLE_SHIFT (0x00000009U)
2899 #define CSL_DSS_VID_ATTRIBUTES_COLORCONVENABLE_MAX (0x00000001U)
2900 
2901 #define CSL_DSS_VID_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
2902 #define CSL_DSS_VID_ATTRIBUTES_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
2903 
2904 #define CSL_DSS_VID_ATTRIBUTES_NIBBLEMODE_MASK (0x00000400U)
2905 #define CSL_DSS_VID_ATTRIBUTES_NIBBLEMODE_SHIFT (0x0000000AU)
2906 #define CSL_DSS_VID_ATTRIBUTES_NIBBLEMODE_MAX (0x00000001U)
2907 
2908 #define CSL_DSS_VID_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEEN (0x1U)
2909 #define CSL_DSS_VID_ATTRIBUTES_NIBBLEMODE_VAL_NIBBLEMODEDIS (0x0U)
2910 
2911 #define CSL_DSS_VID_ATTRIBUTES_FULLRANGE_MASK (0x00000800U)
2912 #define CSL_DSS_VID_ATTRIBUTES_FULLRANGE_SHIFT (0x0000000BU)
2913 #define CSL_DSS_VID_ATTRIBUTES_FULLRANGE_MAX (0x00000001U)
2914 
2915 #define CSL_DSS_VID_ATTRIBUTES_FULLRANGE_VAL_FULLRANGE (0x1U)
2916 #define CSL_DSS_VID_ATTRIBUTES_FULLRANGE_VAL_LIMRANGE (0x0U)
2917 
2918 #define CSL_DSS_VID_ATTRIBUTES_FLIP_MASK (0x00001000U)
2919 #define CSL_DSS_VID_ATTRIBUTES_FLIP_SHIFT (0x0000000CU)
2920 #define CSL_DSS_VID_ATTRIBUTES_FLIP_MAX (0x00000001U)
2921 
2922 #define CSL_DSS_VID_ATTRIBUTES_FLIP_VAL_FLIP (0x1U)
2923 #define CSL_DSS_VID_ATTRIBUTES_FLIP_VAL_NOFLIP (0x0U)
2924 
2925 #define CSL_DSS_VID_ATTRIBUTES_RESERVED1_MASK (0x00002000U)
2926 #define CSL_DSS_VID_ATTRIBUTES_RESERVED1_SHIFT (0x0000000DU)
2927 #define CSL_DSS_VID_ATTRIBUTES_RESERVED1_MAX (0x00000001U)
2928 
2929 #define CSL_DSS_VID_ATTRIBUTES_RESERVED9_MASK (0x0001C000U)
2930 #define CSL_DSS_VID_ATTRIBUTES_RESERVED9_SHIFT (0x0000000EU)
2931 #define CSL_DSS_VID_ATTRIBUTES_RESERVED9_MAX (0x00000007U)
2932 
2933 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESHAUTO_MASK (0x00020000U)
2934 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESHAUTO_SHIFT (0x00000011U)
2935 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESHAUTO_MAX (0x00000001U)
2936 
2937 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN (0x1U)
2938 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS (0x0U)
2939 
2940 #define CSL_DSS_VID_ATTRIBUTES_RESERVED7_MASK (0x00040000U)
2941 #define CSL_DSS_VID_ATTRIBUTES_RESERVED7_SHIFT (0x00000012U)
2942 #define CSL_DSS_VID_ATTRIBUTES_RESERVED7_MAX (0x00000001U)
2943 
2944 #define CSL_DSS_VID_ATTRIBUTES_BUFPRELOAD_MASK (0x00080000U)
2945 #define CSL_DSS_VID_ATTRIBUTES_BUFPRELOAD_SHIFT (0x00000013U)
2946 #define CSL_DSS_VID_ATTRIBUTES_BUFPRELOAD_MAX (0x00000001U)
2947 
2948 #define CSL_DSS_VID_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES (0x1U)
2949 #define CSL_DSS_VID_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL (0x0U)
2950 
2951 #define CSL_DSS_VID_ATTRIBUTES_RESERVED2_MASK (0x00100000U)
2952 #define CSL_DSS_VID_ATTRIBUTES_RESERVED2_SHIFT (0x00000014U)
2953 #define CSL_DSS_VID_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
2954 
2955 #define CSL_DSS_VID_ATTRIBUTES_VERTICALTAPS_MASK (0x00200000U)
2956 #define CSL_DSS_VID_ATTRIBUTES_VERTICALTAPS_SHIFT (0x00000015U)
2957 #define CSL_DSS_VID_ATTRIBUTES_VERTICALTAPS_MAX (0x00000001U)
2958 
2959 #define CSL_DSS_VID_ATTRIBUTES_VERTICALTAPS_VAL_TAPS5 (0x1U)
2960 #define CSL_DSS_VID_ATTRIBUTES_VERTICALTAPS_VAL_TAPS3 (0x0U)
2961 
2962 #define CSL_DSS_VID_ATTRIBUTES_RESERVED6_MASK (0x00400000U)
2963 #define CSL_DSS_VID_ATTRIBUTES_RESERVED6_SHIFT (0x00000016U)
2964 #define CSL_DSS_VID_ATTRIBUTES_RESERVED6_MAX (0x00000001U)
2965 
2966 #define CSL_DSS_VID_ATTRIBUTES_ARBITRATION_MASK (0x00800000U)
2967 #define CSL_DSS_VID_ATTRIBUTES_ARBITRATION_SHIFT (0x00000017U)
2968 #define CSL_DSS_VID_ATTRIBUTES_ARBITRATION_MAX (0x00000001U)
2969 
2970 #define CSL_DSS_VID_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO (0x1U)
2971 #define CSL_DSS_VID_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO (0x0U)
2972 
2973 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESH_MASK (0x01000000U)
2974 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESH_SHIFT (0x00000018U)
2975 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESH_MAX (0x00000001U)
2976 
2977 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHENB (0x1U)
2978 #define CSL_DSS_VID_ATTRIBUTES_SELFREFRESH_VAL_SELFREFRESHDIS (0x0U)
2979 
2980 #define CSL_DSS_VID_ATTRIBUTES_RESERVED5_MASK (0x0E000000U)
2981 #define CSL_DSS_VID_ATTRIBUTES_RESERVED5_SHIFT (0x00000019U)
2982 #define CSL_DSS_VID_ATTRIBUTES_RESERVED5_MAX (0x00000007U)
2983 
2984 #define CSL_DSS_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK (0x10000000U)
2985 #define CSL_DSS_VID_ATTRIBUTES_PREMULTIPLYALPHA_SHIFT (0x0000001CU)
2986 #define CSL_DSS_VID_ATTRIBUTES_PREMULTIPLYALPHA_MAX (0x00000001U)
2987 
2988 #define CSL_DSS_VID_ATTRIBUTES_PREMULTIPLYALPHA_VAL_PREMULTIPLIEDALPHA (0x1U)
2989 #define CSL_DSS_VID_ATTRIBUTES_PREMULTIPLYALPHA_VAL_NONPREMULTIPLIEDALPHA (0x0U)
2990 
2991 #define CSL_DSS_VID_ATTRIBUTES_RESERVED4_MASK (0x20000000U)
2992 #define CSL_DSS_VID_ATTRIBUTES_RESERVED4_SHIFT (0x0000001DU)
2993 #define CSL_DSS_VID_ATTRIBUTES_RESERVED4_MAX (0x00000001U)
2994 
2995 #define CSL_DSS_VID_ATTRIBUTES_GAMMAINVERSION_MASK (0x40000000U)
2996 #define CSL_DSS_VID_ATTRIBUTES_GAMMAINVERSION_SHIFT (0x0000001EU)
2997 #define CSL_DSS_VID_ATTRIBUTES_GAMMAINVERSION_MAX (0x00000001U)
2998 
2999 #define CSL_DSS_VID_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMAEN (0x1U)
3000 #define CSL_DSS_VID_ATTRIBUTES_GAMMAINVERSION_VAL_INVGAMMADIS (0x0U)
3001 
3002 #define CSL_DSS_VID_ATTRIBUTES_LUMAKEYENABLE_MASK (0x80000000U)
3003 #define CSL_DSS_VID_ATTRIBUTES_LUMAKEYENABLE_SHIFT (0x0000001FU)
3004 #define CSL_DSS_VID_ATTRIBUTES_LUMAKEYENABLE_MAX (0x00000001U)
3005 
3006 #define CSL_DSS_VID_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYEN (0x1U)
3007 #define CSL_DSS_VID_ATTRIBUTES_LUMAKEYENABLE_VAL_LUMAKEYDIS (0x0U)
3008 
3009 /* ATTRIBUTES2 */
3010 
3011 #define CSL_DSS_VID_ATTRIBUTES2_VC1ENABLE_MASK (0x00000001U)
3012 #define CSL_DSS_VID_ATTRIBUTES2_VC1ENABLE_SHIFT (0x00000000U)
3013 #define CSL_DSS_VID_ATTRIBUTES2_VC1ENABLE_MAX (0x00000001U)
3014 
3015 #define CSL_DSS_VID_ATTRIBUTES2_VC1ENABLE_VAL_VC1ENB (0x1U)
3016 #define CSL_DSS_VID_ATTRIBUTES2_VC1ENABLE_VAL_VC1DIS (0x0U)
3017 
3018 #define CSL_DSS_VID_ATTRIBUTES2_VC1_RANGE_Y_MASK (0x0000000EU)
3019 #define CSL_DSS_VID_ATTRIBUTES2_VC1_RANGE_Y_SHIFT (0x00000001U)
3020 #define CSL_DSS_VID_ATTRIBUTES2_VC1_RANGE_Y_MAX (0x00000007U)
3021 
3022 #define CSL_DSS_VID_ATTRIBUTES2_VC1_RANGE_CBCR_MASK (0x00000070U)
3023 #define CSL_DSS_VID_ATTRIBUTES2_VC1_RANGE_CBCR_SHIFT (0x00000004U)
3024 #define CSL_DSS_VID_ATTRIBUTES2_VC1_RANGE_CBCR_MAX (0x00000007U)
3025 
3026 #define CSL_DSS_VID_ATTRIBUTES2_YUV_SIZE_MASK (0x00000180U)
3027 #define CSL_DSS_VID_ATTRIBUTES2_YUV_SIZE_SHIFT (0x00000007U)
3028 #define CSL_DSS_VID_ATTRIBUTES2_YUV_SIZE_MAX (0x00000003U)
3029 
3030 #define CSL_DSS_VID_ATTRIBUTES2_YUV_SIZE_VAL_8B (0x0U)
3031 #define CSL_DSS_VID_ATTRIBUTES2_YUV_SIZE_VAL_10B (0x1U)
3032 #define CSL_DSS_VID_ATTRIBUTES2_YUV_SIZE_VAL_12B (0x2U)
3033 
3034 #define CSL_DSS_VID_ATTRIBUTES2_YUV_MODE_MASK (0x00000200U)
3035 #define CSL_DSS_VID_ATTRIBUTES2_YUV_MODE_SHIFT (0x00000009U)
3036 #define CSL_DSS_VID_ATTRIBUTES2_YUV_MODE_MAX (0x00000001U)
3037 
3038 #define CSL_DSS_VID_ATTRIBUTES2_YUV_MODE_VAL_PACKED (0x0U)
3039 #define CSL_DSS_VID_ATTRIBUTES2_YUV_MODE_VAL_UNPACKED (0x1U)
3040 
3041 #define CSL_DSS_VID_ATTRIBUTES2_YUV_ALIGN_MASK (0x00000400U)
3042 #define CSL_DSS_VID_ATTRIBUTES2_YUV_ALIGN_SHIFT (0x0000000AU)
3043 #define CSL_DSS_VID_ATTRIBUTES2_YUV_ALIGN_MAX (0x00000001U)
3044 
3045 #define CSL_DSS_VID_ATTRIBUTES2_YUV_ALIGN_VAL_MSB (0x1U)
3046 #define CSL_DSS_VID_ATTRIBUTES2_YUV_ALIGN_VAL_LSB (0x0U)
3047 
3048 #define CSL_DSS_VID_ATTRIBUTES2_RESERVED_MASK (0x03FFF800U)
3049 #define CSL_DSS_VID_ATTRIBUTES2_RESERVED_SHIFT (0x0000000BU)
3050 #define CSL_DSS_VID_ATTRIBUTES2_RESERVED_MAX (0x00007FFFU)
3051 
3052 #define CSL_DSS_VID_ATTRIBUTES2_TAGS_MASK (0x7C000000U)
3053 #define CSL_DSS_VID_ATTRIBUTES2_TAGS_SHIFT (0x0000001AU)
3054 #define CSL_DSS_VID_ATTRIBUTES2_TAGS_MAX (0x0000001FU)
3055 
3056 #define CSL_DSS_VID_ATTRIBUTES2_RESERVED3_MASK (0x80000000U)
3057 #define CSL_DSS_VID_ATTRIBUTES2_RESERVED3_SHIFT (0x0000001FU)
3058 #define CSL_DSS_VID_ATTRIBUTES2_RESERVED3_MAX (0x00000001U)
3059 
3060 /* BA_0 */
3061 
3062 #define CSL_DSS_VID_BA_0_BA_MASK (0xFFFFFFFFU)
3063 #define CSL_DSS_VID_BA_0_BA_SHIFT (0x00000000U)
3064 #define CSL_DSS_VID_BA_0_BA_MAX (0xFFFFFFFFU)
3065 
3066 /* BA_1 */
3067 
3068 #define CSL_DSS_VID_BA_1_BA_MASK (0xFFFFFFFFU)
3069 #define CSL_DSS_VID_BA_1_BA_SHIFT (0x00000000U)
3070 #define CSL_DSS_VID_BA_1_BA_MAX (0xFFFFFFFFU)
3071 
3072 /* BA_UV_0 */
3073 
3074 #define CSL_DSS_VID_BA_UV_0_BA_MASK (0xFFFFFFFFU)
3075 #define CSL_DSS_VID_BA_UV_0_BA_SHIFT (0x00000000U)
3076 #define CSL_DSS_VID_BA_UV_0_BA_MAX (0xFFFFFFFFU)
3077 
3078 /* BA_UV_1 */
3079 
3080 #define CSL_DSS_VID_BA_UV_1_BA_MASK (0xFFFFFFFFU)
3081 #define CSL_DSS_VID_BA_UV_1_BA_SHIFT (0x00000000U)
3082 #define CSL_DSS_VID_BA_UV_1_BA_MAX (0xFFFFFFFFU)
3083 
3084 /* BUF_SIZE_STATUS */
3085 
3086 #define CSL_DSS_VID_BUF_SIZE_STATUS_BUFSIZE_MASK (0x0000FFFFU)
3087 #define CSL_DSS_VID_BUF_SIZE_STATUS_BUFSIZE_SHIFT (0x00000000U)
3088 #define CSL_DSS_VID_BUF_SIZE_STATUS_BUFSIZE_MAX (0x0000FFFFU)
3089 
3090 #define CSL_DSS_VID_BUF_SIZE_STATUS_RESERVED_61_MASK (0xFFFF0000U)
3091 #define CSL_DSS_VID_BUF_SIZE_STATUS_RESERVED_61_SHIFT (0x00000010U)
3092 #define CSL_DSS_VID_BUF_SIZE_STATUS_RESERVED_61_MAX (0x0000FFFFU)
3093 
3094 /* BUF_THRESHOLD */
3095 
3096 #define CSL_DSS_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK (0x0000FFFFU)
3097 #define CSL_DSS_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_SHIFT (0x00000000U)
3098 #define CSL_DSS_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MAX (0x0000FFFFU)
3099 
3100 #define CSL_DSS_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK (0xFFFF0000U)
3101 #define CSL_DSS_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_SHIFT (0x00000010U)
3102 #define CSL_DSS_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MAX (0x0000FFFFU)
3103 
3104 /* CSC_COEF0 */
3105 
3106 #define CSL_DSS_VID_CSC_COEF0_C00_MASK (0x000007FFU)
3107 #define CSL_DSS_VID_CSC_COEF0_C00_SHIFT (0x00000000U)
3108 #define CSL_DSS_VID_CSC_COEF0_C00_MAX (0x000007FFU)
3109 
3110 #define CSL_DSS_VID_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
3111 #define CSL_DSS_VID_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
3112 #define CSL_DSS_VID_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
3113 
3114 #define CSL_DSS_VID_CSC_COEF0_C01_MASK (0x07FF0000U)
3115 #define CSL_DSS_VID_CSC_COEF0_C01_SHIFT (0x00000010U)
3116 #define CSL_DSS_VID_CSC_COEF0_C01_MAX (0x000007FFU)
3117 
3118 #define CSL_DSS_VID_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
3119 #define CSL_DSS_VID_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
3120 #define CSL_DSS_VID_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
3121 
3122 /* CSC_COEF1 */
3123 
3124 #define CSL_DSS_VID_CSC_COEF1_C02_MASK (0x000007FFU)
3125 #define CSL_DSS_VID_CSC_COEF1_C02_SHIFT (0x00000000U)
3126 #define CSL_DSS_VID_CSC_COEF1_C02_MAX (0x000007FFU)
3127 
3128 #define CSL_DSS_VID_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
3129 #define CSL_DSS_VID_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
3130 #define CSL_DSS_VID_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
3131 
3132 #define CSL_DSS_VID_CSC_COEF1_C10_MASK (0x07FF0000U)
3133 #define CSL_DSS_VID_CSC_COEF1_C10_SHIFT (0x00000010U)
3134 #define CSL_DSS_VID_CSC_COEF1_C10_MAX (0x000007FFU)
3135 
3136 #define CSL_DSS_VID_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
3137 #define CSL_DSS_VID_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
3138 #define CSL_DSS_VID_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
3139 
3140 /* CSC_COEF2 */
3141 
3142 #define CSL_DSS_VID_CSC_COEF2_C11_MASK (0x000007FFU)
3143 #define CSL_DSS_VID_CSC_COEF2_C11_SHIFT (0x00000000U)
3144 #define CSL_DSS_VID_CSC_COEF2_C11_MAX (0x000007FFU)
3145 
3146 #define CSL_DSS_VID_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
3147 #define CSL_DSS_VID_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
3148 #define CSL_DSS_VID_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
3149 
3150 #define CSL_DSS_VID_CSC_COEF2_C12_MASK (0x07FF0000U)
3151 #define CSL_DSS_VID_CSC_COEF2_C12_SHIFT (0x00000010U)
3152 #define CSL_DSS_VID_CSC_COEF2_C12_MAX (0x000007FFU)
3153 
3154 #define CSL_DSS_VID_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
3155 #define CSL_DSS_VID_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
3156 #define CSL_DSS_VID_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
3157 
3158 /* CSC_COEF3 */
3159 
3160 #define CSL_DSS_VID_CSC_COEF3_C20_MASK (0x000007FFU)
3161 #define CSL_DSS_VID_CSC_COEF3_C20_SHIFT (0x00000000U)
3162 #define CSL_DSS_VID_CSC_COEF3_C20_MAX (0x000007FFU)
3163 
3164 #define CSL_DSS_VID_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
3165 #define CSL_DSS_VID_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
3166 #define CSL_DSS_VID_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
3167 
3168 #define CSL_DSS_VID_CSC_COEF3_C21_MASK (0x07FF0000U)
3169 #define CSL_DSS_VID_CSC_COEF3_C21_SHIFT (0x00000010U)
3170 #define CSL_DSS_VID_CSC_COEF3_C21_MAX (0x000007FFU)
3171 
3172 #define CSL_DSS_VID_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
3173 #define CSL_DSS_VID_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
3174 #define CSL_DSS_VID_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
3175 
3176 /* CSC_COEF4 */
3177 
3178 #define CSL_DSS_VID_CSC_COEF4_C22_MASK (0x000007FFU)
3179 #define CSL_DSS_VID_CSC_COEF4_C22_SHIFT (0x00000000U)
3180 #define CSL_DSS_VID_CSC_COEF4_C22_MAX (0x000007FFU)
3181 
3182 #define CSL_DSS_VID_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
3183 #define CSL_DSS_VID_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
3184 #define CSL_DSS_VID_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
3185 
3186 /* CSC_COEF5 */
3187 
3188 #define CSL_DSS_VID_CSC_COEF5_RESERVED_MASK (0x00000007U)
3189 #define CSL_DSS_VID_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
3190 #define CSL_DSS_VID_CSC_COEF5_RESERVED_MAX (0x00000007U)
3191 
3192 #define CSL_DSS_VID_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
3193 #define CSL_DSS_VID_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
3194 #define CSL_DSS_VID_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
3195 
3196 #define CSL_DSS_VID_CSC_COEF5_RESERVED1_MASK (0x00070000U)
3197 #define CSL_DSS_VID_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
3198 #define CSL_DSS_VID_CSC_COEF5_RESERVED1_MAX (0x00000007U)
3199 
3200 #define CSL_DSS_VID_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
3201 #define CSL_DSS_VID_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
3202 #define CSL_DSS_VID_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
3203 
3204 /* CSC_COEF6 */
3205 
3206 #define CSL_DSS_VID_CSC_COEF6_RESERVED_MASK (0x00000007U)
3207 #define CSL_DSS_VID_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
3208 #define CSL_DSS_VID_CSC_COEF6_RESERVED_MAX (0x00000007U)
3209 
3210 #define CSL_DSS_VID_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
3211 #define CSL_DSS_VID_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
3212 #define CSL_DSS_VID_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
3213 
3214 #define CSL_DSS_VID_CSC_COEF6_RESERVED1_MASK (0x00070000U)
3215 #define CSL_DSS_VID_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
3216 #define CSL_DSS_VID_CSC_COEF6_RESERVED1_MAX (0x00000007U)
3217 
3218 #define CSL_DSS_VID_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
3219 #define CSL_DSS_VID_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
3220 #define CSL_DSS_VID_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
3221 
3222 /* FIRH */
3223 
3224 #define CSL_DSS_VID_FIRH_FIRHINC_MASK (0x00FFFFFFU)
3225 #define CSL_DSS_VID_FIRH_FIRHINC_SHIFT (0x00000000U)
3226 #define CSL_DSS_VID_FIRH_FIRHINC_MAX (0x00FFFFFFU)
3227 
3228 #define CSL_DSS_VID_FIRH_RESERVED_MASK (0xFF000000U)
3229 #define CSL_DSS_VID_FIRH_RESERVED_SHIFT (0x00000018U)
3230 #define CSL_DSS_VID_FIRH_RESERVED_MAX (0x000000FFU)
3231 
3232 /* FIRH2 */
3233 
3234 #define CSL_DSS_VID_FIRH2_FIRHINC_MASK (0x00FFFFFFU)
3235 #define CSL_DSS_VID_FIRH2_FIRHINC_SHIFT (0x00000000U)
3236 #define CSL_DSS_VID_FIRH2_FIRHINC_MAX (0x00FFFFFFU)
3237 
3238 #define CSL_DSS_VID_FIRH2_RESERVED_MASK (0xFF000000U)
3239 #define CSL_DSS_VID_FIRH2_RESERVED_SHIFT (0x00000018U)
3240 #define CSL_DSS_VID_FIRH2_RESERVED_MAX (0x000000FFU)
3241 
3242 /* FIRV */
3243 
3244 #define CSL_DSS_VID_FIRV_FIRVINC_MASK (0x00FFFFFFU)
3245 #define CSL_DSS_VID_FIRV_FIRVINC_SHIFT (0x00000000U)
3246 #define CSL_DSS_VID_FIRV_FIRVINC_MAX (0x00FFFFFFU)
3247 
3248 #define CSL_DSS_VID_FIRV_RESERVED_MASK (0xFF000000U)
3249 #define CSL_DSS_VID_FIRV_RESERVED_SHIFT (0x00000018U)
3250 #define CSL_DSS_VID_FIRV_RESERVED_MAX (0x000000FFU)
3251 
3252 /* FIRV2 */
3253 
3254 #define CSL_DSS_VID_FIRV2_FIRVINC_MASK (0x00FFFFFFU)
3255 #define CSL_DSS_VID_FIRV2_FIRVINC_SHIFT (0x00000000U)
3256 #define CSL_DSS_VID_FIRV2_FIRVINC_MAX (0x00FFFFFFU)
3257 
3258 #define CSL_DSS_VID_FIRV2_RESERVED_MASK (0xFF000000U)
3259 #define CSL_DSS_VID_FIRV2_RESERVED_SHIFT (0x00000018U)
3260 #define CSL_DSS_VID_FIRV2_RESERVED_MAX (0x000000FFU)
3261 
3262 /* FIR_COEF_H0 */
3263 
3264 #define CSL_DSS_VID_FIR_COEF_H0_FIRHC0_MASK (0x000003FFU)
3265 #define CSL_DSS_VID_FIR_COEF_H0_FIRHC0_SHIFT (0x00000000U)
3266 #define CSL_DSS_VID_FIR_COEF_H0_FIRHC0_MAX (0x000003FFU)
3267 
3268 #define CSL_DSS_VID_FIR_COEF_H0_RESERVED1_MASK (0x3FFFFC00U)
3269 #define CSL_DSS_VID_FIR_COEF_H0_RESERVED1_SHIFT (0x0000000AU)
3270 #define CSL_DSS_VID_FIR_COEF_H0_RESERVED1_MAX (0x000FFFFFU)
3271 
3272 #define CSL_DSS_VID_FIR_COEF_H0_RESERVED_MASK (0xC0000000U)
3273 #define CSL_DSS_VID_FIR_COEF_H0_RESERVED_SHIFT (0x0000001EU)
3274 #define CSL_DSS_VID_FIR_COEF_H0_RESERVED_MAX (0x00000003U)
3275 
3276 /* FIR_COEF_H0_C */
3277 
3278 #define CSL_DSS_VID_FIR_COEF_H0_C_FIRHC0_MASK (0x000003FFU)
3279 #define CSL_DSS_VID_FIR_COEF_H0_C_FIRHC0_SHIFT (0x00000000U)
3280 #define CSL_DSS_VID_FIR_COEF_H0_C_FIRHC0_MAX (0x000003FFU)
3281 
3282 #define CSL_DSS_VID_FIR_COEF_H0_C_RESERVED1_MASK (0x3FFFFC00U)
3283 #define CSL_DSS_VID_FIR_COEF_H0_C_RESERVED1_SHIFT (0x0000000AU)
3284 #define CSL_DSS_VID_FIR_COEF_H0_C_RESERVED1_MAX (0x000FFFFFU)
3285 
3286 #define CSL_DSS_VID_FIR_COEF_H0_C_RESERVED_MASK (0xC0000000U)
3287 #define CSL_DSS_VID_FIR_COEF_H0_C_RESERVED_SHIFT (0x0000001EU)
3288 #define CSL_DSS_VID_FIR_COEF_H0_C_RESERVED_MAX (0x00000003U)
3289 
3290 /* FIR_COEF_H12 */
3291 
3292 #define CSL_DSS_VID_FIR_COEF_H12_RESERVED1_MASK (0x000003FFU)
3293 #define CSL_DSS_VID_FIR_COEF_H12_RESERVED1_SHIFT (0x00000000U)
3294 #define CSL_DSS_VID_FIR_COEF_H12_RESERVED1_MAX (0x000003FFU)
3295 
3296 #define CSL_DSS_VID_FIR_COEF_H12_FIRHC1_MASK (0x000FFC00U)
3297 #define CSL_DSS_VID_FIR_COEF_H12_FIRHC1_SHIFT (0x0000000AU)
3298 #define CSL_DSS_VID_FIR_COEF_H12_FIRHC1_MAX (0x000003FFU)
3299 
3300 #define CSL_DSS_VID_FIR_COEF_H12_FIRHC2_MASK (0x3FF00000U)
3301 #define CSL_DSS_VID_FIR_COEF_H12_FIRHC2_SHIFT (0x00000014U)
3302 #define CSL_DSS_VID_FIR_COEF_H12_FIRHC2_MAX (0x000003FFU)
3303 
3304 #define CSL_DSS_VID_FIR_COEF_H12_RESERVED_MASK (0xC0000000U)
3305 #define CSL_DSS_VID_FIR_COEF_H12_RESERVED_SHIFT (0x0000001EU)
3306 #define CSL_DSS_VID_FIR_COEF_H12_RESERVED_MAX (0x00000003U)
3307 
3308 /* FIR_COEF_H12_C */
3309 
3310 #define CSL_DSS_VID_FIR_COEF_H12_C_RESERVED1_MASK (0x000003FFU)
3311 #define CSL_DSS_VID_FIR_COEF_H12_C_RESERVED1_SHIFT (0x00000000U)
3312 #define CSL_DSS_VID_FIR_COEF_H12_C_RESERVED1_MAX (0x000003FFU)
3313 
3314 #define CSL_DSS_VID_FIR_COEF_H12_C_FIRHC1_MASK (0x000FFC00U)
3315 #define CSL_DSS_VID_FIR_COEF_H12_C_FIRHC1_SHIFT (0x0000000AU)
3316 #define CSL_DSS_VID_FIR_COEF_H12_C_FIRHC1_MAX (0x000003FFU)
3317 
3318 #define CSL_DSS_VID_FIR_COEF_H12_C_FIRHC2_MASK (0x3FF00000U)
3319 #define CSL_DSS_VID_FIR_COEF_H12_C_FIRHC2_SHIFT (0x00000014U)
3320 #define CSL_DSS_VID_FIR_COEF_H12_C_FIRHC2_MAX (0x000003FFU)
3321 
3322 #define CSL_DSS_VID_FIR_COEF_H12_C_RESERVED_MASK (0xC0000000U)
3323 #define CSL_DSS_VID_FIR_COEF_H12_C_RESERVED_SHIFT (0x0000001EU)
3324 #define CSL_DSS_VID_FIR_COEF_H12_C_RESERVED_MAX (0x00000003U)
3325 
3326 /* FIR_COEF_V0 */
3327 
3328 #define CSL_DSS_VID_FIR_COEF_V0_FIRVC0_MASK (0x000003FFU)
3329 #define CSL_DSS_VID_FIR_COEF_V0_FIRVC0_SHIFT (0x00000000U)
3330 #define CSL_DSS_VID_FIR_COEF_V0_FIRVC0_MAX (0x000003FFU)
3331 
3332 #define CSL_DSS_VID_FIR_COEF_V0_RESERVED1_MASK (0x3FFFFC00U)
3333 #define CSL_DSS_VID_FIR_COEF_V0_RESERVED1_SHIFT (0x0000000AU)
3334 #define CSL_DSS_VID_FIR_COEF_V0_RESERVED1_MAX (0x000FFFFFU)
3335 
3336 #define CSL_DSS_VID_FIR_COEF_V0_RESERVED_MASK (0xC0000000U)
3337 #define CSL_DSS_VID_FIR_COEF_V0_RESERVED_SHIFT (0x0000001EU)
3338 #define CSL_DSS_VID_FIR_COEF_V0_RESERVED_MAX (0x00000003U)
3339 
3340 /* FIR_COEF_V0_C */
3341 
3342 #define CSL_DSS_VID_FIR_COEF_V0_C_FIRVC0_MASK (0x000003FFU)
3343 #define CSL_DSS_VID_FIR_COEF_V0_C_FIRVC0_SHIFT (0x00000000U)
3344 #define CSL_DSS_VID_FIR_COEF_V0_C_FIRVC0_MAX (0x000003FFU)
3345 
3346 #define CSL_DSS_VID_FIR_COEF_V0_C_RESERVED1_MASK (0x3FFFFC00U)
3347 #define CSL_DSS_VID_FIR_COEF_V0_C_RESERVED1_SHIFT (0x0000000AU)
3348 #define CSL_DSS_VID_FIR_COEF_V0_C_RESERVED1_MAX (0x000FFFFFU)
3349 
3350 #define CSL_DSS_VID_FIR_COEF_V0_C_RESERVED_MASK (0xC0000000U)
3351 #define CSL_DSS_VID_FIR_COEF_V0_C_RESERVED_SHIFT (0x0000001EU)
3352 #define CSL_DSS_VID_FIR_COEF_V0_C_RESERVED_MAX (0x00000003U)
3353 
3354 /* FIR_COEF_V12 */
3355 
3356 #define CSL_DSS_VID_FIR_COEF_V12_RESERVED1_MASK (0x000003FFU)
3357 #define CSL_DSS_VID_FIR_COEF_V12_RESERVED1_SHIFT (0x00000000U)
3358 #define CSL_DSS_VID_FIR_COEF_V12_RESERVED1_MAX (0x000003FFU)
3359 
3360 #define CSL_DSS_VID_FIR_COEF_V12_FIRVC1_MASK (0x000FFC00U)
3361 #define CSL_DSS_VID_FIR_COEF_V12_FIRVC1_SHIFT (0x0000000AU)
3362 #define CSL_DSS_VID_FIR_COEF_V12_FIRVC1_MAX (0x000003FFU)
3363 
3364 #define CSL_DSS_VID_FIR_COEF_V12_FIRVC2_MASK (0x3FF00000U)
3365 #define CSL_DSS_VID_FIR_COEF_V12_FIRVC2_SHIFT (0x00000014U)
3366 #define CSL_DSS_VID_FIR_COEF_V12_FIRVC2_MAX (0x000003FFU)
3367 
3368 #define CSL_DSS_VID_FIR_COEF_V12_RESERVED_MASK (0xC0000000U)
3369 #define CSL_DSS_VID_FIR_COEF_V12_RESERVED_SHIFT (0x0000001EU)
3370 #define CSL_DSS_VID_FIR_COEF_V12_RESERVED_MAX (0x00000003U)
3371 
3372 /* FIR_COEF_V12_C */
3373 
3374 #define CSL_DSS_VID_FIR_COEF_V12_C_RESERVED1_MASK (0x000003FFU)
3375 #define CSL_DSS_VID_FIR_COEF_V12_C_RESERVED1_SHIFT (0x00000000U)
3376 #define CSL_DSS_VID_FIR_COEF_V12_C_RESERVED1_MAX (0x000003FFU)
3377 
3378 #define CSL_DSS_VID_FIR_COEF_V12_C_FIRVC1_MASK (0x000FFC00U)
3379 #define CSL_DSS_VID_FIR_COEF_V12_C_FIRVC1_SHIFT (0x0000000AU)
3380 #define CSL_DSS_VID_FIR_COEF_V12_C_FIRVC1_MAX (0x000003FFU)
3381 
3382 #define CSL_DSS_VID_FIR_COEF_V12_C_FIRVC2_MASK (0x3FF00000U)
3383 #define CSL_DSS_VID_FIR_COEF_V12_C_FIRVC2_SHIFT (0x00000014U)
3384 #define CSL_DSS_VID_FIR_COEF_V12_C_FIRVC2_MAX (0x000003FFU)
3385 
3386 #define CSL_DSS_VID_FIR_COEF_V12_C_RESERVED_MASK (0xC0000000U)
3387 #define CSL_DSS_VID_FIR_COEF_V12_C_RESERVED_SHIFT (0x0000001EU)
3388 #define CSL_DSS_VID_FIR_COEF_V12_C_RESERVED_MAX (0x00000003U)
3389 
3390 /* GLOBAL_ALPHA */
3391 
3392 #define CSL_DSS_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK (0x000000FFU)
3393 #define CSL_DSS_VID_GLOBAL_ALPHA_GLOBALALPHA_SHIFT (0x00000000U)
3394 #define CSL_DSS_VID_GLOBAL_ALPHA_GLOBALALPHA_MAX (0x000000FFU)
3395 
3396 #define CSL_DSS_VID_GLOBAL_ALPHA_RESERVED_MASK (0xFFFFFF00U)
3397 #define CSL_DSS_VID_GLOBAL_ALPHA_RESERVED_SHIFT (0x00000008U)
3398 #define CSL_DSS_VID_GLOBAL_ALPHA_RESERVED_MAX (0x00FFFFFFU)
3399 
3400 /* MFLAG_THRESHOLD */
3401 
3402 #define CSL_DSS_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK (0x0000FFFFU)
3403 #define CSL_DSS_VID_MFLAG_THRESHOLD_LT_MFLAG_SHIFT (0x00000000U)
3404 #define CSL_DSS_VID_MFLAG_THRESHOLD_LT_MFLAG_MAX (0x0000FFFFU)
3405 
3406 #define CSL_DSS_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK (0xFFFF0000U)
3407 #define CSL_DSS_VID_MFLAG_THRESHOLD_HT_MFLAG_SHIFT (0x00000010U)
3408 #define CSL_DSS_VID_MFLAG_THRESHOLD_HT_MFLAG_MAX (0x0000FFFFU)
3409 
3410 /* PICTURE_SIZE */
3411 
3412 #define CSL_DSS_VID_PICTURE_SIZE_MEMSIZEX_MASK (0x00000FFFU)
3413 #define CSL_DSS_VID_PICTURE_SIZE_MEMSIZEX_SHIFT (0x00000000U)
3414 #define CSL_DSS_VID_PICTURE_SIZE_MEMSIZEX_MAX (0x00000FFFU)
3415 
3416 #define CSL_DSS_VID_PICTURE_SIZE_RESERVED1_MASK (0x0000F000U)
3417 #define CSL_DSS_VID_PICTURE_SIZE_RESERVED1_SHIFT (0x0000000CU)
3418 #define CSL_DSS_VID_PICTURE_SIZE_RESERVED1_MAX (0x0000000FU)
3419 
3420 #define CSL_DSS_VID_PICTURE_SIZE_MEMSIZEY_MASK (0x0FFF0000U)
3421 #define CSL_DSS_VID_PICTURE_SIZE_MEMSIZEY_SHIFT (0x00000010U)
3422 #define CSL_DSS_VID_PICTURE_SIZE_MEMSIZEY_MAX (0x00000FFFU)
3423 
3424 #define CSL_DSS_VID_PICTURE_SIZE_RESERVED_MASK (0xF0000000U)
3425 #define CSL_DSS_VID_PICTURE_SIZE_RESERVED_SHIFT (0x0000001CU)
3426 #define CSL_DSS_VID_PICTURE_SIZE_RESERVED_MAX (0x0000000FU)
3427 
3428 /* PIXEL_INC */
3429 
3430 #define CSL_DSS_VID_PIXEL_INC_PIXELINC_MASK (0x000000FFU)
3431 #define CSL_DSS_VID_PIXEL_INC_PIXELINC_SHIFT (0x00000000U)
3432 #define CSL_DSS_VID_PIXEL_INC_PIXELINC_MAX (0x000000FFU)
3433 
3434 #define CSL_DSS_VID_PIXEL_INC_RESERVED_68_MASK (0xFFFFFF00U)
3435 #define CSL_DSS_VID_PIXEL_INC_RESERVED_68_SHIFT (0x00000008U)
3436 #define CSL_DSS_VID_PIXEL_INC_RESERVED_68_MAX (0x00FFFFFFU)
3437 
3438 /* PRELOAD */
3439 
3440 #define CSL_DSS_VID_PRELOAD_PRELOAD_MASK (0x00000FFFU)
3441 #define CSL_DSS_VID_PRELOAD_PRELOAD_SHIFT (0x00000000U)
3442 #define CSL_DSS_VID_PRELOAD_PRELOAD_MAX (0x00000FFFU)
3443 
3444 #define CSL_DSS_VID_PRELOAD_RESERVED_212_MASK (0xFFFFF000U)
3445 #define CSL_DSS_VID_PRELOAD_RESERVED_212_SHIFT (0x0000000CU)
3446 #define CSL_DSS_VID_PRELOAD_RESERVED_212_MAX (0x000FFFFFU)
3447 
3448 /* ROW_INC */
3449 
3450 #define CSL_DSS_VID_ROW_INC_ROWINC_MASK (0xFFFFFFFFU)
3451 #define CSL_DSS_VID_ROW_INC_ROWINC_SHIFT (0x00000000U)
3452 #define CSL_DSS_VID_ROW_INC_ROWINC_MAX (0xFFFFFFFFU)
3453 
3454 /* SIZE */
3455 
3456 #define CSL_DSS_VID_SIZE_SIZEX_MASK (0x00000FFFU)
3457 #define CSL_DSS_VID_SIZE_SIZEX_SHIFT (0x00000000U)
3458 #define CSL_DSS_VID_SIZE_SIZEX_MAX (0x00000FFFU)
3459 
3460 #define CSL_DSS_VID_SIZE_RESERVED_MASK (0x0000F000U)
3461 #define CSL_DSS_VID_SIZE_RESERVED_SHIFT (0x0000000CU)
3462 #define CSL_DSS_VID_SIZE_RESERVED_MAX (0x0000000FU)
3463 
3464 #define CSL_DSS_VID_SIZE_SIZEY_MASK (0x0FFF0000U)
3465 #define CSL_DSS_VID_SIZE_SIZEY_SHIFT (0x00000010U)
3466 #define CSL_DSS_VID_SIZE_SIZEY_MAX (0x00000FFFU)
3467 
3468 #define CSL_DSS_VID_SIZE_RESERVED1_MASK (0xF0000000U)
3469 #define CSL_DSS_VID_SIZE_RESERVED1_SHIFT (0x0000001CU)
3470 #define CSL_DSS_VID_SIZE_RESERVED1_MAX (0x0000000FU)
3471 
3472 /* BA_EXT_0 */
3473 
3474 #define CSL_DSS_VID_BA_EXT_0_BA_EXT_MASK (0x0000FFFFU)
3475 #define CSL_DSS_VID_BA_EXT_0_BA_EXT_SHIFT (0x00000000U)
3476 #define CSL_DSS_VID_BA_EXT_0_BA_EXT_MAX (0x0000FFFFU)
3477 
3478 #define CSL_DSS_VID_BA_EXT_0_RESERVED_MASK (0xFFFF0000U)
3479 #define CSL_DSS_VID_BA_EXT_0_RESERVED_SHIFT (0x00000010U)
3480 #define CSL_DSS_VID_BA_EXT_0_RESERVED_MAX (0x0000FFFFU)
3481 
3482 /* BA_EXT_1 */
3483 
3484 #define CSL_DSS_VID_BA_EXT_1_BA_EXT_MASK (0x0000FFFFU)
3485 #define CSL_DSS_VID_BA_EXT_1_BA_EXT_SHIFT (0x00000000U)
3486 #define CSL_DSS_VID_BA_EXT_1_BA_EXT_MAX (0x0000FFFFU)
3487 
3488 #define CSL_DSS_VID_BA_EXT_1_RESERVED_MASK (0xFFFF0000U)
3489 #define CSL_DSS_VID_BA_EXT_1_RESERVED_SHIFT (0x00000010U)
3490 #define CSL_DSS_VID_BA_EXT_1_RESERVED_MAX (0x0000FFFFU)
3491 
3492 /* BA_UV_EXT_0 */
3493 
3494 #define CSL_DSS_VID_BA_UV_EXT_0_BA_UV_EXT_MASK (0x0000FFFFU)
3495 #define CSL_DSS_VID_BA_UV_EXT_0_BA_UV_EXT_SHIFT (0x00000000U)
3496 #define CSL_DSS_VID_BA_UV_EXT_0_BA_UV_EXT_MAX (0x0000FFFFU)
3497 
3498 #define CSL_DSS_VID_BA_UV_EXT_0_RESERVED_MASK (0xFFFF0000U)
3499 #define CSL_DSS_VID_BA_UV_EXT_0_RESERVED_SHIFT (0x00000010U)
3500 #define CSL_DSS_VID_BA_UV_EXT_0_RESERVED_MAX (0x0000FFFFU)
3501 
3502 /* BA_UV_EXT_1 */
3503 
3504 #define CSL_DSS_VID_BA_UV_EXT_1_BA_UV_EXT_MASK (0x0000FFFFU)
3505 #define CSL_DSS_VID_BA_UV_EXT_1_BA_UV_EXT_SHIFT (0x00000000U)
3506 #define CSL_DSS_VID_BA_UV_EXT_1_BA_UV_EXT_MAX (0x0000FFFFU)
3507 
3508 #define CSL_DSS_VID_BA_UV_EXT_1_RESERVED_MASK (0xFFFF0000U)
3509 #define CSL_DSS_VID_BA_UV_EXT_1_RESERVED_SHIFT (0x00000010U)
3510 #define CSL_DSS_VID_BA_UV_EXT_1_RESERVED_MAX (0x0000FFFFU)
3511 
3512 /* CSC_COEF7 */
3513 
3514 #define CSL_DSS_VID_CSC_COEF7_RESERVED_MASK (0x00000007U)
3515 #define CSL_DSS_VID_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
3516 #define CSL_DSS_VID_CSC_COEF7_RESERVED_MAX (0x00000007U)
3517 
3518 #define CSL_DSS_VID_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
3519 #define CSL_DSS_VID_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
3520 #define CSL_DSS_VID_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
3521 
3522 #define CSL_DSS_VID_CSC_COEF7_RESERVED1_MASK (0x00070000U)
3523 #define CSL_DSS_VID_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
3524 #define CSL_DSS_VID_CSC_COEF7_RESERVED1_MAX (0x00000007U)
3525 
3526 #define CSL_DSS_VID_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
3527 #define CSL_DSS_VID_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
3528 #define CSL_DSS_VID_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
3529 
3530 /* ROW_INC_UV */
3531 
3532 #define CSL_DSS_VID_ROW_INC_UV_ROWINC_MASK (0xFFFFFFFFU)
3533 #define CSL_DSS_VID_ROW_INC_UV_ROWINC_SHIFT (0x00000000U)
3534 #define CSL_DSS_VID_ROW_INC_UV_ROWINC_MAX (0xFFFFFFFFU)
3535 
3536 /* CLUT_0 */
3537 
3538 #define CSL_DSS_VID_CLUT_0_VALUE_B_MASK (0x000000FFU)
3539 #define CSL_DSS_VID_CLUT_0_VALUE_B_SHIFT (0x00000000U)
3540 #define CSL_DSS_VID_CLUT_0_VALUE_B_MAX (0x000000FFU)
3541 
3542 #define CSL_DSS_VID_CLUT_0_VALUE_G_MASK (0x0000FF00U)
3543 #define CSL_DSS_VID_CLUT_0_VALUE_G_SHIFT (0x00000008U)
3544 #define CSL_DSS_VID_CLUT_0_VALUE_G_MAX (0x000000FFU)
3545 
3546 #define CSL_DSS_VID_CLUT_0_VALUE_R_MASK (0x00FF0000U)
3547 #define CSL_DSS_VID_CLUT_0_VALUE_R_SHIFT (0x00000010U)
3548 #define CSL_DSS_VID_CLUT_0_VALUE_R_MAX (0x000000FFU)
3549 
3550 #define CSL_DSS_VID_CLUT_0_INDEX_MASK (0xFF000000U)
3551 #define CSL_DSS_VID_CLUT_0_INDEX_SHIFT (0x00000018U)
3552 #define CSL_DSS_VID_CLUT_0_INDEX_MAX (0x000000FFU)
3553 
3554 /* CLUT_1 */
3555 
3556 #define CSL_DSS_VID_CLUT_1_VALUE_B_MASK (0x000000FFU)
3557 #define CSL_DSS_VID_CLUT_1_VALUE_B_SHIFT (0x00000000U)
3558 #define CSL_DSS_VID_CLUT_1_VALUE_B_MAX (0x000000FFU)
3559 
3560 #define CSL_DSS_VID_CLUT_1_VALUE_G_MASK (0x0000FF00U)
3561 #define CSL_DSS_VID_CLUT_1_VALUE_G_SHIFT (0x00000008U)
3562 #define CSL_DSS_VID_CLUT_1_VALUE_G_MAX (0x000000FFU)
3563 
3564 #define CSL_DSS_VID_CLUT_1_VALUE_R_MASK (0x00FF0000U)
3565 #define CSL_DSS_VID_CLUT_1_VALUE_R_SHIFT (0x00000010U)
3566 #define CSL_DSS_VID_CLUT_1_VALUE_R_MAX (0x000000FFU)
3567 
3568 #define CSL_DSS_VID_CLUT_1_INDEX_MASK (0xFF000000U)
3569 #define CSL_DSS_VID_CLUT_1_INDEX_SHIFT (0x00000018U)
3570 #define CSL_DSS_VID_CLUT_1_INDEX_MAX (0x000000FFU)
3571 
3572 /* CLUT_2 */
3573 
3574 #define CSL_DSS_VID_CLUT_2_VALUE_B_MASK (0x000000FFU)
3575 #define CSL_DSS_VID_CLUT_2_VALUE_B_SHIFT (0x00000000U)
3576 #define CSL_DSS_VID_CLUT_2_VALUE_B_MAX (0x000000FFU)
3577 
3578 #define CSL_DSS_VID_CLUT_2_VALUE_G_MASK (0x0000FF00U)
3579 #define CSL_DSS_VID_CLUT_2_VALUE_G_SHIFT (0x00000008U)
3580 #define CSL_DSS_VID_CLUT_2_VALUE_G_MAX (0x000000FFU)
3581 
3582 #define CSL_DSS_VID_CLUT_2_VALUE_R_MASK (0x00FF0000U)
3583 #define CSL_DSS_VID_CLUT_2_VALUE_R_SHIFT (0x00000010U)
3584 #define CSL_DSS_VID_CLUT_2_VALUE_R_MAX (0x000000FFU)
3585 
3586 #define CSL_DSS_VID_CLUT_2_INDEX_MASK (0xFF000000U)
3587 #define CSL_DSS_VID_CLUT_2_INDEX_SHIFT (0x00000018U)
3588 #define CSL_DSS_VID_CLUT_2_INDEX_MAX (0x000000FFU)
3589 
3590 /* CLUT_3 */
3591 
3592 #define CSL_DSS_VID_CLUT_3_VALUE_B_MASK (0x000000FFU)
3593 #define CSL_DSS_VID_CLUT_3_VALUE_B_SHIFT (0x00000000U)
3594 #define CSL_DSS_VID_CLUT_3_VALUE_B_MAX (0x000000FFU)
3595 
3596 #define CSL_DSS_VID_CLUT_3_VALUE_G_MASK (0x0000FF00U)
3597 #define CSL_DSS_VID_CLUT_3_VALUE_G_SHIFT (0x00000008U)
3598 #define CSL_DSS_VID_CLUT_3_VALUE_G_MAX (0x000000FFU)
3599 
3600 #define CSL_DSS_VID_CLUT_3_VALUE_R_MASK (0x00FF0000U)
3601 #define CSL_DSS_VID_CLUT_3_VALUE_R_SHIFT (0x00000010U)
3602 #define CSL_DSS_VID_CLUT_3_VALUE_R_MAX (0x000000FFU)
3603 
3604 #define CSL_DSS_VID_CLUT_3_INDEX_MASK (0xFF000000U)
3605 #define CSL_DSS_VID_CLUT_3_INDEX_SHIFT (0x00000018U)
3606 #define CSL_DSS_VID_CLUT_3_INDEX_MAX (0x000000FFU)
3607 
3608 /* CLUT_4 */
3609 
3610 #define CSL_DSS_VID_CLUT_4_VALUE_B_MASK (0x000000FFU)
3611 #define CSL_DSS_VID_CLUT_4_VALUE_B_SHIFT (0x00000000U)
3612 #define CSL_DSS_VID_CLUT_4_VALUE_B_MAX (0x000000FFU)
3613 
3614 #define CSL_DSS_VID_CLUT_4_VALUE_G_MASK (0x0000FF00U)
3615 #define CSL_DSS_VID_CLUT_4_VALUE_G_SHIFT (0x00000008U)
3616 #define CSL_DSS_VID_CLUT_4_VALUE_G_MAX (0x000000FFU)
3617 
3618 #define CSL_DSS_VID_CLUT_4_VALUE_R_MASK (0x00FF0000U)
3619 #define CSL_DSS_VID_CLUT_4_VALUE_R_SHIFT (0x00000010U)
3620 #define CSL_DSS_VID_CLUT_4_VALUE_R_MAX (0x000000FFU)
3621 
3622 #define CSL_DSS_VID_CLUT_4_INDEX_MASK (0xFF000000U)
3623 #define CSL_DSS_VID_CLUT_4_INDEX_SHIFT (0x00000018U)
3624 #define CSL_DSS_VID_CLUT_4_INDEX_MAX (0x000000FFU)
3625 
3626 /* CLUT_5 */
3627 
3628 #define CSL_DSS_VID_CLUT_5_VALUE_B_MASK (0x000000FFU)
3629 #define CSL_DSS_VID_CLUT_5_VALUE_B_SHIFT (0x00000000U)
3630 #define CSL_DSS_VID_CLUT_5_VALUE_B_MAX (0x000000FFU)
3631 
3632 #define CSL_DSS_VID_CLUT_5_VALUE_G_MASK (0x0000FF00U)
3633 #define CSL_DSS_VID_CLUT_5_VALUE_G_SHIFT (0x00000008U)
3634 #define CSL_DSS_VID_CLUT_5_VALUE_G_MAX (0x000000FFU)
3635 
3636 #define CSL_DSS_VID_CLUT_5_VALUE_R_MASK (0x00FF0000U)
3637 #define CSL_DSS_VID_CLUT_5_VALUE_R_SHIFT (0x00000010U)
3638 #define CSL_DSS_VID_CLUT_5_VALUE_R_MAX (0x000000FFU)
3639 
3640 #define CSL_DSS_VID_CLUT_5_INDEX_MASK (0xFF000000U)
3641 #define CSL_DSS_VID_CLUT_5_INDEX_SHIFT (0x00000018U)
3642 #define CSL_DSS_VID_CLUT_5_INDEX_MAX (0x000000FFU)
3643 
3644 /* CLUT_6 */
3645 
3646 #define CSL_DSS_VID_CLUT_6_VALUE_B_MASK (0x000000FFU)
3647 #define CSL_DSS_VID_CLUT_6_VALUE_B_SHIFT (0x00000000U)
3648 #define CSL_DSS_VID_CLUT_6_VALUE_B_MAX (0x000000FFU)
3649 
3650 #define CSL_DSS_VID_CLUT_6_VALUE_G_MASK (0x0000FF00U)
3651 #define CSL_DSS_VID_CLUT_6_VALUE_G_SHIFT (0x00000008U)
3652 #define CSL_DSS_VID_CLUT_6_VALUE_G_MAX (0x000000FFU)
3653 
3654 #define CSL_DSS_VID_CLUT_6_VALUE_R_MASK (0x00FF0000U)
3655 #define CSL_DSS_VID_CLUT_6_VALUE_R_SHIFT (0x00000010U)
3656 #define CSL_DSS_VID_CLUT_6_VALUE_R_MAX (0x000000FFU)
3657 
3658 #define CSL_DSS_VID_CLUT_6_INDEX_MASK (0xFF000000U)
3659 #define CSL_DSS_VID_CLUT_6_INDEX_SHIFT (0x00000018U)
3660 #define CSL_DSS_VID_CLUT_6_INDEX_MAX (0x000000FFU)
3661 
3662 /* CLUT_7 */
3663 
3664 #define CSL_DSS_VID_CLUT_7_VALUE_B_MASK (0x000000FFU)
3665 #define CSL_DSS_VID_CLUT_7_VALUE_B_SHIFT (0x00000000U)
3666 #define CSL_DSS_VID_CLUT_7_VALUE_B_MAX (0x000000FFU)
3667 
3668 #define CSL_DSS_VID_CLUT_7_VALUE_G_MASK (0x0000FF00U)
3669 #define CSL_DSS_VID_CLUT_7_VALUE_G_SHIFT (0x00000008U)
3670 #define CSL_DSS_VID_CLUT_7_VALUE_G_MAX (0x000000FFU)
3671 
3672 #define CSL_DSS_VID_CLUT_7_VALUE_R_MASK (0x00FF0000U)
3673 #define CSL_DSS_VID_CLUT_7_VALUE_R_SHIFT (0x00000010U)
3674 #define CSL_DSS_VID_CLUT_7_VALUE_R_MAX (0x000000FFU)
3675 
3676 #define CSL_DSS_VID_CLUT_7_INDEX_MASK (0xFF000000U)
3677 #define CSL_DSS_VID_CLUT_7_INDEX_SHIFT (0x00000018U)
3678 #define CSL_DSS_VID_CLUT_7_INDEX_MAX (0x000000FFU)
3679 
3680 /* CLUT_8 */
3681 
3682 #define CSL_DSS_VID_CLUT_8_VALUE_B_MASK (0x000000FFU)
3683 #define CSL_DSS_VID_CLUT_8_VALUE_B_SHIFT (0x00000000U)
3684 #define CSL_DSS_VID_CLUT_8_VALUE_B_MAX (0x000000FFU)
3685 
3686 #define CSL_DSS_VID_CLUT_8_VALUE_G_MASK (0x0000FF00U)
3687 #define CSL_DSS_VID_CLUT_8_VALUE_G_SHIFT (0x00000008U)
3688 #define CSL_DSS_VID_CLUT_8_VALUE_G_MAX (0x000000FFU)
3689 
3690 #define CSL_DSS_VID_CLUT_8_VALUE_R_MASK (0x00FF0000U)
3691 #define CSL_DSS_VID_CLUT_8_VALUE_R_SHIFT (0x00000010U)
3692 #define CSL_DSS_VID_CLUT_8_VALUE_R_MAX (0x000000FFU)
3693 
3694 #define CSL_DSS_VID_CLUT_8_INDEX_MASK (0xFF000000U)
3695 #define CSL_DSS_VID_CLUT_8_INDEX_SHIFT (0x00000018U)
3696 #define CSL_DSS_VID_CLUT_8_INDEX_MAX (0x000000FFU)
3697 
3698 /* CLUT_9 */
3699 
3700 #define CSL_DSS_VID_CLUT_9_VALUE_B_MASK (0x000000FFU)
3701 #define CSL_DSS_VID_CLUT_9_VALUE_B_SHIFT (0x00000000U)
3702 #define CSL_DSS_VID_CLUT_9_VALUE_B_MAX (0x000000FFU)
3703 
3704 #define CSL_DSS_VID_CLUT_9_VALUE_G_MASK (0x0000FF00U)
3705 #define CSL_DSS_VID_CLUT_9_VALUE_G_SHIFT (0x00000008U)
3706 #define CSL_DSS_VID_CLUT_9_VALUE_G_MAX (0x000000FFU)
3707 
3708 #define CSL_DSS_VID_CLUT_9_VALUE_R_MASK (0x00FF0000U)
3709 #define CSL_DSS_VID_CLUT_9_VALUE_R_SHIFT (0x00000010U)
3710 #define CSL_DSS_VID_CLUT_9_VALUE_R_MAX (0x000000FFU)
3711 
3712 #define CSL_DSS_VID_CLUT_9_INDEX_MASK (0xFF000000U)
3713 #define CSL_DSS_VID_CLUT_9_INDEX_SHIFT (0x00000018U)
3714 #define CSL_DSS_VID_CLUT_9_INDEX_MAX (0x000000FFU)
3715 
3716 /* CLUT_10 */
3717 
3718 #define CSL_DSS_VID_CLUT_10_VALUE_B_MASK (0x000000FFU)
3719 #define CSL_DSS_VID_CLUT_10_VALUE_B_SHIFT (0x00000000U)
3720 #define CSL_DSS_VID_CLUT_10_VALUE_B_MAX (0x000000FFU)
3721 
3722 #define CSL_DSS_VID_CLUT_10_VALUE_G_MASK (0x0000FF00U)
3723 #define CSL_DSS_VID_CLUT_10_VALUE_G_SHIFT (0x00000008U)
3724 #define CSL_DSS_VID_CLUT_10_VALUE_G_MAX (0x000000FFU)
3725 
3726 #define CSL_DSS_VID_CLUT_10_VALUE_R_MASK (0x00FF0000U)
3727 #define CSL_DSS_VID_CLUT_10_VALUE_R_SHIFT (0x00000010U)
3728 #define CSL_DSS_VID_CLUT_10_VALUE_R_MAX (0x000000FFU)
3729 
3730 #define CSL_DSS_VID_CLUT_10_INDEX_MASK (0xFF000000U)
3731 #define CSL_DSS_VID_CLUT_10_INDEX_SHIFT (0x00000018U)
3732 #define CSL_DSS_VID_CLUT_10_INDEX_MAX (0x000000FFU)
3733 
3734 /* CLUT_11 */
3735 
3736 #define CSL_DSS_VID_CLUT_11_VALUE_B_MASK (0x000000FFU)
3737 #define CSL_DSS_VID_CLUT_11_VALUE_B_SHIFT (0x00000000U)
3738 #define CSL_DSS_VID_CLUT_11_VALUE_B_MAX (0x000000FFU)
3739 
3740 #define CSL_DSS_VID_CLUT_11_VALUE_G_MASK (0x0000FF00U)
3741 #define CSL_DSS_VID_CLUT_11_VALUE_G_SHIFT (0x00000008U)
3742 #define CSL_DSS_VID_CLUT_11_VALUE_G_MAX (0x000000FFU)
3743 
3744 #define CSL_DSS_VID_CLUT_11_VALUE_R_MASK (0x00FF0000U)
3745 #define CSL_DSS_VID_CLUT_11_VALUE_R_SHIFT (0x00000010U)
3746 #define CSL_DSS_VID_CLUT_11_VALUE_R_MAX (0x000000FFU)
3747 
3748 #define CSL_DSS_VID_CLUT_11_INDEX_MASK (0xFF000000U)
3749 #define CSL_DSS_VID_CLUT_11_INDEX_SHIFT (0x00000018U)
3750 #define CSL_DSS_VID_CLUT_11_INDEX_MAX (0x000000FFU)
3751 
3752 /* CLUT_12 */
3753 
3754 #define CSL_DSS_VID_CLUT_12_VALUE_B_MASK (0x000000FFU)
3755 #define CSL_DSS_VID_CLUT_12_VALUE_B_SHIFT (0x00000000U)
3756 #define CSL_DSS_VID_CLUT_12_VALUE_B_MAX (0x000000FFU)
3757 
3758 #define CSL_DSS_VID_CLUT_12_VALUE_G_MASK (0x0000FF00U)
3759 #define CSL_DSS_VID_CLUT_12_VALUE_G_SHIFT (0x00000008U)
3760 #define CSL_DSS_VID_CLUT_12_VALUE_G_MAX (0x000000FFU)
3761 
3762 #define CSL_DSS_VID_CLUT_12_VALUE_R_MASK (0x00FF0000U)
3763 #define CSL_DSS_VID_CLUT_12_VALUE_R_SHIFT (0x00000010U)
3764 #define CSL_DSS_VID_CLUT_12_VALUE_R_MAX (0x000000FFU)
3765 
3766 #define CSL_DSS_VID_CLUT_12_INDEX_MASK (0xFF000000U)
3767 #define CSL_DSS_VID_CLUT_12_INDEX_SHIFT (0x00000018U)
3768 #define CSL_DSS_VID_CLUT_12_INDEX_MAX (0x000000FFU)
3769 
3770 /* CLUT_13 */
3771 
3772 #define CSL_DSS_VID_CLUT_13_VALUE_B_MASK (0x000000FFU)
3773 #define CSL_DSS_VID_CLUT_13_VALUE_B_SHIFT (0x00000000U)
3774 #define CSL_DSS_VID_CLUT_13_VALUE_B_MAX (0x000000FFU)
3775 
3776 #define CSL_DSS_VID_CLUT_13_VALUE_G_MASK (0x0000FF00U)
3777 #define CSL_DSS_VID_CLUT_13_VALUE_G_SHIFT (0x00000008U)
3778 #define CSL_DSS_VID_CLUT_13_VALUE_G_MAX (0x000000FFU)
3779 
3780 #define CSL_DSS_VID_CLUT_13_VALUE_R_MASK (0x00FF0000U)
3781 #define CSL_DSS_VID_CLUT_13_VALUE_R_SHIFT (0x00000010U)
3782 #define CSL_DSS_VID_CLUT_13_VALUE_R_MAX (0x000000FFU)
3783 
3784 #define CSL_DSS_VID_CLUT_13_INDEX_MASK (0xFF000000U)
3785 #define CSL_DSS_VID_CLUT_13_INDEX_SHIFT (0x00000018U)
3786 #define CSL_DSS_VID_CLUT_13_INDEX_MAX (0x000000FFU)
3787 
3788 /* CLUT_14 */
3789 
3790 #define CSL_DSS_VID_CLUT_14_VALUE_B_MASK (0x000000FFU)
3791 #define CSL_DSS_VID_CLUT_14_VALUE_B_SHIFT (0x00000000U)
3792 #define CSL_DSS_VID_CLUT_14_VALUE_B_MAX (0x000000FFU)
3793 
3794 #define CSL_DSS_VID_CLUT_14_VALUE_G_MASK (0x0000FF00U)
3795 #define CSL_DSS_VID_CLUT_14_VALUE_G_SHIFT (0x00000008U)
3796 #define CSL_DSS_VID_CLUT_14_VALUE_G_MAX (0x000000FFU)
3797 
3798 #define CSL_DSS_VID_CLUT_14_VALUE_R_MASK (0x00FF0000U)
3799 #define CSL_DSS_VID_CLUT_14_VALUE_R_SHIFT (0x00000010U)
3800 #define CSL_DSS_VID_CLUT_14_VALUE_R_MAX (0x000000FFU)
3801 
3802 #define CSL_DSS_VID_CLUT_14_INDEX_MASK (0xFF000000U)
3803 #define CSL_DSS_VID_CLUT_14_INDEX_SHIFT (0x00000018U)
3804 #define CSL_DSS_VID_CLUT_14_INDEX_MAX (0x000000FFU)
3805 
3806 /* CLUT_15 */
3807 
3808 #define CSL_DSS_VID_CLUT_15_VALUE_B_MASK (0x000000FFU)
3809 #define CSL_DSS_VID_CLUT_15_VALUE_B_SHIFT (0x00000000U)
3810 #define CSL_DSS_VID_CLUT_15_VALUE_B_MAX (0x000000FFU)
3811 
3812 #define CSL_DSS_VID_CLUT_15_VALUE_G_MASK (0x0000FF00U)
3813 #define CSL_DSS_VID_CLUT_15_VALUE_G_SHIFT (0x00000008U)
3814 #define CSL_DSS_VID_CLUT_15_VALUE_G_MAX (0x000000FFU)
3815 
3816 #define CSL_DSS_VID_CLUT_15_VALUE_R_MASK (0x00FF0000U)
3817 #define CSL_DSS_VID_CLUT_15_VALUE_R_SHIFT (0x00000010U)
3818 #define CSL_DSS_VID_CLUT_15_VALUE_R_MAX (0x000000FFU)
3819 
3820 #define CSL_DSS_VID_CLUT_15_INDEX_MASK (0xFF000000U)
3821 #define CSL_DSS_VID_CLUT_15_INDEX_SHIFT (0x00000018U)
3822 #define CSL_DSS_VID_CLUT_15_INDEX_MAX (0x000000FFU)
3823 
3824 /* SAFETY_ATTRIBUTES */
3825 
3826 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
3827 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
3828 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
3829 
3830 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
3831 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
3832 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
3833 
3834 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
3835 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
3836 
3837 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
3838 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
3839 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
3840 
3841 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
3842 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
3843 
3844 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
3845 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
3846 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
3847 
3848 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
3849 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
3850 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
3851 
3852 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE (0x0U)
3853 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
3854 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
3855 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
3856 
3857 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
3858 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
3859 #define CSL_DSS_VID_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
3860 
3861 /* SAFETY_CAPT_SIGNATURE */
3862 
3863 #define CSL_DSS_VID_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
3864 #define CSL_DSS_VID_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
3865 #define CSL_DSS_VID_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
3866 
3867 /* SAFETY_POSITION */
3868 
3869 #define CSL_DSS_VID_SAFETY_POSITION_POSX_MASK (0x00000FFFU)
3870 #define CSL_DSS_VID_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
3871 #define CSL_DSS_VID_SAFETY_POSITION_POSX_MAX (0x00000FFFU)
3872 
3873 #define CSL_DSS_VID_SAFETY_POSITION_RESERVED1_MASK (0x0000F000U)
3874 #define CSL_DSS_VID_SAFETY_POSITION_RESERVED1_SHIFT (0x0000000CU)
3875 #define CSL_DSS_VID_SAFETY_POSITION_RESERVED1_MAX (0x0000000FU)
3876 
3877 #define CSL_DSS_VID_SAFETY_POSITION_POSY_MASK (0x0FFF0000U)
3878 #define CSL_DSS_VID_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
3879 #define CSL_DSS_VID_SAFETY_POSITION_POSY_MAX (0x00000FFFU)
3880 
3881 #define CSL_DSS_VID_SAFETY_POSITION_RESERVED_MASK (0xF0000000U)
3882 #define CSL_DSS_VID_SAFETY_POSITION_RESERVED_SHIFT (0x0000001CU)
3883 #define CSL_DSS_VID_SAFETY_POSITION_RESERVED_MAX (0x0000000FU)
3884 
3885 /* SAFETY_REF_SIGNATURE */
3886 
3887 #define CSL_DSS_VID_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
3888 #define CSL_DSS_VID_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
3889 #define CSL_DSS_VID_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
3890 
3891 /* SAFETY_SIZE */
3892 
3893 #define CSL_DSS_VID_SAFETY_SIZE_SIZEX_MASK (0x00000FFFU)
3894 #define CSL_DSS_VID_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
3895 #define CSL_DSS_VID_SAFETY_SIZE_SIZEX_MAX (0x00000FFFU)
3896 
3897 #define CSL_DSS_VID_SAFETY_SIZE_RESERVED1_MASK (0x0000F000U)
3898 #define CSL_DSS_VID_SAFETY_SIZE_RESERVED1_SHIFT (0x0000000CU)
3899 #define CSL_DSS_VID_SAFETY_SIZE_RESERVED1_MAX (0x0000000FU)
3900 
3901 #define CSL_DSS_VID_SAFETY_SIZE_SIZEY_MASK (0x0FFF0000U)
3902 #define CSL_DSS_VID_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
3903 #define CSL_DSS_VID_SAFETY_SIZE_SIZEY_MAX (0x00000FFFU)
3904 
3905 #define CSL_DSS_VID_SAFETY_SIZE_RESERVED_MASK (0xF0000000U)
3906 #define CSL_DSS_VID_SAFETY_SIZE_RESERVED_SHIFT (0x0000001CU)
3907 #define CSL_DSS_VID_SAFETY_SIZE_RESERVED_MAX (0x0000000FU)
3908 
3909 /* SAFETY_LFSR_SEED */
3910 
3911 #define CSL_DSS_VID_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
3912 #define CSL_DSS_VID_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
3913 #define CSL_DSS_VID_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
3914 
3915 /* LUMAKEY */
3916 
3917 #define CSL_DSS_VID_LUMAKEY_RESERVED1_MASK (0xF0000000U)
3918 #define CSL_DSS_VID_LUMAKEY_RESERVED1_SHIFT (0x0000001CU)
3919 #define CSL_DSS_VID_LUMAKEY_RESERVED1_MAX (0x0000000FU)
3920 
3921 #define CSL_DSS_VID_LUMAKEY_LUMAKEYMAX_MASK (0x0FFF0000U)
3922 #define CSL_DSS_VID_LUMAKEY_LUMAKEYMAX_SHIFT (0x00000010U)
3923 #define CSL_DSS_VID_LUMAKEY_LUMAKEYMAX_MAX (0x00000FFFU)
3924 
3925 #define CSL_DSS_VID_LUMAKEY_RESERVED_MASK (0x0000F000U)
3926 #define CSL_DSS_VID_LUMAKEY_RESERVED_SHIFT (0x0000000CU)
3927 #define CSL_DSS_VID_LUMAKEY_RESERVED_MAX (0x0000000FU)
3928 
3929 #define CSL_DSS_VID_LUMAKEY_LUMAKEYMIN_MASK (0x00000FFFU)
3930 #define CSL_DSS_VID_LUMAKEY_LUMAKEYMIN_SHIFT (0x00000000U)
3931 #define CSL_DSS_VID_LUMAKEY_LUMAKEYMIN_MAX (0x00000FFFU)
3932 
3933 /**************************************************************************
3934 * Hardware Region : OVR1 Registers
3935 **************************************************************************/
3936 
3937 
3938 /**************************************************************************
3939 * Register Overlay Structure
3940 **************************************************************************/
3941 
3942 typedef struct {
3943  volatile uint32_t CONFIG; /* CONFIG */
3944  volatile uint8_t Resv_8[4];
3945  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
3946  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
3947  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
3948  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
3949  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
3950  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
3951  volatile uint32_t ATTRIBUTES[4U]; /* ATTRIBUTES 0..3 */
3953 
3954 
3955 /**************************************************************************
3956 * Register Macros
3957 **************************************************************************/
3958 
3959 #define CSL_DSS_OVR1_CONFIG (0x00000000U)
3960 #define CSL_DSS_OVR1_DEFAULT_COLOR (0x00000008U)
3961 #define CSL_DSS_OVR1_DEFAULT_COLOR2 (0x0000000CU)
3962 #define CSL_DSS_OVR1_TRANS_COLOR_MAX (0x00000010U)
3963 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2 (0x00000014U)
3964 #define CSL_DSS_OVR1_TRANS_COLOR_MIN (0x00000018U)
3965 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2 (0x0000001CU)
3966 #define CSL_DSS_OVR1_ATTRIBUTES(index) (0x00000020U+((uint32_t)(index)*0x4U))
3967 
3968 /**************************************************************************
3969 * Field Definition Macros
3970 **************************************************************************/
3971 
3972 
3973 /* CONFIG */
3974 
3975 #define CSL_DSS_OVR1_CONFIG_RESERVED6_MASK (0x00000001U)
3976 #define CSL_DSS_OVR1_CONFIG_RESERVED6_SHIFT (0x00000000U)
3977 #define CSL_DSS_OVR1_CONFIG_RESERVED6_MAX (0x00000001U)
3978 
3979 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_MASK (0x00000002U)
3980 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_SHIFT (0x00000001U)
3981 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_MAX (0x00000001U)
3982 
3983 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
3984 #define CSL_DSS_OVR1_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
3985 
3986 #define CSL_DSS_OVR1_CONFIG_RESERVED_MASK (0x000003FCU)
3987 #define CSL_DSS_OVR1_CONFIG_RESERVED_SHIFT (0x00000002U)
3988 #define CSL_DSS_OVR1_CONFIG_RESERVED_MAX (0x000000FFU)
3989 
3990 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
3991 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
3992 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
3993 
3994 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
3995 #define CSL_DSS_OVR1_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
3996 
3997 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
3998 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
3999 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
4000 
4001 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
4002 #define CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
4003 
4004 #define CSL_DSS_OVR1_CONFIG_RESERVED2_MASK (0x00001000U)
4005 #define CSL_DSS_OVR1_CONFIG_RESERVED2_SHIFT (0x0000000CU)
4006 #define CSL_DSS_OVR1_CONFIG_RESERVED2_MAX (0x00000001U)
4007 
4008 #define CSL_DSS_OVR1_CONFIG_RESERVED3_MASK (0x00002000U)
4009 #define CSL_DSS_OVR1_CONFIG_RESERVED3_SHIFT (0x0000000DU)
4010 #define CSL_DSS_OVR1_CONFIG_RESERVED3_MAX (0x00000001U)
4011 
4012 #define CSL_DSS_OVR1_CONFIG_RESERVED1_MASK (0xFFFFC000U)
4013 #define CSL_DSS_OVR1_CONFIG_RESERVED1_SHIFT (0x0000000EU)
4014 #define CSL_DSS_OVR1_CONFIG_RESERVED1_MAX (0x0003FFFFU)
4015 
4016 /* DEFAULT_COLOR */
4017 
4018 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
4019 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
4020 #define CSL_DSS_OVR1_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
4021 
4022 /* DEFAULT_COLOR2 */
4023 
4024 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
4025 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
4026 #define CSL_DSS_OVR1_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
4027 
4028 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
4029 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
4030 #define CSL_DSS_OVR1_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
4031 
4032 /* TRANS_COLOR_MAX */
4033 
4034 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
4035 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
4036 #define CSL_DSS_OVR1_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
4037 
4038 /* TRANS_COLOR_MAX2 */
4039 
4040 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
4041 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
4042 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
4043 
4044 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
4045 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
4046 #define CSL_DSS_OVR1_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
4047 
4048 /* TRANS_COLOR_MIN */
4049 
4050 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
4051 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
4052 #define CSL_DSS_OVR1_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
4053 
4054 /* TRANS_COLOR_MIN2 */
4055 
4056 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
4057 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
4058 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
4059 
4060 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
4061 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
4062 #define CSL_DSS_OVR1_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
4063 
4064 /* ATTRIBUTES */
4065 
4066 #define CSL_DSS_OVR1_ATTRIBUTES_POSX_MASK (0x0003FFC0U)
4067 #define CSL_DSS_OVR1_ATTRIBUTES_POSX_SHIFT (0x00000006U)
4068 #define CSL_DSS_OVR1_ATTRIBUTES_POSX_MAX (0x00000FFFU)
4069 
4070 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED_MASK (0x00040000U)
4071 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED_SHIFT (0x00000012U)
4072 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED_MAX (0x00000001U)
4073 
4074 #define CSL_DSS_OVR1_ATTRIBUTES_POSY_MASK (0x7FF80000U)
4075 #define CSL_DSS_OVR1_ATTRIBUTES_POSY_SHIFT (0x00000013U)
4076 #define CSL_DSS_OVR1_ATTRIBUTES_POSY_MAX (0x00000FFFU)
4077 
4078 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED1_MASK (0x80000000U)
4079 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED1_SHIFT (0x0000001FU)
4080 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED1_MAX (0x00000001U)
4081 
4082 #define CSL_DSS_OVR1_ATTRIBUTES_ENABLE_MASK (0x00000001U)
4083 #define CSL_DSS_OVR1_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
4084 #define CSL_DSS_OVR1_ATTRIBUTES_ENABLE_MAX (0x00000001U)
4085 
4086 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_MASK (0x0000001EU)
4087 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_SHIFT (0x00000001U)
4088 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_MAX (0x0000000FU)
4089 
4090 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VID (0x0U)
4091 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VIDL1 (0x1U)
4092 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VIDL2 (0x2U)
4093 #define CSL_DSS_OVR1_ATTRIBUTES_CHANNELIN_VAL_VIDL3 (0x3U)
4094 
4095 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED2_MASK (0x00000020U)
4096 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED2_SHIFT (0x00000005U)
4097 #define CSL_DSS_OVR1_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
4098 
4099 /**************************************************************************
4100 * Hardware Region : OVR2 Registers
4101 **************************************************************************/
4102 
4103 
4104 /**************************************************************************
4105 * Register Overlay Structure
4106 **************************************************************************/
4107 
4108 typedef struct {
4109  volatile uint32_t CONFIG; /* CONFIG */
4110  volatile uint8_t Resv_8[4];
4111  volatile uint32_t DEFAULT_COLOR; /* DEFAULT_COLOR */
4112  volatile uint32_t DEFAULT_COLOR2; /* DEFAULT_COLOR2 */
4113  volatile uint32_t TRANS_COLOR_MAX; /* TRANS_COLOR_MAX */
4114  volatile uint32_t TRANS_COLOR_MAX2; /* TRANS_COLOR_MAX2 */
4115  volatile uint32_t TRANS_COLOR_MIN; /* TRANS_COLOR_MIN */
4116  volatile uint32_t TRANS_COLOR_MIN2; /* TRANS_COLOR_MIN2 */
4117  volatile uint32_t ATTRIBUTES[4U]; /* ATTRIBUTES 0..3 */
4119 
4120 
4121 /**************************************************************************
4122 * Register Macros
4123 **************************************************************************/
4124 
4125 #define CSL_DSS_OVR2_CONFIG (0x00000000U)
4126 #define CSL_DSS_OVR2_DEFAULT_COLOR (0x00000008U)
4127 #define CSL_DSS_OVR2_DEFAULT_COLOR2 (0x0000000CU)
4128 #define CSL_DSS_OVR2_TRANS_COLOR_MAX (0x00000010U)
4129 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2 (0x00000014U)
4130 #define CSL_DSS_OVR2_TRANS_COLOR_MIN (0x00000018U)
4131 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2 (0x0000001CU)
4132 #define CSL_DSS_OVR2_ATTRIBUTES(index) (0x00000020U+((uint32_t)(index)*0x4U))
4133 
4134 /**************************************************************************
4135 * Field Definition Macros
4136 **************************************************************************/
4137 
4138 
4139 /* CONFIG */
4140 
4141 #define CSL_DSS_OVR2_CONFIG_RESERVED6_MASK (0x00000001U)
4142 #define CSL_DSS_OVR2_CONFIG_RESERVED6_SHIFT (0x00000000U)
4143 #define CSL_DSS_OVR2_CONFIG_RESERVED6_MAX (0x00000001U)
4144 
4145 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_MASK (0x00000002U)
4146 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_SHIFT (0x00000001U)
4147 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_MAX (0x00000001U)
4148 
4149 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_VAL_COLORBARDIS (0x0U)
4150 #define CSL_DSS_OVR2_CONFIG_COLORBAREN_VAL_COLORBAREN (0x1U)
4151 
4152 #define CSL_DSS_OVR2_CONFIG_RESERVED_MASK (0x000003FCU)
4153 #define CSL_DSS_OVR2_CONFIG_RESERVED_SHIFT (0x00000002U)
4154 #define CSL_DSS_OVR2_CONFIG_RESERVED_MAX (0x000000FFU)
4155 
4156 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_MASK (0x00000400U)
4157 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_SHIFT (0x0000000AU)
4158 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_MAX (0x00000001U)
4159 
4160 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_VAL_DISTCK (0x0U)
4161 #define CSL_DSS_OVR2_CONFIG_TCKLCDENABLE_VAL_ENBTCK (0x1U)
4162 
4163 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_MASK (0x00000800U)
4164 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_SHIFT (0x0000000BU)
4165 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_MAX (0x00000001U)
4166 
4167 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_VAL_GDTK (0x0U)
4168 #define CSL_DSS_OVR2_CONFIG_TCKLCDSELECTION_VAL_VSTK (0x1U)
4169 
4170 #define CSL_DSS_OVR2_CONFIG_RESERVED2_MASK (0x00001000U)
4171 #define CSL_DSS_OVR2_CONFIG_RESERVED2_SHIFT (0x0000000CU)
4172 #define CSL_DSS_OVR2_CONFIG_RESERVED2_MAX (0x00000001U)
4173 
4174 #define CSL_DSS_OVR2_CONFIG_RESERVED3_MASK (0x00002000U)
4175 #define CSL_DSS_OVR2_CONFIG_RESERVED3_SHIFT (0x0000000DU)
4176 #define CSL_DSS_OVR2_CONFIG_RESERVED3_MAX (0x00000001U)
4177 
4178 #define CSL_DSS_OVR2_CONFIG_RESERVED1_MASK (0xFFFFC000U)
4179 #define CSL_DSS_OVR2_CONFIG_RESERVED1_SHIFT (0x0000000EU)
4180 #define CSL_DSS_OVR2_CONFIG_RESERVED1_MAX (0x0003FFFFU)
4181 
4182 /* DEFAULT_COLOR */
4183 
4184 #define CSL_DSS_OVR2_DEFAULT_COLOR_DEFAULTCOLOR_MASK (0xFFFFFFFFU)
4185 #define CSL_DSS_OVR2_DEFAULT_COLOR_DEFAULTCOLOR_SHIFT (0x00000000U)
4186 #define CSL_DSS_OVR2_DEFAULT_COLOR_DEFAULTCOLOR_MAX (0xFFFFFFFFU)
4187 
4188 /* DEFAULT_COLOR2 */
4189 
4190 #define CSL_DSS_OVR2_DEFAULT_COLOR2_DEFAULTCOLOR_MASK (0x0000FFFFU)
4191 #define CSL_DSS_OVR2_DEFAULT_COLOR2_DEFAULTCOLOR_SHIFT (0x00000000U)
4192 #define CSL_DSS_OVR2_DEFAULT_COLOR2_DEFAULTCOLOR_MAX (0x0000FFFFU)
4193 
4194 #define CSL_DSS_OVR2_DEFAULT_COLOR2_RESERVED_MASK (0xFFFF0000U)
4195 #define CSL_DSS_OVR2_DEFAULT_COLOR2_RESERVED_SHIFT (0x00000010U)
4196 #define CSL_DSS_OVR2_DEFAULT_COLOR2_RESERVED_MAX (0x0000FFFFU)
4197 
4198 /* TRANS_COLOR_MAX */
4199 
4200 #define CSL_DSS_OVR2_TRANS_COLOR_MAX_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
4201 #define CSL_DSS_OVR2_TRANS_COLOR_MAX_TRANSCOLORKEY_SHIFT (0x00000000U)
4202 #define CSL_DSS_OVR2_TRANS_COLOR_MAX_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
4203 
4204 /* TRANS_COLOR_MAX2 */
4205 
4206 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_TRANSCOLORKEY_MASK (0x0000000FU)
4207 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_TRANSCOLORKEY_SHIFT (0x00000000U)
4208 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_TRANSCOLORKEY_MAX (0x0000000FU)
4209 
4210 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_RESERVED_MASK (0xFFFFFFF0U)
4211 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_RESERVED_SHIFT (0x00000004U)
4212 #define CSL_DSS_OVR2_TRANS_COLOR_MAX2_RESERVED_MAX (0x0FFFFFFFU)
4213 
4214 /* TRANS_COLOR_MIN */
4215 
4216 #define CSL_DSS_OVR2_TRANS_COLOR_MIN_TRANSCOLORKEY_MASK (0xFFFFFFFFU)
4217 #define CSL_DSS_OVR2_TRANS_COLOR_MIN_TRANSCOLORKEY_SHIFT (0x00000000U)
4218 #define CSL_DSS_OVR2_TRANS_COLOR_MIN_TRANSCOLORKEY_MAX (0xFFFFFFFFU)
4219 
4220 /* TRANS_COLOR_MIN2 */
4221 
4222 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_TRANSCOLORKEY_MASK (0x0000000FU)
4223 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_TRANSCOLORKEY_SHIFT (0x00000000U)
4224 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_TRANSCOLORKEY_MAX (0x0000000FU)
4225 
4226 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_RESERVED_MASK (0xFFFFFFF0U)
4227 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_RESERVED_SHIFT (0x00000004U)
4228 #define CSL_DSS_OVR2_TRANS_COLOR_MIN2_RESERVED_MAX (0x0FFFFFFFU)
4229 
4230 /* ATTRIBUTES */
4231 
4232 #define CSL_DSS_OVR2_ATTRIBUTES_POSX_MASK (0x0003FFC0U)
4233 #define CSL_DSS_OVR2_ATTRIBUTES_POSX_SHIFT (0x00000006U)
4234 #define CSL_DSS_OVR2_ATTRIBUTES_POSX_MAX (0x00000FFFU)
4235 
4236 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED_MASK (0x00040000U)
4237 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED_SHIFT (0x00000012U)
4238 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED_MAX (0x00000001U)
4239 
4240 #define CSL_DSS_OVR2_ATTRIBUTES_POSY_MASK (0x7FF80000U)
4241 #define CSL_DSS_OVR2_ATTRIBUTES_POSY_SHIFT (0x00000013U)
4242 #define CSL_DSS_OVR2_ATTRIBUTES_POSY_MAX (0x00000FFFU)
4243 
4244 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED1_MASK (0x80000000U)
4245 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED1_SHIFT (0x0000001FU)
4246 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED1_MAX (0x00000001U)
4247 
4248 #define CSL_DSS_OVR2_ATTRIBUTES_ENABLE_MASK (0x00000001U)
4249 #define CSL_DSS_OVR2_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
4250 #define CSL_DSS_OVR2_ATTRIBUTES_ENABLE_MAX (0x00000001U)
4251 
4252 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_MASK (0x0000001EU)
4253 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_SHIFT (0x00000001U)
4254 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_MAX (0x0000000FU)
4255 
4256 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VID (0x0U)
4257 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VIDL1 (0x1U)
4258 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VIDL2 (0x2U)
4259 #define CSL_DSS_OVR2_ATTRIBUTES_CHANNELIN_VAL_VIDL3 (0x3U)
4260 
4261 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED2_MASK (0x00000020U)
4262 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED2_SHIFT (0x00000005U)
4263 #define CSL_DSS_OVR2_ATTRIBUTES_RESERVED2_MAX (0x00000001U)
4264 
4265 /**************************************************************************
4266 * Hardware Region : VP1 Registers
4267 **************************************************************************/
4268 
4269 
4270 /**************************************************************************
4271 * Register Overlay Structure
4272 **************************************************************************/
4273 
4274 typedef struct {
4275  volatile uint32_t CONFIG; /* CONFIG */
4276  volatile uint32_t CONTROL; /* CONTROL */
4277  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
4278  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
4279  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
4280  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
4281  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
4282  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
4283  volatile uint8_t Resv_68[36];
4284  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
4285  volatile uint8_t Resv_76[4];
4286  volatile uint32_t POL_FREQ; /* POL_FREQ */
4287  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
4288  volatile uint32_t TIMING_H; /* TIMING_H */
4289  volatile uint32_t TIMING_V; /* TIMING_V */
4290  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
4291  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
4292  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
4293  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
4294  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
4295  volatile uint32_t SAFETY_ATTRIBUTES[4U]; /* SAFETY_ATTRIBUTES 0..3 */
4296  volatile uint8_t Resv_144[16];
4297  volatile uint32_t SAFETY_CAPT_SIGNATURE[4U]; /* SAFETY_CAPT_SIGNATURE 0..3 */
4298  volatile uint8_t Resv_176[16];
4299  volatile uint32_t SAFETY_POSITION[4U]; /* SAFETY_POSITION 0..3 */
4300  volatile uint8_t Resv_208[16];
4301  volatile uint32_t SAFETY_REF_SIGNATURE[4U]; /* SAFETY_REF_SIGNATURE 0..3 */
4302  volatile uint8_t Resv_240[16];
4303  volatile uint32_t SAFETY_SIZE[4U]; /* SAFETY_SIZE 0..3 */
4304  volatile uint8_t Resv_272[16];
4305  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
4306  volatile uint8_t Resv_288[12];
4307  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
4308  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
4309  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
4310  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
4311  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
4312  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
4313  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
4314  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
4315  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
4316  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
4317  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
4318  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
4319  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
4320  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
4321  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
4322  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
4323  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
4324  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
4325  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
4326 } CSL_dss_vp1Regs;
4327 
4328 
4329 /**************************************************************************
4330 * Register Macros
4331 **************************************************************************/
4332 
4333 #define CSL_DSS_VP1_CONFIG (0x00000000U)
4334 #define CSL_DSS_VP1_CONTROL (0x00000004U)
4335 #define CSL_DSS_VP1_CSC_COEF0 (0x00000008U)
4336 #define CSL_DSS_VP1_CSC_COEF1 (0x0000000CU)
4337 #define CSL_DSS_VP1_CSC_COEF2 (0x00000010U)
4338 #define CSL_DSS_VP1_DATA_CYCLE_0 (0x00000014U)
4339 #define CSL_DSS_VP1_DATA_CYCLE_1 (0x00000018U)
4340 #define CSL_DSS_VP1_DATA_CYCLE_2 (0x0000001CU)
4341 #define CSL_DSS_VP1_LINE_NUMBER (0x00000044U)
4342 #define CSL_DSS_VP1_POL_FREQ (0x0000004CU)
4343 #define CSL_DSS_VP1_SIZE_SCREEN (0x00000050U)
4344 #define CSL_DSS_VP1_TIMING_H (0x00000054U)
4345 #define CSL_DSS_VP1_TIMING_V (0x00000058U)
4346 #define CSL_DSS_VP1_CSC_COEF3 (0x0000005CU)
4347 #define CSL_DSS_VP1_CSC_COEF4 (0x00000060U)
4348 #define CSL_DSS_VP1_CSC_COEF5 (0x00000064U)
4349 #define CSL_DSS_VP1_CSC_COEF6 (0x00000068U)
4350 #define CSL_DSS_VP1_CSC_COEF7 (0x0000006CU)
4351 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
4352 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
4353 #define CSL_DSS_VP1_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
4354 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
4355 #define CSL_DSS_VP1_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
4356 #define CSL_DSS_VP1_SAFETY_LFSR_SEED (0x00000110U)
4357 #define CSL_DSS_VP1_GAMMA_TABLE_0 (0x00000120U)
4358 #define CSL_DSS_VP1_GAMMA_TABLE_1 (0x00000124U)
4359 #define CSL_DSS_VP1_GAMMA_TABLE_2 (0x00000128U)
4360 #define CSL_DSS_VP1_GAMMA_TABLE_3 (0x0000012CU)
4361 #define CSL_DSS_VP1_GAMMA_TABLE_4 (0x00000130U)
4362 #define CSL_DSS_VP1_GAMMA_TABLE_5 (0x00000134U)
4363 #define CSL_DSS_VP1_GAMMA_TABLE_6 (0x00000138U)
4364 #define CSL_DSS_VP1_GAMMA_TABLE_7 (0x0000013CU)
4365 #define CSL_DSS_VP1_GAMMA_TABLE_8 (0x00000140U)
4366 #define CSL_DSS_VP1_GAMMA_TABLE_9 (0x00000144U)
4367 #define CSL_DSS_VP1_GAMMA_TABLE_10 (0x00000148U)
4368 #define CSL_DSS_VP1_GAMMA_TABLE_11 (0x0000014CU)
4369 #define CSL_DSS_VP1_GAMMA_TABLE_12 (0x00000150U)
4370 #define CSL_DSS_VP1_GAMMA_TABLE_13 (0x00000154U)
4371 #define CSL_DSS_VP1_GAMMA_TABLE_14 (0x00000158U)
4372 #define CSL_DSS_VP1_GAMMA_TABLE_15 (0x0000015CU)
4373 #define CSL_DSS_VP1_DSS_OLDI_CFG (0x00000160U)
4374 #define CSL_DSS_VP1_DSS_OLDI_STATUS (0x00000164U)
4375 #define CSL_DSS_VP1_DSS_OLDI_LB (0x00000168U)
4376 
4377 /**************************************************************************
4378 * Field Definition Macros
4379 **************************************************************************/
4380 
4381 
4382 /* CONFIG */
4383 
4384 #define CSL_DSS_VP1_CONFIG_PIXELGATED_MASK (0x00000001U)
4385 #define CSL_DSS_VP1_CONFIG_PIXELGATED_SHIFT (0x00000000U)
4386 #define CSL_DSS_VP1_CONFIG_PIXELGATED_MAX (0x00000001U)
4387 
4388 #define CSL_DSS_VP1_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
4389 #define CSL_DSS_VP1_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
4390 
4391 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
4392 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
4393 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
4394 
4395 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
4396 #define CSL_DSS_VP1_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
4397 
4398 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_MASK (0x00000004U)
4399 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
4400 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_MAX (0x00000001U)
4401 
4402 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
4403 #define CSL_DSS_VP1_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
4404 
4405 #define CSL_DSS_VP1_CONFIG_HDMIMODE_MASK (0x00000008U)
4406 #define CSL_DSS_VP1_CONFIG_HDMIMODE_SHIFT (0x00000003U)
4407 #define CSL_DSS_VP1_CONFIG_HDMIMODE_MAX (0x00000001U)
4408 
4409 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
4410 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
4411 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
4412 
4413 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
4414 #define CSL_DSS_VP1_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
4415 
4416 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
4417 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
4418 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
4419 
4420 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
4421 #define CSL_DSS_VP1_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
4422 
4423 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_MASK (0x00000040U)
4424 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
4425 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_MAX (0x00000001U)
4426 
4427 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
4428 #define CSL_DSS_VP1_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
4429 
4430 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_MASK (0x00000080U)
4431 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
4432 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_MAX (0x00000001U)
4433 
4434 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
4435 #define CSL_DSS_VP1_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
4436 
4437 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
4438 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
4439 #define CSL_DSS_VP1_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
4440 
4441 #define CSL_DSS_VP1_CONFIG_RESERVED1_MASK (0x00007E00U)
4442 #define CSL_DSS_VP1_CONFIG_RESERVED1_SHIFT (0x00000009U)
4443 #define CSL_DSS_VP1_CONFIG_RESERVED1_MAX (0x0000003FU)
4444 
4445 #define CSL_DSS_VP1_CONFIG_CPR_MASK (0x00008000U)
4446 #define CSL_DSS_VP1_CONFIG_CPR_SHIFT (0x0000000FU)
4447 #define CSL_DSS_VP1_CONFIG_CPR_MAX (0x00000001U)
4448 
4449 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
4450 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
4451 #define CSL_DSS_VP1_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
4452 
4453 #define CSL_DSS_VP1_CONFIG_RESERVED2_MASK (0x000E0000U)
4454 #define CSL_DSS_VP1_CONFIG_RESERVED2_SHIFT (0x00000011U)
4455 #define CSL_DSS_VP1_CONFIG_RESERVED2_MAX (0x00000007U)
4456 
4457 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_MASK (0x00100000U)
4458 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
4459 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_MAX (0x00000001U)
4460 
4461 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
4462 #define CSL_DSS_VP1_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
4463 
4464 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_MASK (0x00200000U)
4465 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
4466 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_MAX (0x00000001U)
4467 
4468 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
4469 #define CSL_DSS_VP1_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
4470 
4471 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
4472 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
4473 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
4474 
4475 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
4476 #define CSL_DSS_VP1_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
4477 
4478 #define CSL_DSS_VP1_CONFIG_FIDFIRST_MASK (0x00800000U)
4479 #define CSL_DSS_VP1_CONFIG_FIDFIRST_SHIFT (0x00000017U)
4480 #define CSL_DSS_VP1_CONFIG_FIDFIRST_MAX (0x00000001U)
4481 
4482 #define CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
4483 #define CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD (0x1U)
4484 
4485 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
4486 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
4487 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
4488 
4489 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
4490 #define CSL_DSS_VP1_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
4491 
4492 #define CSL_DSS_VP1_CONFIG_FULLRANGE_MASK (0x02000000U)
4493 #define CSL_DSS_VP1_CONFIG_FULLRANGE_SHIFT (0x00000019U)
4494 #define CSL_DSS_VP1_CONFIG_FULLRANGE_MAX (0x00000001U)
4495 
4496 #define CSL_DSS_VP1_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
4497 #define CSL_DSS_VP1_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
4498 
4499 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_MASK (0x04000000U)
4500 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
4501 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_MAX (0x00000001U)
4502 
4503 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
4504 #define CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
4505 
4506 #define CSL_DSS_VP1_CONFIG_RESERVED3_MASK (0xF8000000U)
4507 #define CSL_DSS_VP1_CONFIG_RESERVED3_SHIFT (0x0000001BU)
4508 #define CSL_DSS_VP1_CONFIG_RESERVED3_MAX (0x0000001FU)
4509 
4510 /* CONTROL */
4511 
4512 #define CSL_DSS_VP1_CONTROL_ENABLE_MASK (0x00000001U)
4513 #define CSL_DSS_VP1_CONTROL_ENABLE_SHIFT (0x00000000U)
4514 #define CSL_DSS_VP1_CONTROL_ENABLE_MAX (0x00000001U)
4515 
4516 #define CSL_DSS_VP1_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
4517 #define CSL_DSS_VP1_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
4518 
4519 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
4520 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
4521 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
4522 
4523 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
4524 #define CSL_DSS_VP1_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
4525 
4526 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_MASK (0x00000004U)
4527 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
4528 #define CSL_DSS_VP1_CONTROL_MONOCOLOR_MAX (0x00000001U)
4529 
4530 #define CSL_DSS_VP1_CONTROL_STN_MASK (0x00000008U)
4531 #define CSL_DSS_VP1_CONTROL_STN_SHIFT (0x00000003U)
4532 #define CSL_DSS_VP1_CONTROL_STN_MAX (0x00000001U)
4533 
4534 #define CSL_DSS_VP1_CONTROL_M8B_MASK (0x00000010U)
4535 #define CSL_DSS_VP1_CONTROL_M8B_SHIFT (0x00000004U)
4536 #define CSL_DSS_VP1_CONTROL_M8B_MAX (0x00000001U)
4537 
4538 #define CSL_DSS_VP1_CONTROL_GOBIT_MASK (0x00000020U)
4539 #define CSL_DSS_VP1_CONTROL_GOBIT_SHIFT (0x00000005U)
4540 #define CSL_DSS_VP1_CONTROL_GOBIT_MAX (0x00000001U)
4541 
4542 #define CSL_DSS_VP1_CONTROL_GOBIT_VAL_HFUISR (0x0U)
4543 #define CSL_DSS_VP1_CONTROL_GOBIT_VAL_UFPSR (0x1U)
4544 
4545 #define CSL_DSS_VP1_CONTROL_DPIENABLE_MASK (0x00000040U)
4546 #define CSL_DSS_VP1_CONTROL_DPIENABLE_SHIFT (0x00000006U)
4547 #define CSL_DSS_VP1_CONTROL_DPIENABLE_MAX (0x00000001U)
4548 
4549 #define CSL_DSS_VP1_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
4550 #define CSL_DSS_VP1_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
4551 
4552 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_MASK (0x00000080U)
4553 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
4554 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_MAX (0x00000001U)
4555 
4556 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
4557 #define CSL_DSS_VP1_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
4558 
4559 #define CSL_DSS_VP1_CONTROL_DATALINES_MASK (0x00000700U)
4560 #define CSL_DSS_VP1_CONTROL_DATALINES_SHIFT (0x00000008U)
4561 #define CSL_DSS_VP1_CONTROL_DATALINES_MAX (0x00000007U)
4562 
4563 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
4564 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
4565 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
4566 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
4567 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
4568 #define CSL_DSS_VP1_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
4569 
4570 #define CSL_DSS_VP1_CONTROL_STALLMODE_MASK (0x00000800U)
4571 #define CSL_DSS_VP1_CONTROL_STALLMODE_SHIFT (0x0000000BU)
4572 #define CSL_DSS_VP1_CONTROL_STALLMODE_MAX (0x00000001U)
4573 
4574 #define CSL_DSS_VP1_CONTROL_RESERVED6_MASK (0x00001000U)
4575 #define CSL_DSS_VP1_CONTROL_RESERVED6_SHIFT (0x0000000CU)
4576 #define CSL_DSS_VP1_CONTROL_RESERVED6_MAX (0x00000001U)
4577 
4578 #define CSL_DSS_VP1_CONTROL_RESERVED3_MASK (0x00002000U)
4579 #define CSL_DSS_VP1_CONTROL_RESERVED3_SHIFT (0x0000000DU)
4580 #define CSL_DSS_VP1_CONTROL_RESERVED3_MAX (0x00000001U)
4581 
4582 #define CSL_DSS_VP1_CONTROL_HT_MASK (0x0001C000U)
4583 #define CSL_DSS_VP1_CONTROL_HT_SHIFT (0x0000000EU)
4584 #define CSL_DSS_VP1_CONTROL_HT_MAX (0x00000007U)
4585 
4586 #define CSL_DSS_VP1_CONTROL_RESERVED1_MASK (0x000E0000U)
4587 #define CSL_DSS_VP1_CONTROL_RESERVED1_SHIFT (0x00000011U)
4588 #define CSL_DSS_VP1_CONTROL_RESERVED1_MAX (0x00000007U)
4589 
4590 #define CSL_DSS_VP1_CONTROL_TDMENABLE_MASK (0x00100000U)
4591 #define CSL_DSS_VP1_CONTROL_TDMENABLE_SHIFT (0x00000014U)
4592 #define CSL_DSS_VP1_CONTROL_TDMENABLE_MAX (0x00000001U)
4593 
4594 #define CSL_DSS_VP1_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
4595 #define CSL_DSS_VP1_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
4596 
4597 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
4598 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
4599 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
4600 
4601 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
4602 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
4603 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
4604 #define CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
4605 
4606 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
4607 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
4608 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
4609 
4610 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
4611 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
4612 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
4613 #define CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
4614 
4615 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
4616 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
4617 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
4618 
4619 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
4620 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
4621 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
4622 #define CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
4623 
4624 #define CSL_DSS_VP1_CONTROL_RESERVED_MASK (0x38000000U)
4625 #define CSL_DSS_VP1_CONTROL_RESERVED_SHIFT (0x0000001BU)
4626 #define CSL_DSS_VP1_CONTROL_RESERVED_MAX (0x00000007U)
4627 
4628 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
4629 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
4630 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
4631 
4632 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
4633 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
4634 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
4635 #define CSL_DSS_VP1_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
4636 
4637 /* CSC_COEF0 */
4638 
4639 #define CSL_DSS_VP1_CSC_COEF0_C00_MASK (0x000007FFU)
4640 #define CSL_DSS_VP1_CSC_COEF0_C00_SHIFT (0x00000000U)
4641 #define CSL_DSS_VP1_CSC_COEF0_C00_MAX (0x000007FFU)
4642 
4643 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
4644 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
4645 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
4646 
4647 #define CSL_DSS_VP1_CSC_COEF0_C01_MASK (0x07FF0000U)
4648 #define CSL_DSS_VP1_CSC_COEF0_C01_SHIFT (0x00000010U)
4649 #define CSL_DSS_VP1_CSC_COEF0_C01_MAX (0x000007FFU)
4650 
4651 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
4652 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
4653 #define CSL_DSS_VP1_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
4654 
4655 /* CSC_COEF1 */
4656 
4657 #define CSL_DSS_VP1_CSC_COEF1_C02_MASK (0x000007FFU)
4658 #define CSL_DSS_VP1_CSC_COEF1_C02_SHIFT (0x00000000U)
4659 #define CSL_DSS_VP1_CSC_COEF1_C02_MAX (0x000007FFU)
4660 
4661 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
4662 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
4663 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
4664 
4665 #define CSL_DSS_VP1_CSC_COEF1_C10_MASK (0x07FF0000U)
4666 #define CSL_DSS_VP1_CSC_COEF1_C10_SHIFT (0x00000010U)
4667 #define CSL_DSS_VP1_CSC_COEF1_C10_MAX (0x000007FFU)
4668 
4669 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
4670 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
4671 #define CSL_DSS_VP1_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
4672 
4673 /* CSC_COEF2 */
4674 
4675 #define CSL_DSS_VP1_CSC_COEF2_C11_MASK (0x000007FFU)
4676 #define CSL_DSS_VP1_CSC_COEF2_C11_SHIFT (0x00000000U)
4677 #define CSL_DSS_VP1_CSC_COEF2_C11_MAX (0x000007FFU)
4678 
4679 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
4680 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
4681 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
4682 
4683 #define CSL_DSS_VP1_CSC_COEF2_C12_MASK (0x07FF0000U)
4684 #define CSL_DSS_VP1_CSC_COEF2_C12_SHIFT (0x00000010U)
4685 #define CSL_DSS_VP1_CSC_COEF2_C12_MAX (0x000007FFU)
4686 
4687 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
4688 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
4689 #define CSL_DSS_VP1_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
4690 
4691 /* DATA_CYCLE_0 */
4692 
4693 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
4694 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
4695 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
4696 
4697 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
4698 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
4699 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
4700 
4701 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
4702 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
4703 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
4704 
4705 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
4706 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
4707 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
4708 
4709 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
4710 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
4711 #define CSL_DSS_VP1_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
4712 
4713 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
4714 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
4715 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
4716 
4717 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
4718 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
4719 #define CSL_DSS_VP1_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
4720 
4721 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
4722 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
4723 #define CSL_DSS_VP1_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
4724 
4725 /* DATA_CYCLE_1 */
4726 
4727 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
4728 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
4729 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
4730 
4731 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
4732 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
4733 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
4734 
4735 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
4736 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
4737 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
4738 
4739 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
4740 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
4741 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
4742 
4743 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
4744 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
4745 #define CSL_DSS_VP1_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
4746 
4747 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
4748 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
4749 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
4750 
4751 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
4752 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
4753 #define CSL_DSS_VP1_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
4754 
4755 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
4756 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
4757 #define CSL_DSS_VP1_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
4758 
4759 /* DATA_CYCLE_2 */
4760 
4761 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
4762 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
4763 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
4764 
4765 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
4766 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
4767 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
4768 
4769 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
4770 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
4771 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
4772 
4773 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
4774 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
4775 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
4776 
4777 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
4778 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
4779 #define CSL_DSS_VP1_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
4780 
4781 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
4782 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
4783 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
4784 
4785 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
4786 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
4787 #define CSL_DSS_VP1_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
4788 
4789 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
4790 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
4791 #define CSL_DSS_VP1_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
4792 
4793 /* LINE_NUMBER */
4794 
4795 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_MASK (0x00000FFFU)
4796 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
4797 #define CSL_DSS_VP1_LINE_NUMBER_LINENUMBER_MAX (0x00000FFFU)
4798 
4799 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_MASK (0xFFFFF000U)
4800 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_SHIFT (0x0000000CU)
4801 #define CSL_DSS_VP1_LINE_NUMBER_RESERVED_MAX (0x000FFFFFU)
4802 
4803 /* POL_FREQ */
4804 
4805 #define CSL_DSS_VP1_POL_FREQ_ACB_MASK (0x000000FFU)
4806 #define CSL_DSS_VP1_POL_FREQ_ACB_SHIFT (0x00000000U)
4807 #define CSL_DSS_VP1_POL_FREQ_ACB_MAX (0x000000FFU)
4808 
4809 #define CSL_DSS_VP1_POL_FREQ_ACBI_MASK (0x00000F00U)
4810 #define CSL_DSS_VP1_POL_FREQ_ACBI_SHIFT (0x00000008U)
4811 #define CSL_DSS_VP1_POL_FREQ_ACBI_MAX (0x0000000FU)
4812 
4813 #define CSL_DSS_VP1_POL_FREQ_IVS_MASK (0x00001000U)
4814 #define CSL_DSS_VP1_POL_FREQ_IVS_SHIFT (0x0000000CU)
4815 #define CSL_DSS_VP1_POL_FREQ_IVS_MAX (0x00000001U)
4816 
4817 #define CSL_DSS_VP1_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
4818 #define CSL_DSS_VP1_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
4819 
4820 #define CSL_DSS_VP1_POL_FREQ_IHS_MASK (0x00002000U)
4821 #define CSL_DSS_VP1_POL_FREQ_IHS_SHIFT (0x0000000DU)
4822 #define CSL_DSS_VP1_POL_FREQ_IHS_MAX (0x00000001U)
4823 
4824 #define CSL_DSS_VP1_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
4825 #define CSL_DSS_VP1_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
4826 
4827 #define CSL_DSS_VP1_POL_FREQ_IPC_MASK (0x00004000U)
4828 #define CSL_DSS_VP1_POL_FREQ_IPC_SHIFT (0x0000000EU)
4829 #define CSL_DSS_VP1_POL_FREQ_IPC_MAX (0x00000001U)
4830 
4831 #define CSL_DSS_VP1_POL_FREQ_IPC_VAL_DRPCK (0x0U)
4832 #define CSL_DSS_VP1_POL_FREQ_IPC_VAL_DFPCK (0x1U)
4833 
4834 #define CSL_DSS_VP1_POL_FREQ_IEO_MASK (0x00008000U)
4835 #define CSL_DSS_VP1_POL_FREQ_IEO_SHIFT (0x0000000FU)
4836 #define CSL_DSS_VP1_POL_FREQ_IEO_MAX (0x00000001U)
4837 
4838 #define CSL_DSS_VP1_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
4839 #define CSL_DSS_VP1_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
4840 
4841 #define CSL_DSS_VP1_POL_FREQ_RF_MASK (0x00010000U)
4842 #define CSL_DSS_VP1_POL_FREQ_RF_SHIFT (0x00000010U)
4843 #define CSL_DSS_VP1_POL_FREQ_RF_MAX (0x00000001U)
4844 
4845 #define CSL_DSS_VP1_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
4846 #define CSL_DSS_VP1_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
4847 
4848 #define CSL_DSS_VP1_POL_FREQ_ONOFF_MASK (0x00020000U)
4849 #define CSL_DSS_VP1_POL_FREQ_ONOFF_SHIFT (0x00000011U)
4850 #define CSL_DSS_VP1_POL_FREQ_ONOFF_MAX (0x00000001U)
4851 
4852 #define CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
4853 #define CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
4854 
4855 #define CSL_DSS_VP1_POL_FREQ_ALIGN_MASK (0x00040000U)
4856 #define CSL_DSS_VP1_POL_FREQ_ALIGN_SHIFT (0x00000012U)
4857 #define CSL_DSS_VP1_POL_FREQ_ALIGN_MAX (0x00000001U)
4858 
4859 #define CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
4860 #define CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
4861 
4862 #define CSL_DSS_VP1_POL_FREQ_RESERVED_MASK (0xFFF80000U)
4863 #define CSL_DSS_VP1_POL_FREQ_RESERVED_SHIFT (0x00000013U)
4864 #define CSL_DSS_VP1_POL_FREQ_RESERVED_MAX (0x00001FFFU)
4865 
4866 /* SIZE_SCREEN */
4867 
4868 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_MASK (0x00000FFFU)
4869 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
4870 #define CSL_DSS_VP1_SIZE_SCREEN_PPL_MAX (0x00000FFFU)
4871 
4872 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED_MASK (0x00003000U)
4873 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED_SHIFT (0x0000000CU)
4874 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED_MAX (0x00000003U)
4875 
4876 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
4877 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
4878 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
4879 
4880 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
4881 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
4882 #define CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
4883 
4884 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_MASK (0x0FFF0000U)
4885 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
4886 #define CSL_DSS_VP1_SIZE_SCREEN_LPP_MAX (0x00000FFFU)
4887 
4888 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED1_MASK (0xF0000000U)
4889 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED1_SHIFT (0x0000001CU)
4890 #define CSL_DSS_VP1_SIZE_SCREEN_RESERVED1_MAX (0x0000000FU)
4891 
4892 /* TIMING_H */
4893 
4894 #define CSL_DSS_VP1_TIMING_H_HSW_MASK (0x000000FFU)
4895 #define CSL_DSS_VP1_TIMING_H_HSW_SHIFT (0x00000000U)
4896 #define CSL_DSS_VP1_TIMING_H_HSW_MAX (0x000000FFU)
4897 
4898 #define CSL_DSS_VP1_TIMING_H_HFP_MASK (0x000FFF00U)
4899 #define CSL_DSS_VP1_TIMING_H_HFP_SHIFT (0x00000008U)
4900 #define CSL_DSS_VP1_TIMING_H_HFP_MAX (0x00000FFFU)
4901 
4902 #define CSL_DSS_VP1_TIMING_H_HBP_MASK (0xFFF00000U)
4903 #define CSL_DSS_VP1_TIMING_H_HBP_SHIFT (0x00000014U)
4904 #define CSL_DSS_VP1_TIMING_H_HBP_MAX (0x00000FFFU)
4905 
4906 /* TIMING_V */
4907 
4908 #define CSL_DSS_VP1_TIMING_V_VSW_MASK (0x000000FFU)
4909 #define CSL_DSS_VP1_TIMING_V_VSW_SHIFT (0x00000000U)
4910 #define CSL_DSS_VP1_TIMING_V_VSW_MAX (0x000000FFU)
4911 
4912 #define CSL_DSS_VP1_TIMING_V_VFP_MASK (0x000FFF00U)
4913 #define CSL_DSS_VP1_TIMING_V_VFP_SHIFT (0x00000008U)
4914 #define CSL_DSS_VP1_TIMING_V_VFP_MAX (0x00000FFFU)
4915 
4916 #define CSL_DSS_VP1_TIMING_V_VBP_MASK (0xFFF00000U)
4917 #define CSL_DSS_VP1_TIMING_V_VBP_SHIFT (0x00000014U)
4918 #define CSL_DSS_VP1_TIMING_V_VBP_MAX (0x00000FFFU)
4919 
4920 /* CSC_COEF3 */
4921 
4922 #define CSL_DSS_VP1_CSC_COEF3_C20_MASK (0x000007FFU)
4923 #define CSL_DSS_VP1_CSC_COEF3_C20_SHIFT (0x00000000U)
4924 #define CSL_DSS_VP1_CSC_COEF3_C20_MAX (0x000007FFU)
4925 
4926 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
4927 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
4928 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
4929 
4930 #define CSL_DSS_VP1_CSC_COEF3_C21_MASK (0x07FF0000U)
4931 #define CSL_DSS_VP1_CSC_COEF3_C21_SHIFT (0x00000010U)
4932 #define CSL_DSS_VP1_CSC_COEF3_C21_MAX (0x000007FFU)
4933 
4934 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
4935 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
4936 #define CSL_DSS_VP1_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
4937 
4938 /* CSC_COEF4 */
4939 
4940 #define CSL_DSS_VP1_CSC_COEF4_C22_MASK (0x000007FFU)
4941 #define CSL_DSS_VP1_CSC_COEF4_C22_SHIFT (0x00000000U)
4942 #define CSL_DSS_VP1_CSC_COEF4_C22_MAX (0x000007FFU)
4943 
4944 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
4945 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
4946 #define CSL_DSS_VP1_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
4947 
4948 /* CSC_COEF5 */
4949 
4950 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_MASK (0x00000007U)
4951 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
4952 #define CSL_DSS_VP1_CSC_COEF5_RESERVED_MAX (0x00000007U)
4953 
4954 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
4955 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
4956 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
4957 
4958 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_MASK (0x00070000U)
4959 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
4960 #define CSL_DSS_VP1_CSC_COEF5_RESERVED1_MAX (0x00000007U)
4961 
4962 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
4963 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
4964 #define CSL_DSS_VP1_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
4965 
4966 /* CSC_COEF6 */
4967 
4968 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_MASK (0x00000007U)
4969 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
4970 #define CSL_DSS_VP1_CSC_COEF6_RESERVED_MAX (0x00000007U)
4971 
4972 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
4973 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
4974 #define CSL_DSS_VP1_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
4975 
4976 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_MASK (0x00070000U)
4977 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
4978 #define CSL_DSS_VP1_CSC_COEF6_RESERVED1_MAX (0x00000007U)
4979 
4980 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
4981 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
4982 #define CSL_DSS_VP1_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
4983 
4984 /* CSC_COEF7 */
4985 
4986 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_MASK (0x00000007U)
4987 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
4988 #define CSL_DSS_VP1_CSC_COEF7_RESERVED_MAX (0x00000007U)
4989 
4990 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
4991 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
4992 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
4993 
4994 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_MASK (0x00070000U)
4995 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
4996 #define CSL_DSS_VP1_CSC_COEF7_RESERVED1_MAX (0x00000007U)
4997 
4998 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
4999 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
5000 #define CSL_DSS_VP1_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
5001 
5002 /* SAFETY_ATTRIBUTES */
5003 
5004 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
5005 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
5006 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
5007 
5008 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
5009 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
5010 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
5011 
5012 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
5013 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
5014 
5015 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
5016 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
5017 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
5018 
5019 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
5020 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
5021 
5022 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
5023 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
5024 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
5025 
5026 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
5027 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
5028 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
5029 
5030 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
5031 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
5032 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
5033 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
5034 
5035 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
5036 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
5037 #define CSL_DSS_VP1_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
5038 
5039 /* SAFETY_CAPT_SIGNATURE */
5040 
5041 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
5042 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
5043 #define CSL_DSS_VP1_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
5044 
5045 /* SAFETY_POSITION */
5046 
5047 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_MASK (0x00000FFFU)
5048 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
5049 #define CSL_DSS_VP1_SAFETY_POSITION_POSX_MAX (0x00000FFFU)
5050 
5051 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED1_MASK (0x0000F000U)
5052 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED1_SHIFT (0x0000000CU)
5053 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED1_MAX (0x0000000FU)
5054 
5055 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_MASK (0x0FFF0000U)
5056 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
5057 #define CSL_DSS_VP1_SAFETY_POSITION_POSY_MAX (0x00000FFFU)
5058 
5059 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED_MASK (0xF0000000U)
5060 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED_SHIFT (0x0000001CU)
5061 #define CSL_DSS_VP1_SAFETY_POSITION_RESERVED_MAX (0x0000000FU)
5062 
5063 /* SAFETY_REF_SIGNATURE */
5064 
5065 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
5066 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
5067 #define CSL_DSS_VP1_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
5068 
5069 /* SAFETY_SIZE */
5070 
5071 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_MASK (0x00000FFFU)
5072 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
5073 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEX_MAX (0x00000FFFU)
5074 
5075 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED1_MASK (0x0000F000U)
5076 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED1_SHIFT (0x0000000CU)
5077 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED1_MAX (0x0000000FU)
5078 
5079 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_MASK (0x0FFF0000U)
5080 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
5081 #define CSL_DSS_VP1_SAFETY_SIZE_SIZEY_MAX (0x00000FFFU)
5082 
5083 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED_MASK (0xF0000000U)
5084 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED_SHIFT (0x0000001CU)
5085 #define CSL_DSS_VP1_SAFETY_SIZE_RESERVED_MAX (0x0000000FU)
5086 
5087 /* SAFETY_LFSR_SEED */
5088 
5089 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
5090 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
5091 #define CSL_DSS_VP1_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
5092 
5093 /* GAMMA_TABLE_0 */
5094 
5095 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_MASK (0x000000FFU)
5096 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
5097 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_B_MAX (0x000000FFU)
5098 
5099 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_MASK (0x0000FF00U)
5100 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_SHIFT (0x00000008U)
5101 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_G_MAX (0x000000FFU)
5102 
5103 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_MASK (0x00FF0000U)
5104 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000010U)
5105 #define CSL_DSS_VP1_GAMMA_TABLE_0_VALUE_R_MAX (0x000000FFU)
5106 
5107 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_MASK (0xFF000000U)
5108 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_SHIFT (0x00000018U)
5109 #define CSL_DSS_VP1_GAMMA_TABLE_0_INDEX_MAX (0x000000FFU)
5110 
5111 /* GAMMA_TABLE_1 */
5112 
5113 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_MASK (0x000000FFU)
5114 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
5115 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_B_MAX (0x000000FFU)
5116 
5117 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_MASK (0x0000FF00U)
5118 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_SHIFT (0x00000008U)
5119 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_G_MAX (0x000000FFU)
5120 
5121 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_MASK (0x00FF0000U)
5122 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000010U)
5123 #define CSL_DSS_VP1_GAMMA_TABLE_1_VALUE_R_MAX (0x000000FFU)
5124 
5125 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_MASK (0xFF000000U)
5126 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_SHIFT (0x00000018U)
5127 #define CSL_DSS_VP1_GAMMA_TABLE_1_INDEX_MAX (0x000000FFU)
5128 
5129 /* GAMMA_TABLE_2 */
5130 
5131 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_MASK (0x000000FFU)
5132 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
5133 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_B_MAX (0x000000FFU)
5134 
5135 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_MASK (0x0000FF00U)
5136 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_SHIFT (0x00000008U)
5137 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_G_MAX (0x000000FFU)
5138 
5139 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_MASK (0x00FF0000U)
5140 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000010U)
5141 #define CSL_DSS_VP1_GAMMA_TABLE_2_VALUE_R_MAX (0x000000FFU)
5142 
5143 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_MASK (0xFF000000U)
5144 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_SHIFT (0x00000018U)
5145 #define CSL_DSS_VP1_GAMMA_TABLE_2_INDEX_MAX (0x000000FFU)
5146 
5147 /* GAMMA_TABLE_3 */
5148 
5149 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_MASK (0x000000FFU)
5150 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
5151 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_B_MAX (0x000000FFU)
5152 
5153 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_MASK (0x0000FF00U)
5154 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_SHIFT (0x00000008U)
5155 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_G_MAX (0x000000FFU)
5156 
5157 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_MASK (0x00FF0000U)
5158 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000010U)
5159 #define CSL_DSS_VP1_GAMMA_TABLE_3_VALUE_R_MAX (0x000000FFU)
5160 
5161 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_MASK (0xFF000000U)
5162 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_SHIFT (0x00000018U)
5163 #define CSL_DSS_VP1_GAMMA_TABLE_3_INDEX_MAX (0x000000FFU)
5164 
5165 /* GAMMA_TABLE_4 */
5166 
5167 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_MASK (0x000000FFU)
5168 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
5169 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_B_MAX (0x000000FFU)
5170 
5171 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_MASK (0x0000FF00U)
5172 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_SHIFT (0x00000008U)
5173 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_G_MAX (0x000000FFU)
5174 
5175 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_MASK (0x00FF0000U)
5176 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000010U)
5177 #define CSL_DSS_VP1_GAMMA_TABLE_4_VALUE_R_MAX (0x000000FFU)
5178 
5179 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_MASK (0xFF000000U)
5180 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_SHIFT (0x00000018U)
5181 #define CSL_DSS_VP1_GAMMA_TABLE_4_INDEX_MAX (0x000000FFU)
5182 
5183 /* GAMMA_TABLE_5 */
5184 
5185 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_MASK (0x000000FFU)
5186 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
5187 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_B_MAX (0x000000FFU)
5188 
5189 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_MASK (0x0000FF00U)
5190 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_SHIFT (0x00000008U)
5191 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_G_MAX (0x000000FFU)
5192 
5193 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_MASK (0x00FF0000U)
5194 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000010U)
5195 #define CSL_DSS_VP1_GAMMA_TABLE_5_VALUE_R_MAX (0x000000FFU)
5196 
5197 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_MASK (0xFF000000U)
5198 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_SHIFT (0x00000018U)
5199 #define CSL_DSS_VP1_GAMMA_TABLE_5_INDEX_MAX (0x000000FFU)
5200 
5201 /* GAMMA_TABLE_6 */
5202 
5203 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_MASK (0x000000FFU)
5204 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
5205 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_B_MAX (0x000000FFU)
5206 
5207 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_MASK (0x0000FF00U)
5208 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_SHIFT (0x00000008U)
5209 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_G_MAX (0x000000FFU)
5210 
5211 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_MASK (0x00FF0000U)
5212 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000010U)
5213 #define CSL_DSS_VP1_GAMMA_TABLE_6_VALUE_R_MAX (0x000000FFU)
5214 
5215 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_MASK (0xFF000000U)
5216 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_SHIFT (0x00000018U)
5217 #define CSL_DSS_VP1_GAMMA_TABLE_6_INDEX_MAX (0x000000FFU)
5218 
5219 /* GAMMA_TABLE_7 */
5220 
5221 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_MASK (0x000000FFU)
5222 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
5223 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_B_MAX (0x000000FFU)
5224 
5225 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_MASK (0x0000FF00U)
5226 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_SHIFT (0x00000008U)
5227 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_G_MAX (0x000000FFU)
5228 
5229 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_MASK (0x00FF0000U)
5230 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000010U)
5231 #define CSL_DSS_VP1_GAMMA_TABLE_7_VALUE_R_MAX (0x000000FFU)
5232 
5233 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_MASK (0xFF000000U)
5234 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_SHIFT (0x00000018U)
5235 #define CSL_DSS_VP1_GAMMA_TABLE_7_INDEX_MAX (0x000000FFU)
5236 
5237 /* GAMMA_TABLE_8 */
5238 
5239 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_MASK (0x000000FFU)
5240 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
5241 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_B_MAX (0x000000FFU)
5242 
5243 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_MASK (0x0000FF00U)
5244 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_SHIFT (0x00000008U)
5245 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_G_MAX (0x000000FFU)
5246 
5247 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_MASK (0x00FF0000U)
5248 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000010U)
5249 #define CSL_DSS_VP1_GAMMA_TABLE_8_VALUE_R_MAX (0x000000FFU)
5250 
5251 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_MASK (0xFF000000U)
5252 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_SHIFT (0x00000018U)
5253 #define CSL_DSS_VP1_GAMMA_TABLE_8_INDEX_MAX (0x000000FFU)
5254 
5255 /* GAMMA_TABLE_9 */
5256 
5257 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_MASK (0x000000FFU)
5258 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
5259 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_B_MAX (0x000000FFU)
5260 
5261 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_MASK (0x0000FF00U)
5262 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_SHIFT (0x00000008U)
5263 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_G_MAX (0x000000FFU)
5264 
5265 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_MASK (0x00FF0000U)
5266 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000010U)
5267 #define CSL_DSS_VP1_GAMMA_TABLE_9_VALUE_R_MAX (0x000000FFU)
5268 
5269 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_MASK (0xFF000000U)
5270 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_SHIFT (0x00000018U)
5271 #define CSL_DSS_VP1_GAMMA_TABLE_9_INDEX_MAX (0x000000FFU)
5272 
5273 /* GAMMA_TABLE_10 */
5274 
5275 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_MASK (0x000000FFU)
5276 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
5277 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_B_MAX (0x000000FFU)
5278 
5279 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_MASK (0x0000FF00U)
5280 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_SHIFT (0x00000008U)
5281 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_G_MAX (0x000000FFU)
5282 
5283 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_MASK (0x00FF0000U)
5284 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000010U)
5285 #define CSL_DSS_VP1_GAMMA_TABLE_10_VALUE_R_MAX (0x000000FFU)
5286 
5287 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_MASK (0xFF000000U)
5288 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_SHIFT (0x00000018U)
5289 #define CSL_DSS_VP1_GAMMA_TABLE_10_INDEX_MAX (0x000000FFU)
5290 
5291 /* GAMMA_TABLE_11 */
5292 
5293 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_MASK (0x000000FFU)
5294 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
5295 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_B_MAX (0x000000FFU)
5296 
5297 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_MASK (0x0000FF00U)
5298 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_SHIFT (0x00000008U)
5299 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_G_MAX (0x000000FFU)
5300 
5301 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_MASK (0x00FF0000U)
5302 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000010U)
5303 #define CSL_DSS_VP1_GAMMA_TABLE_11_VALUE_R_MAX (0x000000FFU)
5304 
5305 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_MASK (0xFF000000U)
5306 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_SHIFT (0x00000018U)
5307 #define CSL_DSS_VP1_GAMMA_TABLE_11_INDEX_MAX (0x000000FFU)
5308 
5309 /* GAMMA_TABLE_12 */
5310 
5311 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_MASK (0x000000FFU)
5312 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
5313 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_B_MAX (0x000000FFU)
5314 
5315 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_MASK (0x0000FF00U)
5316 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_SHIFT (0x00000008U)
5317 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_G_MAX (0x000000FFU)
5318 
5319 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_MASK (0x00FF0000U)
5320 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000010U)
5321 #define CSL_DSS_VP1_GAMMA_TABLE_12_VALUE_R_MAX (0x000000FFU)
5322 
5323 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_MASK (0xFF000000U)
5324 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_SHIFT (0x00000018U)
5325 #define CSL_DSS_VP1_GAMMA_TABLE_12_INDEX_MAX (0x000000FFU)
5326 
5327 /* GAMMA_TABLE_13 */
5328 
5329 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_MASK (0x000000FFU)
5330 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
5331 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_B_MAX (0x000000FFU)
5332 
5333 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_MASK (0x0000FF00U)
5334 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_SHIFT (0x00000008U)
5335 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_G_MAX (0x000000FFU)
5336 
5337 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_MASK (0x00FF0000U)
5338 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000010U)
5339 #define CSL_DSS_VP1_GAMMA_TABLE_13_VALUE_R_MAX (0x000000FFU)
5340 
5341 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_MASK (0xFF000000U)
5342 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_SHIFT (0x00000018U)
5343 #define CSL_DSS_VP1_GAMMA_TABLE_13_INDEX_MAX (0x000000FFU)
5344 
5345 /* GAMMA_TABLE_14 */
5346 
5347 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_MASK (0x000000FFU)
5348 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
5349 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_B_MAX (0x000000FFU)
5350 
5351 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_MASK (0x0000FF00U)
5352 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_SHIFT (0x00000008U)
5353 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_G_MAX (0x000000FFU)
5354 
5355 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_MASK (0x00FF0000U)
5356 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000010U)
5357 #define CSL_DSS_VP1_GAMMA_TABLE_14_VALUE_R_MAX (0x000000FFU)
5358 
5359 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_MASK (0xFF000000U)
5360 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_SHIFT (0x00000018U)
5361 #define CSL_DSS_VP1_GAMMA_TABLE_14_INDEX_MAX (0x000000FFU)
5362 
5363 /* GAMMA_TABLE_15 */
5364 
5365 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_MASK (0x000000FFU)
5366 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
5367 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_B_MAX (0x000000FFU)
5368 
5369 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_MASK (0x0000FF00U)
5370 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_SHIFT (0x00000008U)
5371 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_G_MAX (0x000000FFU)
5372 
5373 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_MASK (0x00FF0000U)
5374 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000010U)
5375 #define CSL_DSS_VP1_GAMMA_TABLE_15_VALUE_R_MAX (0x000000FFU)
5376 
5377 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_MASK (0xFF000000U)
5378 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_SHIFT (0x00000018U)
5379 #define CSL_DSS_VP1_GAMMA_TABLE_15_INDEX_MAX (0x000000FFU)
5380 
5381 /* DSS_OLDI_CFG */
5382 
5383 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_MASK (0x00000001U)
5384 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_SHIFT (0x00000000U)
5385 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_MAX (0x00000001U)
5386 
5387 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_VAL_DISABLED (0x0U)
5388 #define CSL_DSS_VP1_DSS_OLDI_CFG_ENABLE_VAL_ENABLED (0x1U)
5389 
5390 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_MASK (0x0000000EU)
5391 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_SHIFT (0x00000001U)
5392 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_MAX (0x00000007U)
5393 
5394 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_A (0x0U)
5395 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_B (0x1U)
5396 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_C (0x2U)
5397 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_D (0x4U)
5398 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_E (0x5U)
5399 #define CSL_DSS_VP1_DSS_OLDI_CFG_MAP_VAL_TYPE_F (0x6U)
5400 
5401 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_MASK (0x00000010U)
5402 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_SHIFT (0x00000004U)
5403 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_MAX (0x00000001U)
5404 
5405 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_VAL_CHANNEL0 (0x0U)
5406 #define CSL_DSS_VP1_DSS_OLDI_CFG_SRC_VAL_CHANNEL1 (0x1U)
5407 
5408 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_MASK (0x00000020U)
5409 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_SHIFT (0x00000005U)
5410 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_MAX (0x00000001U)
5411 
5412 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_VAL_SINGLE (0x0U)
5413 #define CSL_DSS_VP1_DSS_OLDI_CFG_MODE_VAL_DUPLICATE (0x1U)
5414 
5415 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_MASK (0x00000040U)
5416 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_SHIFT (0x00000006U)
5417 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_MAX (0x00000001U)
5418 
5419 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_VAL_MASTER (0x0U)
5420 #define CSL_DSS_VP1_DSS_OLDI_CFG_MASTERSLAVE_VAL_SLAVE (0x1U)
5421 
5422 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_MASK (0x00000080U)
5423 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_SHIFT (0x00000007U)
5424 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_MAX (0x00000001U)
5425 
5426 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_VAL_HIGH (0x0U)
5427 #define CSL_DSS_VP1_DSS_OLDI_CFG_DEPOL_VAL_LOW (0x1U)
5428 
5429 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_MASK (0x00000100U)
5430 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_SHIFT (0x00000008U)
5431 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_MAX (0x00000001U)
5432 
5433 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_18B (0x0U)
5434 #define CSL_DSS_VP1_DSS_OLDI_CFG_MSB_VAL_24B (0x1U)
5435 
5436 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_MASK (0x00000200U)
5437 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_SHIFT (0x00000009U)
5438 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_MAX (0x00000001U)
5439 
5440 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_VAL_DISABLE (0x0U)
5441 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBEN_VAL_ENABLE (0x1U)
5442 
5443 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBDATA_MASK (0x00000400U)
5444 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBDATA_SHIFT (0x0000000AU)
5445 #define CSL_DSS_VP1_DSS_OLDI_CFG_LBDATA_MAX (0x00000001U)
5446 
5447 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_MASK (0x00000800U)
5448 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_SHIFT (0x0000000BU)
5449 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_MAX (0x00000001U)
5450 
5451 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE (0x0U)
5452 #define CSL_DSS_VP1_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE (0x1U)
5453 
5454 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_MASK (0x00001000U)
5455 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_SHIFT (0x0000000CU)
5456 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_MAX (0x00000001U)
5457 
5458 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_VAL_ASSERT (0x0U)
5459 #define CSL_DSS_VP1_DSS_OLDI_CFG_SOFTRST_VAL_DEASSERT (0x1U)
5460 
5461 #define CSL_DSS_VP1_DSS_OLDI_CFG_TPATCFG_MASK (0x00002000U)
5462 #define CSL_DSS_VP1_DSS_OLDI_CFG_TPATCFG_SHIFT (0x0000000DU)
5463 #define CSL_DSS_VP1_DSS_OLDI_CFG_TPATCFG_MAX (0x00000001U)
5464 
5465 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
5466 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
5467 #define CSL_DSS_VP1_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
5468 
5469 /* DSS_OLDI_STATUS */
5470 
5471 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMIN_MASK (0x0000003FU)
5472 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMIN_SHIFT (0x00000000U)
5473 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMIN_MAX (0x0000003FU)
5474 
5475 #define CSL_DSS_VP1_DSS_OLDI_STATUS_CUSTOM_MASK (0x000000C0U)
5476 #define CSL_DSS_VP1_DSS_OLDI_STATUS_CUSTOM_SHIFT (0x00000006U)
5477 #define CSL_DSS_VP1_DSS_OLDI_STATUS_CUSTOM_MAX (0x00000003U)
5478 
5479 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMAJOR_MASK (0x00000700U)
5480 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMAJOR_SHIFT (0x00000008U)
5481 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVMAJOR_MAX (0x00000007U)
5482 
5483 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVRTL_MASK (0x0000F800U)
5484 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVRTL_SHIFT (0x0000000BU)
5485 #define CSL_DSS_VP1_DSS_OLDI_STATUS_REVRTL_MAX (0x0000001FU)
5486 
5487 #define CSL_DSS_VP1_DSS_OLDI_STATUS_MODID_MASK (0xFFFF0000U)
5488 #define CSL_DSS_VP1_DSS_OLDI_STATUS_MODID_SHIFT (0x00000010U)
5489 #define CSL_DSS_VP1_DSS_OLDI_STATUS_MODID_MAX (0x0000FFFFU)
5490 
5491 /* DSS_OLDI_LB */
5492 
5493 #define CSL_DSS_VP1_DSS_OLDI_LB_LBRDATA_MASK (0x000003FFU)
5494 #define CSL_DSS_VP1_DSS_OLDI_LB_LBRDATA_SHIFT (0x00000000U)
5495 #define CSL_DSS_VP1_DSS_OLDI_LB_LBRDATA_MAX (0x000003FFU)
5496 
5497 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFC00U)
5498 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_SHIFT (0x0000000AU)
5499 #define CSL_DSS_VP1_DSS_OLDI_LB_RESERVED_MAX (0x003FFFFFU)
5500 
5501 /**************************************************************************
5502 * Hardware Region : VP2 Registers
5503 **************************************************************************/
5504 
5505 
5506 /**************************************************************************
5507 * Register Overlay Structure
5508 **************************************************************************/
5509 
5510 typedef struct {
5511  volatile uint32_t CONFIG; /* CONFIG */
5512  volatile uint32_t CONTROL; /* CONTROL */
5513  volatile uint32_t CSC_COEF0; /* CSC_COEF0 */
5514  volatile uint32_t CSC_COEF1; /* CSC_COEF1 */
5515  volatile uint32_t CSC_COEF2; /* CSC_COEF2 */
5516  volatile uint32_t DATA_CYCLE_0; /* DATA_CYCLE_0 */
5517  volatile uint32_t DATA_CYCLE_1; /* DATA_CYCLE_1 */
5518  volatile uint32_t DATA_CYCLE_2; /* DATA_CYCLE_2 */
5519  volatile uint8_t Resv_68[36];
5520  volatile uint32_t LINE_NUMBER; /* LINE_NUMBER */
5521  volatile uint8_t Resv_76[4];
5522  volatile uint32_t POL_FREQ; /* POL_FREQ */
5523  volatile uint32_t SIZE_SCREEN; /* SIZE_SCREEN */
5524  volatile uint32_t TIMING_H; /* TIMING_H */
5525  volatile uint32_t TIMING_V; /* TIMING_V */
5526  volatile uint32_t CSC_COEF3; /* CSC_COEF3 */
5527  volatile uint32_t CSC_COEF4; /* CSC_COEF4 */
5528  volatile uint32_t CSC_COEF5; /* CSC_COEF5 */
5529  volatile uint32_t CSC_COEF6; /* CSC_COEF6 */
5530  volatile uint32_t CSC_COEF7; /* CSC_COEF7 */
5531  volatile uint32_t SAFETY_ATTRIBUTES[4U]; /* SAFETY_ATTRIBUTES 0..3 */
5532  volatile uint8_t Resv_144[16];
5533  volatile uint32_t SAFETY_CAPT_SIGNATURE[4U]; /* SAFETY_CAPT_SIGNATURE 0..3 */
5534  volatile uint8_t Resv_176[16];
5535  volatile uint32_t SAFETY_POSITION[4U]; /* SAFETY_POSITION 0..3 */
5536  volatile uint8_t Resv_208[16];
5537  volatile uint32_t SAFETY_REF_SIGNATURE[4U]; /* SAFETY_REF_SIGNATURE 0..3 */
5538  volatile uint8_t Resv_240[16];
5539  volatile uint32_t SAFETY_SIZE[4U]; /* SAFETY_SIZE 0..3 */
5540  volatile uint8_t Resv_272[16];
5541  volatile uint32_t SAFETY_LFSR_SEED; /* SAFETY_LFSR_SEED */
5542  volatile uint8_t Resv_288[12];
5543  volatile uint32_t GAMMA_TABLE_0; /* GAMMA_TABLE_0 */
5544  volatile uint32_t GAMMA_TABLE_1; /* GAMMA_TABLE_1 */
5545  volatile uint32_t GAMMA_TABLE_2; /* GAMMA_TABLE_2 */
5546  volatile uint32_t GAMMA_TABLE_3; /* GAMMA_TABLE_3 */
5547  volatile uint32_t GAMMA_TABLE_4; /* GAMMA_TABLE_4 */
5548  volatile uint32_t GAMMA_TABLE_5; /* GAMMA_TABLE_5 */
5549  volatile uint32_t GAMMA_TABLE_6; /* GAMMA_TABLE_6 */
5550  volatile uint32_t GAMMA_TABLE_7; /* GAMMA_TABLE_7 */
5551  volatile uint32_t GAMMA_TABLE_8; /* GAMMA_TABLE_8 */
5552  volatile uint32_t GAMMA_TABLE_9; /* GAMMA_TABLE_9 */
5553  volatile uint32_t GAMMA_TABLE_10; /* GAMMA_TABLE_10 */
5554  volatile uint32_t GAMMA_TABLE_11; /* GAMMA_TABLE_11 */
5555  volatile uint32_t GAMMA_TABLE_12; /* GAMMA_TABLE_12 */
5556  volatile uint32_t GAMMA_TABLE_13; /* GAMMA_TABLE_13 */
5557  volatile uint32_t GAMMA_TABLE_14; /* GAMMA_TABLE_14 */
5558  volatile uint32_t GAMMA_TABLE_15; /* GAMMA_TABLE_15 */
5559  volatile uint32_t DSS_OLDI_CFG; /* DSS_OLDI_CFG */
5560  volatile uint32_t DSS_OLDI_STATUS; /* DSS_OLDI_STATUS */
5561  volatile uint32_t DSS_OLDI_LB; /* DSS_OLDI_LB */
5562 } CSL_dss_vp2Regs;
5563 
5564 
5565 /**************************************************************************
5566 * Register Macros
5567 **************************************************************************/
5568 
5569 #define CSL_DSS_VP2_CONFIG (0x00000000U)
5570 #define CSL_DSS_VP2_CONTROL (0x00000004U)
5571 #define CSL_DSS_VP2_CSC_COEF0 (0x00000008U)
5572 #define CSL_DSS_VP2_CSC_COEF1 (0x0000000CU)
5573 #define CSL_DSS_VP2_CSC_COEF2 (0x00000010U)
5574 #define CSL_DSS_VP2_DATA_CYCLE_0 (0x00000014U)
5575 #define CSL_DSS_VP2_DATA_CYCLE_1 (0x00000018U)
5576 #define CSL_DSS_VP2_DATA_CYCLE_2 (0x0000001CU)
5577 #define CSL_DSS_VP2_LINE_NUMBER (0x00000044U)
5578 #define CSL_DSS_VP2_POL_FREQ (0x0000004CU)
5579 #define CSL_DSS_VP2_SIZE_SCREEN (0x00000050U)
5580 #define CSL_DSS_VP2_TIMING_H (0x00000054U)
5581 #define CSL_DSS_VP2_TIMING_V (0x00000058U)
5582 #define CSL_DSS_VP2_CSC_COEF3 (0x0000005CU)
5583 #define CSL_DSS_VP2_CSC_COEF4 (0x00000060U)
5584 #define CSL_DSS_VP2_CSC_COEF5 (0x00000064U)
5585 #define CSL_DSS_VP2_CSC_COEF6 (0x00000068U)
5586 #define CSL_DSS_VP2_CSC_COEF7 (0x0000006CU)
5587 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES(index) (0x00000070U+((uint32_t)(index)*0x4U))
5588 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE(index) (0x00000090U+((uint32_t)(index)*0x4U))
5589 #define CSL_DSS_VP2_SAFETY_POSITION(index) (0x000000B0U+((uint32_t)(index)*0x4U))
5590 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE(index) (0x000000D0U+((uint32_t)(index)*0x4U))
5591 #define CSL_DSS_VP2_SAFETY_SIZE(index) (0x000000F0U+((uint32_t)(index)*0x4U))
5592 #define CSL_DSS_VP2_SAFETY_LFSR_SEED (0x00000110U)
5593 #define CSL_DSS_VP2_GAMMA_TABLE_0 (0x00000120U)
5594 #define CSL_DSS_VP2_GAMMA_TABLE_1 (0x00000124U)
5595 #define CSL_DSS_VP2_GAMMA_TABLE_2 (0x00000128U)
5596 #define CSL_DSS_VP2_GAMMA_TABLE_3 (0x0000012CU)
5597 #define CSL_DSS_VP2_GAMMA_TABLE_4 (0x00000130U)
5598 #define CSL_DSS_VP2_GAMMA_TABLE_5 (0x00000134U)
5599 #define CSL_DSS_VP2_GAMMA_TABLE_6 (0x00000138U)
5600 #define CSL_DSS_VP2_GAMMA_TABLE_7 (0x0000013CU)
5601 #define CSL_DSS_VP2_GAMMA_TABLE_8 (0x00000140U)
5602 #define CSL_DSS_VP2_GAMMA_TABLE_9 (0x00000144U)
5603 #define CSL_DSS_VP2_GAMMA_TABLE_10 (0x00000148U)
5604 #define CSL_DSS_VP2_GAMMA_TABLE_11 (0x0000014CU)
5605 #define CSL_DSS_VP2_GAMMA_TABLE_12 (0x00000150U)
5606 #define CSL_DSS_VP2_GAMMA_TABLE_13 (0x00000154U)
5607 #define CSL_DSS_VP2_GAMMA_TABLE_14 (0x00000158U)
5608 #define CSL_DSS_VP2_GAMMA_TABLE_15 (0x0000015CU)
5609 #define CSL_DSS_VP2_DSS_OLDI_CFG (0x00000160U)
5610 #define CSL_DSS_VP2_DSS_OLDI_STATUS (0x00000164U)
5611 #define CSL_DSS_VP2_DSS_OLDI_LB (0x00000168U)
5612 
5613 /**************************************************************************
5614 * Field Definition Macros
5615 **************************************************************************/
5616 
5617 
5618 /* CONFIG */
5619 
5620 #define CSL_DSS_VP2_CONFIG_PIXELGATED_MASK (0x00000001U)
5621 #define CSL_DSS_VP2_CONFIG_PIXELGATED_SHIFT (0x00000000U)
5622 #define CSL_DSS_VP2_CONFIG_PIXELGATED_MAX (0x00000001U)
5623 
5624 #define CSL_DSS_VP2_CONFIG_PIXELGATED_VAL_PCLKTOGA (0x0U)
5625 #define CSL_DSS_VP2_CONFIG_PIXELGATED_VAL_PCLKTOGV (0x1U)
5626 
5627 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_MASK (0x00000002U)
5628 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_SHIFT (0x00000001U)
5629 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_MAX (0x00000001U)
5630 
5631 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_VAL_DEGDIS (0x0U)
5632 #define CSL_DSS_VP2_CONFIG_DATAENABLEGATED_VAL_DEGENB (0x1U)
5633 
5634 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_MASK (0x00000004U)
5635 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_SHIFT (0x00000002U)
5636 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_MAX (0x00000001U)
5637 
5638 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_VAL_GAMMADIS (0x0U)
5639 #define CSL_DSS_VP2_CONFIG_GAMMAENABLE_VAL_GAMMAENB (0x1U)
5640 
5641 #define CSL_DSS_VP2_CONFIG_HDMIMODE_MASK (0x00000008U)
5642 #define CSL_DSS_VP2_CONFIG_HDMIMODE_SHIFT (0x00000003U)
5643 #define CSL_DSS_VP2_CONFIG_HDMIMODE_MAX (0x00000001U)
5644 
5645 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_MASK (0x00000010U)
5646 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_SHIFT (0x00000004U)
5647 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_MAX (0x00000001U)
5648 
5649 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_VAL_PDGDIS (0x0U)
5650 #define CSL_DSS_VP2_CONFIG_PIXELDATAGATED_VAL_PDGENB (0x1U)
5651 
5652 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_MASK (0x00000020U)
5653 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_SHIFT (0x00000005U)
5654 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_MAX (0x00000001U)
5655 
5656 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_VAL_PCGDIS (0x0U)
5657 #define CSL_DSS_VP2_CONFIG_PIXELCLOCKGATED_VAL_PCGENB (0x1U)
5658 
5659 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_MASK (0x00000040U)
5660 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_SHIFT (0x00000006U)
5661 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_MAX (0x00000001U)
5662 
5663 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_VAL_HGDIS (0x0U)
5664 #define CSL_DSS_VP2_CONFIG_HSYNCGATED_VAL_HGENB (0x1U)
5665 
5666 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_MASK (0x00000080U)
5667 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_SHIFT (0x00000007U)
5668 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_MAX (0x00000001U)
5669 
5670 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_VAL_VGDIS (0x0U)
5671 #define CSL_DSS_VP2_CONFIG_VSYNCGATED_VAL_VGENB (0x1U)
5672 
5673 #define CSL_DSS_VP2_CONFIG_EXTERNALSYNCEN_MASK (0x00000100U)
5674 #define CSL_DSS_VP2_CONFIG_EXTERNALSYNCEN_SHIFT (0x00000008U)
5675 #define CSL_DSS_VP2_CONFIG_EXTERNALSYNCEN_MAX (0x00000001U)
5676 
5677 #define CSL_DSS_VP2_CONFIG_RESERVED1_MASK (0x00007E00U)
5678 #define CSL_DSS_VP2_CONFIG_RESERVED1_SHIFT (0x00000009U)
5679 #define CSL_DSS_VP2_CONFIG_RESERVED1_MAX (0x0000003FU)
5680 
5681 #define CSL_DSS_VP2_CONFIG_CPR_MASK (0x00008000U)
5682 #define CSL_DSS_VP2_CONFIG_CPR_SHIFT (0x0000000FU)
5683 #define CSL_DSS_VP2_CONFIG_CPR_MAX (0x00000001U)
5684 
5685 #define CSL_DSS_VP2_CONFIG_BUFFERHANDSHAKE_MASK (0x00010000U)
5686 #define CSL_DSS_VP2_CONFIG_BUFFERHANDSHAKE_SHIFT (0x00000010U)
5687 #define CSL_DSS_VP2_CONFIG_BUFFERHANDSHAKE_MAX (0x00000001U)
5688 
5689 #define CSL_DSS_VP2_CONFIG_RESERVED2_MASK (0x000E0000U)
5690 #define CSL_DSS_VP2_CONFIG_RESERVED2_SHIFT (0x00000011U)
5691 #define CSL_DSS_VP2_CONFIG_RESERVED2_MAX (0x00000007U)
5692 
5693 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_MASK (0x00100000U)
5694 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_SHIFT (0x00000014U)
5695 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_MAX (0x00000001U)
5696 
5697 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_VAL_DISABLE (0x0U)
5698 #define CSL_DSS_VP2_CONFIG_BT656ENABLE_VAL_ENABLE (0x1U)
5699 
5700 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_MASK (0x00200000U)
5701 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_SHIFT (0x00000015U)
5702 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_MAX (0x00000001U)
5703 
5704 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_VAL_DISABLE (0x0U)
5705 #define CSL_DSS_VP2_CONFIG_BT1120ENABLE_VAL_ENABLE (0x1U)
5706 
5707 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_MASK (0x00400000U)
5708 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_SHIFT (0x00000016U)
5709 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_MAX (0x00000001U)
5710 
5711 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_VAL_DISABLE (0x0U)
5712 #define CSL_DSS_VP2_CONFIG_OUTPUTMODEENABLE_VAL_ENABLE (0x1U)
5713 
5714 #define CSL_DSS_VP2_CONFIG_FIDFIRST_MASK (0x00800000U)
5715 #define CSL_DSS_VP2_CONFIG_FIDFIRST_SHIFT (0x00000017U)
5716 #define CSL_DSS_VP2_CONFIG_FIDFIRST_MAX (0x00000001U)
5717 
5718 #define CSL_DSS_VP2_CONFIG_FIDFIRST_VAL_EVEN (0x0U)
5719 #define CSL_DSS_VP2_CONFIG_FIDFIRST_VAL_ODD (0x1U)
5720 
5721 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_MASK (0x01000000U)
5722 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_SHIFT (0x00000018U)
5723 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_MAX (0x00000001U)
5724 
5725 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_VAL_COLSPCDIS (0x0U)
5726 #define CSL_DSS_VP2_CONFIG_COLORCONVENABLE_VAL_COLSPCENB (0x1U)
5727 
5728 #define CSL_DSS_VP2_CONFIG_FULLRANGE_MASK (0x02000000U)
5729 #define CSL_DSS_VP2_CONFIG_FULLRANGE_SHIFT (0x00000019U)
5730 #define CSL_DSS_VP2_CONFIG_FULLRANGE_MAX (0x00000001U)
5731 
5732 #define CSL_DSS_VP2_CONFIG_FULLRANGE_VAL_LIMRANGE (0x0U)
5733 #define CSL_DSS_VP2_CONFIG_FULLRANGE_VAL_FULLRANGE (0x1U)
5734 
5735 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_MASK (0x04000000U)
5736 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_SHIFT (0x0000001AU)
5737 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_MAX (0x00000001U)
5738 
5739 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA (0x0U)
5740 #define CSL_DSS_VP2_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA (0x1U)
5741 
5742 #define CSL_DSS_VP2_CONFIG_RESERVED3_MASK (0xF8000000U)
5743 #define CSL_DSS_VP2_CONFIG_RESERVED3_SHIFT (0x0000001BU)
5744 #define CSL_DSS_VP2_CONFIG_RESERVED3_MAX (0x0000001FU)
5745 
5746 /* CONTROL */
5747 
5748 #define CSL_DSS_VP2_CONTROL_ENABLE_MASK (0x00000001U)
5749 #define CSL_DSS_VP2_CONTROL_ENABLE_SHIFT (0x00000000U)
5750 #define CSL_DSS_VP2_CONTROL_ENABLE_MAX (0x00000001U)
5751 
5752 #define CSL_DSS_VP2_CONTROL_ENABLE_VAL_LCDOPDIS (0x0U)
5753 #define CSL_DSS_VP2_CONTROL_ENABLE_VAL_LCDOPENB (0x1U)
5754 
5755 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_MASK (0x00000002U)
5756 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_SHIFT (0x00000001U)
5757 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_MAX (0x00000001U)
5758 
5759 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODDIS (0x0U)
5760 #define CSL_DSS_VP2_CONTROL_VPPROGLINENUMBERMODULO_VAL_MODEN (0x1U)
5761 
5762 #define CSL_DSS_VP2_CONTROL_MONOCOLOR_MASK (0x00000004U)
5763 #define CSL_DSS_VP2_CONTROL_MONOCOLOR_SHIFT (0x00000002U)
5764 #define CSL_DSS_VP2_CONTROL_MONOCOLOR_MAX (0x00000001U)
5765 
5766 #define CSL_DSS_VP2_CONTROL_STN_MASK (0x00000008U)
5767 #define CSL_DSS_VP2_CONTROL_STN_SHIFT (0x00000003U)
5768 #define CSL_DSS_VP2_CONTROL_STN_MAX (0x00000001U)
5769 
5770 #define CSL_DSS_VP2_CONTROL_M8B_MASK (0x00000010U)
5771 #define CSL_DSS_VP2_CONTROL_M8B_SHIFT (0x00000004U)
5772 #define CSL_DSS_VP2_CONTROL_M8B_MAX (0x00000001U)
5773 
5774 #define CSL_DSS_VP2_CONTROL_GOBIT_MASK (0x00000020U)
5775 #define CSL_DSS_VP2_CONTROL_GOBIT_SHIFT (0x00000005U)
5776 #define CSL_DSS_VP2_CONTROL_GOBIT_MAX (0x00000001U)
5777 
5778 #define CSL_DSS_VP2_CONTROL_GOBIT_VAL_HFUISR (0x0U)
5779 #define CSL_DSS_VP2_CONTROL_GOBIT_VAL_UFPSR (0x1U)
5780 
5781 #define CSL_DSS_VP2_CONTROL_DPIENABLE_MASK (0x00000040U)
5782 #define CSL_DSS_VP2_CONTROL_DPIENABLE_SHIFT (0x00000006U)
5783 #define CSL_DSS_VP2_CONTROL_DPIENABLE_MAX (0x00000001U)
5784 
5785 #define CSL_DSS_VP2_CONTROL_DPIENABLE_VAL_DPIOPDIS (0x0U)
5786 #define CSL_DSS_VP2_CONTROL_DPIENABLE_VAL_DPIOPENB (0x1U)
5787 
5788 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_MASK (0x00000080U)
5789 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_SHIFT (0x00000007U)
5790 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_MAX (0x00000001U)
5791 
5792 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_VAL_STDITHDIS (0x0U)
5793 #define CSL_DSS_VP2_CONTROL_STDITHERENABLE_VAL_STDITHENB (0x1U)
5794 
5795 #define CSL_DSS_VP2_CONTROL_DATALINES_MASK (0x00000700U)
5796 #define CSL_DSS_VP2_CONTROL_DATALINES_SHIFT (0x00000008U)
5797 #define CSL_DSS_VP2_CONTROL_DATALINES_MAX (0x00000007U)
5798 
5799 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB12B (0x0U)
5800 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB16B (0x1U)
5801 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB18B (0x2U)
5802 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB24B (0x3U)
5803 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB30B (0x4U)
5804 #define CSL_DSS_VP2_CONTROL_DATALINES_VAL_OALSB36B (0x5U)
5805 
5806 #define CSL_DSS_VP2_CONTROL_STALLMODE_MASK (0x00000800U)
5807 #define CSL_DSS_VP2_CONTROL_STALLMODE_SHIFT (0x0000000BU)
5808 #define CSL_DSS_VP2_CONTROL_STALLMODE_MAX (0x00000001U)
5809 
5810 #define CSL_DSS_VP2_CONTROL_RESERVED6_MASK (0x00001000U)
5811 #define CSL_DSS_VP2_CONTROL_RESERVED6_SHIFT (0x0000000CU)
5812 #define CSL_DSS_VP2_CONTROL_RESERVED6_MAX (0x00000001U)
5813 
5814 #define CSL_DSS_VP2_CONTROL_RESERVED3_MASK (0x00002000U)
5815 #define CSL_DSS_VP2_CONTROL_RESERVED3_SHIFT (0x0000000DU)
5816 #define CSL_DSS_VP2_CONTROL_RESERVED3_MAX (0x00000001U)
5817 
5818 #define CSL_DSS_VP2_CONTROL_HT_MASK (0x0001C000U)
5819 #define CSL_DSS_VP2_CONTROL_HT_SHIFT (0x0000000EU)
5820 #define CSL_DSS_VP2_CONTROL_HT_MAX (0x00000007U)
5821 
5822 #define CSL_DSS_VP2_CONTROL_RESERVED1_MASK (0x000E0000U)
5823 #define CSL_DSS_VP2_CONTROL_RESERVED1_SHIFT (0x00000011U)
5824 #define CSL_DSS_VP2_CONTROL_RESERVED1_MAX (0x00000007U)
5825 
5826 #define CSL_DSS_VP2_CONTROL_TDMENABLE_MASK (0x00100000U)
5827 #define CSL_DSS_VP2_CONTROL_TDMENABLE_SHIFT (0x00000014U)
5828 #define CSL_DSS_VP2_CONTROL_TDMENABLE_MAX (0x00000001U)
5829 
5830 #define CSL_DSS_VP2_CONTROL_TDMENABLE_VAL_TDMDIS (0x0U)
5831 #define CSL_DSS_VP2_CONTROL_TDMENABLE_VAL_TDMENB (0x1U)
5832 
5833 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_MASK (0x00600000U)
5834 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_SHIFT (0x00000015U)
5835 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_MAX (0x00000003U)
5836 
5837 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT (0x0U)
5838 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT (0x1U)
5839 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT (0x2U)
5840 #define CSL_DSS_VP2_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT (0x3U)
5841 
5842 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_MASK (0x01800000U)
5843 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_SHIFT (0x00000017U)
5844 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_MAX (0x00000003U)
5845 
5846 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX (0x0U)
5847 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX (0x1U)
5848 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX (0x2U)
5849 #define CSL_DSS_VP2_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX (0x3U)
5850 
5851 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_MASK (0x06000000U)
5852 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_SHIFT (0x00000019U)
5853 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_MAX (0x00000003U)
5854 
5855 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL (0x0U)
5856 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL (0x1U)
5857 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED (0x2U)
5858 #define CSL_DSS_VP2_CONTROL_TDMUNUSEDBITS_VAL_RES (0x3U)
5859 
5860 #define CSL_DSS_VP2_CONTROL_RESERVED_MASK (0x38000000U)
5861 #define CSL_DSS_VP2_CONTROL_RESERVED_SHIFT (0x0000001BU)
5862 #define CSL_DSS_VP2_CONTROL_RESERVED_MAX (0x00000007U)
5863 
5864 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MASK (0xC0000000U)
5865 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_SHIFT (0x0000001EU)
5866 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_MAX (0x00000003U)
5867 
5868 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_ONEFRAME (0x0U)
5869 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_TWOFRAMES (0x1U)
5870 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_FOURFRAMES (0x2U)
5871 #define CSL_DSS_VP2_CONTROL_SPATIALTEMPORALDITHERINGFRAMES_VAL_RESERVED (0x3U)
5872 
5873 /* CSC_COEF0 */
5874 
5875 #define CSL_DSS_VP2_CSC_COEF0_C00_MASK (0x000007FFU)
5876 #define CSL_DSS_VP2_CSC_COEF0_C00_SHIFT (0x00000000U)
5877 #define CSL_DSS_VP2_CSC_COEF0_C00_MAX (0x000007FFU)
5878 
5879 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_53_MASK (0x0000F800U)
5880 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_53_SHIFT (0x0000000BU)
5881 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_53_MAX (0x0000001FU)
5882 
5883 #define CSL_DSS_VP2_CSC_COEF0_C01_MASK (0x07FF0000U)
5884 #define CSL_DSS_VP2_CSC_COEF0_C01_SHIFT (0x00000010U)
5885 #define CSL_DSS_VP2_CSC_COEF0_C01_MAX (0x000007FFU)
5886 
5887 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_52_MASK (0xF8000000U)
5888 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_52_SHIFT (0x0000001BU)
5889 #define CSL_DSS_VP2_CSC_COEF0_RESERVED_52_MAX (0x0000001FU)
5890 
5891 /* CSC_COEF1 */
5892 
5893 #define CSL_DSS_VP2_CSC_COEF1_C02_MASK (0x000007FFU)
5894 #define CSL_DSS_VP2_CSC_COEF1_C02_SHIFT (0x00000000U)
5895 #define CSL_DSS_VP2_CSC_COEF1_C02_MAX (0x000007FFU)
5896 
5897 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_55_MASK (0x0000F800U)
5898 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_55_SHIFT (0x0000000BU)
5899 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_55_MAX (0x0000001FU)
5900 
5901 #define CSL_DSS_VP2_CSC_COEF1_C10_MASK (0x07FF0000U)
5902 #define CSL_DSS_VP2_CSC_COEF1_C10_SHIFT (0x00000010U)
5903 #define CSL_DSS_VP2_CSC_COEF1_C10_MAX (0x000007FFU)
5904 
5905 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_54_MASK (0xF8000000U)
5906 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_54_SHIFT (0x0000001BU)
5907 #define CSL_DSS_VP2_CSC_COEF1_RESERVED_54_MAX (0x0000001FU)
5908 
5909 /* CSC_COEF2 */
5910 
5911 #define CSL_DSS_VP2_CSC_COEF2_C11_MASK (0x000007FFU)
5912 #define CSL_DSS_VP2_CSC_COEF2_C11_SHIFT (0x00000000U)
5913 #define CSL_DSS_VP2_CSC_COEF2_C11_MAX (0x000007FFU)
5914 
5915 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_57_MASK (0x0000F800U)
5916 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_57_SHIFT (0x0000000BU)
5917 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_57_MAX (0x0000001FU)
5918 
5919 #define CSL_DSS_VP2_CSC_COEF2_C12_MASK (0x07FF0000U)
5920 #define CSL_DSS_VP2_CSC_COEF2_C12_SHIFT (0x00000010U)
5921 #define CSL_DSS_VP2_CSC_COEF2_C12_MAX (0x000007FFU)
5922 
5923 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_56_MASK (0xF8000000U)
5924 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_56_SHIFT (0x0000001BU)
5925 #define CSL_DSS_VP2_CSC_COEF2_RESERVED_56_MAX (0x0000001FU)
5926 
5927 /* DATA_CYCLE_0 */
5928 
5929 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL1_MASK (0x0000001FU)
5930 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL1_SHIFT (0x00000000U)
5931 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL1_MAX (0x0000001FU)
5932 
5933 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_4_MASK (0x000000E0U)
5934 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_4_SHIFT (0x00000005U)
5935 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_4_MAX (0x00000007U)
5936 
5937 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
5938 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
5939 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
5940 
5941 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_3_MASK (0x0000F000U)
5942 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_3_SHIFT (0x0000000CU)
5943 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_3_MAX (0x0000000FU)
5944 
5945 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL2_MASK (0x001F0000U)
5946 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL2_SHIFT (0x00000010U)
5947 #define CSL_DSS_VP2_DATA_CYCLE_0_NBBITSPIXEL2_MAX (0x0000001FU)
5948 
5949 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_6_MASK (0x00E00000U)
5950 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_6_SHIFT (0x00000015U)
5951 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_6_MAX (0x00000007U)
5952 
5953 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
5954 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
5955 #define CSL_DSS_VP2_DATA_CYCLE_0_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
5956 
5957 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_5_MASK (0xF0000000U)
5958 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_5_SHIFT (0x0000001CU)
5959 #define CSL_DSS_VP2_DATA_CYCLE_0_RESERVED_5_MAX (0x0000000FU)
5960 
5961 /* DATA_CYCLE_1 */
5962 
5963 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL1_MASK (0x0000001FU)
5964 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL1_SHIFT (0x00000000U)
5965 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL1_MAX (0x0000001FU)
5966 
5967 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_4_MASK (0x000000E0U)
5968 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_4_SHIFT (0x00000005U)
5969 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_4_MAX (0x00000007U)
5970 
5971 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
5972 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
5973 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
5974 
5975 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_3_MASK (0x0000F000U)
5976 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_3_SHIFT (0x0000000CU)
5977 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_3_MAX (0x0000000FU)
5978 
5979 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL2_MASK (0x001F0000U)
5980 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL2_SHIFT (0x00000010U)
5981 #define CSL_DSS_VP2_DATA_CYCLE_1_NBBITSPIXEL2_MAX (0x0000001FU)
5982 
5983 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_6_MASK (0x00E00000U)
5984 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_6_SHIFT (0x00000015U)
5985 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_6_MAX (0x00000007U)
5986 
5987 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
5988 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
5989 #define CSL_DSS_VP2_DATA_CYCLE_1_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
5990 
5991 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_5_MASK (0xF0000000U)
5992 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_5_SHIFT (0x0000001CU)
5993 #define CSL_DSS_VP2_DATA_CYCLE_1_RESERVED_5_MAX (0x0000000FU)
5994 
5995 /* DATA_CYCLE_2 */
5996 
5997 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL1_MASK (0x0000001FU)
5998 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL1_SHIFT (0x00000000U)
5999 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL1_MAX (0x0000001FU)
6000 
6001 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_4_MASK (0x000000E0U)
6002 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_4_SHIFT (0x00000005U)
6003 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_4_MAX (0x00000007U)
6004 
6005 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MASK (0x00000F00U)
6006 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL1_SHIFT (0x00000008U)
6007 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL1_MAX (0x0000000FU)
6008 
6009 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_3_MASK (0x0000F000U)
6010 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_3_SHIFT (0x0000000CU)
6011 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_3_MAX (0x0000000FU)
6012 
6013 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL2_MASK (0x001F0000U)
6014 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL2_SHIFT (0x00000010U)
6015 #define CSL_DSS_VP2_DATA_CYCLE_2_NBBITSPIXEL2_MAX (0x0000001FU)
6016 
6017 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_6_MASK (0x00E00000U)
6018 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_6_SHIFT (0x00000015U)
6019 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_6_MAX (0x00000007U)
6020 
6021 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MASK (0x0F000000U)
6022 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL2_SHIFT (0x00000018U)
6023 #define CSL_DSS_VP2_DATA_CYCLE_2_BITALIGNMENTPIXEL2_MAX (0x0000000FU)
6024 
6025 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_5_MASK (0xF0000000U)
6026 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_5_SHIFT (0x0000001CU)
6027 #define CSL_DSS_VP2_DATA_CYCLE_2_RESERVED_5_MAX (0x0000000FU)
6028 
6029 /* LINE_NUMBER */
6030 
6031 #define CSL_DSS_VP2_LINE_NUMBER_LINENUMBER_MASK (0x00000FFFU)
6032 #define CSL_DSS_VP2_LINE_NUMBER_LINENUMBER_SHIFT (0x00000000U)
6033 #define CSL_DSS_VP2_LINE_NUMBER_LINENUMBER_MAX (0x00000FFFU)
6034 
6035 #define CSL_DSS_VP2_LINE_NUMBER_RESERVED_MASK (0xFFFFF000U)
6036 #define CSL_DSS_VP2_LINE_NUMBER_RESERVED_SHIFT (0x0000000CU)
6037 #define CSL_DSS_VP2_LINE_NUMBER_RESERVED_MAX (0x000FFFFFU)
6038 
6039 /* POL_FREQ */
6040 
6041 #define CSL_DSS_VP2_POL_FREQ_ACB_MASK (0x000000FFU)
6042 #define CSL_DSS_VP2_POL_FREQ_ACB_SHIFT (0x00000000U)
6043 #define CSL_DSS_VP2_POL_FREQ_ACB_MAX (0x000000FFU)
6044 
6045 #define CSL_DSS_VP2_POL_FREQ_ACBI_MASK (0x00000F00U)
6046 #define CSL_DSS_VP2_POL_FREQ_ACBI_SHIFT (0x00000008U)
6047 #define CSL_DSS_VP2_POL_FREQ_ACBI_MAX (0x0000000FU)
6048 
6049 #define CSL_DSS_VP2_POL_FREQ_IVS_MASK (0x00001000U)
6050 #define CSL_DSS_VP2_POL_FREQ_IVS_SHIFT (0x0000000CU)
6051 #define CSL_DSS_VP2_POL_FREQ_IVS_MAX (0x00000001U)
6052 
6053 #define CSL_DSS_VP2_POL_FREQ_IVS_VAL_FCKPINAH (0x0U)
6054 #define CSL_DSS_VP2_POL_FREQ_IVS_VAL_FCKPINAL (0x1U)
6055 
6056 #define CSL_DSS_VP2_POL_FREQ_IHS_MASK (0x00002000U)
6057 #define CSL_DSS_VP2_POL_FREQ_IHS_SHIFT (0x0000000DU)
6058 #define CSL_DSS_VP2_POL_FREQ_IHS_MAX (0x00000001U)
6059 
6060 #define CSL_DSS_VP2_POL_FREQ_IHS_VAL_LCKPINAH (0x0U)
6061 #define CSL_DSS_VP2_POL_FREQ_IHS_VAL_LCKPINAL (0x1U)
6062 
6063 #define CSL_DSS_VP2_POL_FREQ_IPC_MASK (0x00004000U)
6064 #define CSL_DSS_VP2_POL_FREQ_IPC_SHIFT (0x0000000EU)
6065 #define CSL_DSS_VP2_POL_FREQ_IPC_MAX (0x00000001U)
6066 
6067 #define CSL_DSS_VP2_POL_FREQ_IPC_VAL_DRPCK (0x0U)
6068 #define CSL_DSS_VP2_POL_FREQ_IPC_VAL_DFPCK (0x1U)
6069 
6070 #define CSL_DSS_VP2_POL_FREQ_IEO_MASK (0x00008000U)
6071 #define CSL_DSS_VP2_POL_FREQ_IEO_SHIFT (0x0000000FU)
6072 #define CSL_DSS_VP2_POL_FREQ_IEO_MAX (0x00000001U)
6073 
6074 #define CSL_DSS_VP2_POL_FREQ_IEO_VAL_ACBAHIGH (0x0U)
6075 #define CSL_DSS_VP2_POL_FREQ_IEO_VAL_ACBALOW (0x1U)
6076 
6077 #define CSL_DSS_VP2_POL_FREQ_RF_MASK (0x00010000U)
6078 #define CSL_DSS_VP2_POL_FREQ_RF_SHIFT (0x00000010U)
6079 #define CSL_DSS_VP2_POL_FREQ_RF_MAX (0x00000001U)
6080 
6081 #define CSL_DSS_VP2_POL_FREQ_RF_VAL_DFEDPCK (0x0U)
6082 #define CSL_DSS_VP2_POL_FREQ_RF_VAL_DRIEDPCK (0x1U)
6083 
6084 #define CSL_DSS_VP2_POL_FREQ_ONOFF_MASK (0x00020000U)
6085 #define CSL_DSS_VP2_POL_FREQ_ONOFF_SHIFT (0x00000011U)
6086 #define CSL_DSS_VP2_POL_FREQ_ONOFF_MAX (0x00000001U)
6087 
6088 #define CSL_DSS_VP2_POL_FREQ_ONOFF_VAL_DOPEDPCK (0x0U)
6089 #define CSL_DSS_VP2_POL_FREQ_ONOFF_VAL_DBIT16 (0x1U)
6090 
6091 #define CSL_DSS_VP2_POL_FREQ_ALIGN_MASK (0x00040000U)
6092 #define CSL_DSS_VP2_POL_FREQ_ALIGN_SHIFT (0x00000012U)
6093 #define CSL_DSS_VP2_POL_FREQ_ALIGN_MAX (0x00000001U)
6094 
6095 #define CSL_DSS_VP2_POL_FREQ_ALIGN_VAL_NOTALIGNED (0x0U)
6096 #define CSL_DSS_VP2_POL_FREQ_ALIGN_VAL_ALIGNED (0x1U)
6097 
6098 #define CSL_DSS_VP2_POL_FREQ_RESERVED_MASK (0xFFF80000U)
6099 #define CSL_DSS_VP2_POL_FREQ_RESERVED_SHIFT (0x00000013U)
6100 #define CSL_DSS_VP2_POL_FREQ_RESERVED_MAX (0x00001FFFU)
6101 
6102 /* SIZE_SCREEN */
6103 
6104 #define CSL_DSS_VP2_SIZE_SCREEN_PPL_MASK (0x00000FFFU)
6105 #define CSL_DSS_VP2_SIZE_SCREEN_PPL_SHIFT (0x00000000U)
6106 #define CSL_DSS_VP2_SIZE_SCREEN_PPL_MAX (0x00000FFFU)
6107 
6108 #define CSL_DSS_VP2_SIZE_SCREEN_RESERVED_MASK (0x00003000U)
6109 #define CSL_DSS_VP2_SIZE_SCREEN_RESERVED_SHIFT (0x0000000CU)
6110 #define CSL_DSS_VP2_SIZE_SCREEN_RESERVED_MAX (0x00000003U)
6111 
6112 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_MASK (0x0000C000U)
6113 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_SHIFT (0x0000000EU)
6114 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_MAX (0x00000003U)
6115 
6116 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_VAL_SAME (0x0U)
6117 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE (0x1U)
6118 #define CSL_DSS_VP2_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE (0x2U)
6119 
6120 #define CSL_DSS_VP2_SIZE_SCREEN_LPP_MASK (0x0FFF0000U)
6121 #define CSL_DSS_VP2_SIZE_SCREEN_LPP_SHIFT (0x00000010U)
6122 #define CSL_DSS_VP2_SIZE_SCREEN_LPP_MAX (0x00000FFFU)
6123 
6124 #define CSL_DSS_VP2_SIZE_SCREEN_RESERVED1_MASK (0xF0000000U)
6125 #define CSL_DSS_VP2_SIZE_SCREEN_RESERVED1_SHIFT (0x0000001CU)
6126 #define CSL_DSS_VP2_SIZE_SCREEN_RESERVED1_MAX (0x0000000FU)
6127 
6128 /* TIMING_H */
6129 
6130 #define CSL_DSS_VP2_TIMING_H_HSW_MASK (0x000000FFU)
6131 #define CSL_DSS_VP2_TIMING_H_HSW_SHIFT (0x00000000U)
6132 #define CSL_DSS_VP2_TIMING_H_HSW_MAX (0x000000FFU)
6133 
6134 #define CSL_DSS_VP2_TIMING_H_HFP_MASK (0x000FFF00U)
6135 #define CSL_DSS_VP2_TIMING_H_HFP_SHIFT (0x00000008U)
6136 #define CSL_DSS_VP2_TIMING_H_HFP_MAX (0x00000FFFU)
6137 
6138 #define CSL_DSS_VP2_TIMING_H_HBP_MASK (0xFFF00000U)
6139 #define CSL_DSS_VP2_TIMING_H_HBP_SHIFT (0x00000014U)
6140 #define CSL_DSS_VP2_TIMING_H_HBP_MAX (0x00000FFFU)
6141 
6142 /* TIMING_V */
6143 
6144 #define CSL_DSS_VP2_TIMING_V_VSW_MASK (0x000000FFU)
6145 #define CSL_DSS_VP2_TIMING_V_VSW_SHIFT (0x00000000U)
6146 #define CSL_DSS_VP2_TIMING_V_VSW_MAX (0x000000FFU)
6147 
6148 #define CSL_DSS_VP2_TIMING_V_VFP_MASK (0x000FFF00U)
6149 #define CSL_DSS_VP2_TIMING_V_VFP_SHIFT (0x00000008U)
6150 #define CSL_DSS_VP2_TIMING_V_VFP_MAX (0x00000FFFU)
6151 
6152 #define CSL_DSS_VP2_TIMING_V_VBP_MASK (0xFFF00000U)
6153 #define CSL_DSS_VP2_TIMING_V_VBP_SHIFT (0x00000014U)
6154 #define CSL_DSS_VP2_TIMING_V_VBP_MAX (0x00000FFFU)
6155 
6156 /* CSC_COEF3 */
6157 
6158 #define CSL_DSS_VP2_CSC_COEF3_C20_MASK (0x000007FFU)
6159 #define CSL_DSS_VP2_CSC_COEF3_C20_SHIFT (0x00000000U)
6160 #define CSL_DSS_VP2_CSC_COEF3_C20_MAX (0x000007FFU)
6161 
6162 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_59_MASK (0x0000F800U)
6163 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_59_SHIFT (0x0000000BU)
6164 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_59_MAX (0x0000001FU)
6165 
6166 #define CSL_DSS_VP2_CSC_COEF3_C21_MASK (0x07FF0000U)
6167 #define CSL_DSS_VP2_CSC_COEF3_C21_SHIFT (0x00000010U)
6168 #define CSL_DSS_VP2_CSC_COEF3_C21_MAX (0x000007FFU)
6169 
6170 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_58_MASK (0xF8000000U)
6171 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_58_SHIFT (0x0000001BU)
6172 #define CSL_DSS_VP2_CSC_COEF3_RESERVED_58_MAX (0x0000001FU)
6173 
6174 /* CSC_COEF4 */
6175 
6176 #define CSL_DSS_VP2_CSC_COEF4_C22_MASK (0x000007FFU)
6177 #define CSL_DSS_VP2_CSC_COEF4_C22_SHIFT (0x00000000U)
6178 #define CSL_DSS_VP2_CSC_COEF4_C22_MAX (0x000007FFU)
6179 
6180 #define CSL_DSS_VP2_CSC_COEF4_RESERVED_60_MASK (0xFFFFF800U)
6181 #define CSL_DSS_VP2_CSC_COEF4_RESERVED_60_SHIFT (0x0000000BU)
6182 #define CSL_DSS_VP2_CSC_COEF4_RESERVED_60_MAX (0x001FFFFFU)
6183 
6184 /* CSC_COEF5 */
6185 
6186 #define CSL_DSS_VP2_CSC_COEF5_RESERVED_MASK (0x00000007U)
6187 #define CSL_DSS_VP2_CSC_COEF5_RESERVED_SHIFT (0x00000000U)
6188 #define CSL_DSS_VP2_CSC_COEF5_RESERVED_MAX (0x00000007U)
6189 
6190 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET1_MASK (0x0000FFF8U)
6191 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET1_SHIFT (0x00000003U)
6192 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET1_MAX (0x00001FFFU)
6193 
6194 #define CSL_DSS_VP2_CSC_COEF5_RESERVED1_MASK (0x00070000U)
6195 #define CSL_DSS_VP2_CSC_COEF5_RESERVED1_SHIFT (0x00000010U)
6196 #define CSL_DSS_VP2_CSC_COEF5_RESERVED1_MAX (0x00000007U)
6197 
6198 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET2_MASK (0xFFF80000U)
6199 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET2_SHIFT (0x00000013U)
6200 #define CSL_DSS_VP2_CSC_COEF5_PREOFFSET2_MAX (0x00001FFFU)
6201 
6202 /* CSC_COEF6 */
6203 
6204 #define CSL_DSS_VP2_CSC_COEF6_RESERVED_MASK (0x00000007U)
6205 #define CSL_DSS_VP2_CSC_COEF6_RESERVED_SHIFT (0x00000000U)
6206 #define CSL_DSS_VP2_CSC_COEF6_RESERVED_MAX (0x00000007U)
6207 
6208 #define CSL_DSS_VP2_CSC_COEF6_PREOFFSET3_MASK (0x0000FFF8U)
6209 #define CSL_DSS_VP2_CSC_COEF6_PREOFFSET3_SHIFT (0x00000003U)
6210 #define CSL_DSS_VP2_CSC_COEF6_PREOFFSET3_MAX (0x00001FFFU)
6211 
6212 #define CSL_DSS_VP2_CSC_COEF6_RESERVED1_MASK (0x00070000U)
6213 #define CSL_DSS_VP2_CSC_COEF6_RESERVED1_SHIFT (0x00000010U)
6214 #define CSL_DSS_VP2_CSC_COEF6_RESERVED1_MAX (0x00000007U)
6215 
6216 #define CSL_DSS_VP2_CSC_COEF6_POSTOFFSET1_MASK (0xFFF80000U)
6217 #define CSL_DSS_VP2_CSC_COEF6_POSTOFFSET1_SHIFT (0x00000013U)
6218 #define CSL_DSS_VP2_CSC_COEF6_POSTOFFSET1_MAX (0x00001FFFU)
6219 
6220 /* CSC_COEF7 */
6221 
6222 #define CSL_DSS_VP2_CSC_COEF7_RESERVED_MASK (0x00000007U)
6223 #define CSL_DSS_VP2_CSC_COEF7_RESERVED_SHIFT (0x00000000U)
6224 #define CSL_DSS_VP2_CSC_COEF7_RESERVED_MAX (0x00000007U)
6225 
6226 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET2_MASK (0x0000FFF8U)
6227 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET2_SHIFT (0x00000003U)
6228 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET2_MAX (0x00001FFFU)
6229 
6230 #define CSL_DSS_VP2_CSC_COEF7_RESERVED1_MASK (0x00070000U)
6231 #define CSL_DSS_VP2_CSC_COEF7_RESERVED1_SHIFT (0x00000010U)
6232 #define CSL_DSS_VP2_CSC_COEF7_RESERVED1_MAX (0x00000007U)
6233 
6234 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET3_MASK (0xFFF80000U)
6235 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET3_SHIFT (0x00000013U)
6236 #define CSL_DSS_VP2_CSC_COEF7_POSTOFFSET3_MAX (0x00001FFFU)
6237 
6238 /* SAFETY_ATTRIBUTES */
6239 
6240 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_ENABLE_MASK (0x00000001U)
6241 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_ENABLE_SHIFT (0x00000000U)
6242 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_ENABLE_MAX (0x00000001U)
6243 
6244 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_MASK (0x00000002U)
6245 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_SHIFT (0x00000001U)
6246 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_MAX (0x00000001U)
6247 
6248 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE (0x0U)
6249 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK (0x1U)
6250 
6251 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_MASK (0x00000004U)
6252 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_SHIFT (0x00000002U)
6253 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_MAX (0x00000001U)
6254 
6255 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_DISABLE (0x0U)
6256 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_SEEDSELECT_VAL_ENABLE (0x1U)
6257 
6258 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_THRESHOLD_MASK (0x000007F8U)
6259 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_THRESHOLD_SHIFT (0x00000003U)
6260 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_THRESHOLD_MAX (0x000000FFU)
6261 
6262 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_MASK (0x00001800U)
6263 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_SHIFT (0x0000000BU)
6264 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_MAX (0x00000003U)
6265 
6266 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_NOSKIP (0x0U)
6267 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN (0x1U)
6268 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD (0x2U)
6269 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_RESERVED (0x3U)
6270 
6271 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_RESERVED_MASK (0xFFFFE000U)
6272 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_RESERVED_SHIFT (0x0000000DU)
6273 #define CSL_DSS_VP2_SAFETY_ATTRIBUTES_RESERVED_MAX (0x0007FFFFU)
6274 
6275 /* SAFETY_CAPT_SIGNATURE */
6276 
6277 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
6278 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
6279 #define CSL_DSS_VP2_SAFETY_CAPT_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
6280 
6281 /* SAFETY_POSITION */
6282 
6283 #define CSL_DSS_VP2_SAFETY_POSITION_POSX_MASK (0x00000FFFU)
6284 #define CSL_DSS_VP2_SAFETY_POSITION_POSX_SHIFT (0x00000000U)
6285 #define CSL_DSS_VP2_SAFETY_POSITION_POSX_MAX (0x00000FFFU)
6286 
6287 #define CSL_DSS_VP2_SAFETY_POSITION_RESERVED1_MASK (0x0000F000U)
6288 #define CSL_DSS_VP2_SAFETY_POSITION_RESERVED1_SHIFT (0x0000000CU)
6289 #define CSL_DSS_VP2_SAFETY_POSITION_RESERVED1_MAX (0x0000000FU)
6290 
6291 #define CSL_DSS_VP2_SAFETY_POSITION_POSY_MASK (0x0FFF0000U)
6292 #define CSL_DSS_VP2_SAFETY_POSITION_POSY_SHIFT (0x00000010U)
6293 #define CSL_DSS_VP2_SAFETY_POSITION_POSY_MAX (0x00000FFFU)
6294 
6295 #define CSL_DSS_VP2_SAFETY_POSITION_RESERVED_MASK (0xF0000000U)
6296 #define CSL_DSS_VP2_SAFETY_POSITION_RESERVED_SHIFT (0x0000001CU)
6297 #define CSL_DSS_VP2_SAFETY_POSITION_RESERVED_MAX (0x0000000FU)
6298 
6299 /* SAFETY_REF_SIGNATURE */
6300 
6301 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE_SIGNATURE_MASK (0xFFFFFFFFU)
6302 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE_SIGNATURE_SHIFT (0x00000000U)
6303 #define CSL_DSS_VP2_SAFETY_REF_SIGNATURE_SIGNATURE_MAX (0xFFFFFFFFU)
6304 
6305 /* SAFETY_SIZE */
6306 
6307 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEX_MASK (0x00000FFFU)
6308 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEX_SHIFT (0x00000000U)
6309 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEX_MAX (0x00000FFFU)
6310 
6311 #define CSL_DSS_VP2_SAFETY_SIZE_RESERVED1_MASK (0x0000F000U)
6312 #define CSL_DSS_VP2_SAFETY_SIZE_RESERVED1_SHIFT (0x0000000CU)
6313 #define CSL_DSS_VP2_SAFETY_SIZE_RESERVED1_MAX (0x0000000FU)
6314 
6315 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEY_MASK (0x0FFF0000U)
6316 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEY_SHIFT (0x00000010U)
6317 #define CSL_DSS_VP2_SAFETY_SIZE_SIZEY_MAX (0x00000FFFU)
6318 
6319 #define CSL_DSS_VP2_SAFETY_SIZE_RESERVED_MASK (0xF0000000U)
6320 #define CSL_DSS_VP2_SAFETY_SIZE_RESERVED_SHIFT (0x0000001CU)
6321 #define CSL_DSS_VP2_SAFETY_SIZE_RESERVED_MAX (0x0000000FU)
6322 
6323 /* SAFETY_LFSR_SEED */
6324 
6325 #define CSL_DSS_VP2_SAFETY_LFSR_SEED_SEED_MASK (0xFFFFFFFFU)
6326 #define CSL_DSS_VP2_SAFETY_LFSR_SEED_SEED_SHIFT (0x00000000U)
6327 #define CSL_DSS_VP2_SAFETY_LFSR_SEED_SEED_MAX (0xFFFFFFFFU)
6328 
6329 /* GAMMA_TABLE_0 */
6330 
6331 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_B_MASK (0x000000FFU)
6332 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_B_SHIFT (0x00000000U)
6333 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_B_MAX (0x000000FFU)
6334 
6335 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_G_MASK (0x0000FF00U)
6336 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_G_SHIFT (0x00000008U)
6337 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_G_MAX (0x000000FFU)
6338 
6339 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_R_MASK (0x00FF0000U)
6340 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_R_SHIFT (0x00000010U)
6341 #define CSL_DSS_VP2_GAMMA_TABLE_0_VALUE_R_MAX (0x000000FFU)
6342 
6343 #define CSL_DSS_VP2_GAMMA_TABLE_0_INDEX_MASK (0xFF000000U)
6344 #define CSL_DSS_VP2_GAMMA_TABLE_0_INDEX_SHIFT (0x00000018U)
6345 #define CSL_DSS_VP2_GAMMA_TABLE_0_INDEX_MAX (0x000000FFU)
6346 
6347 /* GAMMA_TABLE_1 */
6348 
6349 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_B_MASK (0x000000FFU)
6350 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_B_SHIFT (0x00000000U)
6351 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_B_MAX (0x000000FFU)
6352 
6353 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_G_MASK (0x0000FF00U)
6354 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_G_SHIFT (0x00000008U)
6355 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_G_MAX (0x000000FFU)
6356 
6357 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_R_MASK (0x00FF0000U)
6358 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_R_SHIFT (0x00000010U)
6359 #define CSL_DSS_VP2_GAMMA_TABLE_1_VALUE_R_MAX (0x000000FFU)
6360 
6361 #define CSL_DSS_VP2_GAMMA_TABLE_1_INDEX_MASK (0xFF000000U)
6362 #define CSL_DSS_VP2_GAMMA_TABLE_1_INDEX_SHIFT (0x00000018U)
6363 #define CSL_DSS_VP2_GAMMA_TABLE_1_INDEX_MAX (0x000000FFU)
6364 
6365 /* GAMMA_TABLE_2 */
6366 
6367 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_B_MASK (0x000000FFU)
6368 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_B_SHIFT (0x00000000U)
6369 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_B_MAX (0x000000FFU)
6370 
6371 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_G_MASK (0x0000FF00U)
6372 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_G_SHIFT (0x00000008U)
6373 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_G_MAX (0x000000FFU)
6374 
6375 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_R_MASK (0x00FF0000U)
6376 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_R_SHIFT (0x00000010U)
6377 #define CSL_DSS_VP2_GAMMA_TABLE_2_VALUE_R_MAX (0x000000FFU)
6378 
6379 #define CSL_DSS_VP2_GAMMA_TABLE_2_INDEX_MASK (0xFF000000U)
6380 #define CSL_DSS_VP2_GAMMA_TABLE_2_INDEX_SHIFT (0x00000018U)
6381 #define CSL_DSS_VP2_GAMMA_TABLE_2_INDEX_MAX (0x000000FFU)
6382 
6383 /* GAMMA_TABLE_3 */
6384 
6385 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_B_MASK (0x000000FFU)
6386 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_B_SHIFT (0x00000000U)
6387 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_B_MAX (0x000000FFU)
6388 
6389 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_G_MASK (0x0000FF00U)
6390 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_G_SHIFT (0x00000008U)
6391 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_G_MAX (0x000000FFU)
6392 
6393 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_R_MASK (0x00FF0000U)
6394 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_R_SHIFT (0x00000010U)
6395 #define CSL_DSS_VP2_GAMMA_TABLE_3_VALUE_R_MAX (0x000000FFU)
6396 
6397 #define CSL_DSS_VP2_GAMMA_TABLE_3_INDEX_MASK (0xFF000000U)
6398 #define CSL_DSS_VP2_GAMMA_TABLE_3_INDEX_SHIFT (0x00000018U)
6399 #define CSL_DSS_VP2_GAMMA_TABLE_3_INDEX_MAX (0x000000FFU)
6400 
6401 /* GAMMA_TABLE_4 */
6402 
6403 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_B_MASK (0x000000FFU)
6404 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_B_SHIFT (0x00000000U)
6405 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_B_MAX (0x000000FFU)
6406 
6407 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_G_MASK (0x0000FF00U)
6408 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_G_SHIFT (0x00000008U)
6409 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_G_MAX (0x000000FFU)
6410 
6411 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_R_MASK (0x00FF0000U)
6412 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_R_SHIFT (0x00000010U)
6413 #define CSL_DSS_VP2_GAMMA_TABLE_4_VALUE_R_MAX (0x000000FFU)
6414 
6415 #define CSL_DSS_VP2_GAMMA_TABLE_4_INDEX_MASK (0xFF000000U)
6416 #define CSL_DSS_VP2_GAMMA_TABLE_4_INDEX_SHIFT (0x00000018U)
6417 #define CSL_DSS_VP2_GAMMA_TABLE_4_INDEX_MAX (0x000000FFU)
6418 
6419 /* GAMMA_TABLE_5 */
6420 
6421 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_B_MASK (0x000000FFU)
6422 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_B_SHIFT (0x00000000U)
6423 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_B_MAX (0x000000FFU)
6424 
6425 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_G_MASK (0x0000FF00U)
6426 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_G_SHIFT (0x00000008U)
6427 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_G_MAX (0x000000FFU)
6428 
6429 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_R_MASK (0x00FF0000U)
6430 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_R_SHIFT (0x00000010U)
6431 #define CSL_DSS_VP2_GAMMA_TABLE_5_VALUE_R_MAX (0x000000FFU)
6432 
6433 #define CSL_DSS_VP2_GAMMA_TABLE_5_INDEX_MASK (0xFF000000U)
6434 #define CSL_DSS_VP2_GAMMA_TABLE_5_INDEX_SHIFT (0x00000018U)
6435 #define CSL_DSS_VP2_GAMMA_TABLE_5_INDEX_MAX (0x000000FFU)
6436 
6437 /* GAMMA_TABLE_6 */
6438 
6439 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_B_MASK (0x000000FFU)
6440 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_B_SHIFT (0x00000000U)
6441 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_B_MAX (0x000000FFU)
6442 
6443 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_G_MASK (0x0000FF00U)
6444 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_G_SHIFT (0x00000008U)
6445 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_G_MAX (0x000000FFU)
6446 
6447 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_R_MASK (0x00FF0000U)
6448 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_R_SHIFT (0x00000010U)
6449 #define CSL_DSS_VP2_GAMMA_TABLE_6_VALUE_R_MAX (0x000000FFU)
6450 
6451 #define CSL_DSS_VP2_GAMMA_TABLE_6_INDEX_MASK (0xFF000000U)
6452 #define CSL_DSS_VP2_GAMMA_TABLE_6_INDEX_SHIFT (0x00000018U)
6453 #define CSL_DSS_VP2_GAMMA_TABLE_6_INDEX_MAX (0x000000FFU)
6454 
6455 /* GAMMA_TABLE_7 */
6456 
6457 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_B_MASK (0x000000FFU)
6458 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_B_SHIFT (0x00000000U)
6459 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_B_MAX (0x000000FFU)
6460 
6461 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_G_MASK (0x0000FF00U)
6462 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_G_SHIFT (0x00000008U)
6463 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_G_MAX (0x000000FFU)
6464 
6465 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_R_MASK (0x00FF0000U)
6466 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_R_SHIFT (0x00000010U)
6467 #define CSL_DSS_VP2_GAMMA_TABLE_7_VALUE_R_MAX (0x000000FFU)
6468 
6469 #define CSL_DSS_VP2_GAMMA_TABLE_7_INDEX_MASK (0xFF000000U)
6470 #define CSL_DSS_VP2_GAMMA_TABLE_7_INDEX_SHIFT (0x00000018U)
6471 #define CSL_DSS_VP2_GAMMA_TABLE_7_INDEX_MAX (0x000000FFU)
6472 
6473 /* GAMMA_TABLE_8 */
6474 
6475 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_B_MASK (0x000000FFU)
6476 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_B_SHIFT (0x00000000U)
6477 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_B_MAX (0x000000FFU)
6478 
6479 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_G_MASK (0x0000FF00U)
6480 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_G_SHIFT (0x00000008U)
6481 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_G_MAX (0x000000FFU)
6482 
6483 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_R_MASK (0x00FF0000U)
6484 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_R_SHIFT (0x00000010U)
6485 #define CSL_DSS_VP2_GAMMA_TABLE_8_VALUE_R_MAX (0x000000FFU)
6486 
6487 #define CSL_DSS_VP2_GAMMA_TABLE_8_INDEX_MASK (0xFF000000U)
6488 #define CSL_DSS_VP2_GAMMA_TABLE_8_INDEX_SHIFT (0x00000018U)
6489 #define CSL_DSS_VP2_GAMMA_TABLE_8_INDEX_MAX (0x000000FFU)
6490 
6491 /* GAMMA_TABLE_9 */
6492 
6493 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_B_MASK (0x000000FFU)
6494 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_B_SHIFT (0x00000000U)
6495 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_B_MAX (0x000000FFU)
6496 
6497 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_G_MASK (0x0000FF00U)
6498 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_G_SHIFT (0x00000008U)
6499 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_G_MAX (0x000000FFU)
6500 
6501 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_R_MASK (0x00FF0000U)
6502 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_R_SHIFT (0x00000010U)
6503 #define CSL_DSS_VP2_GAMMA_TABLE_9_VALUE_R_MAX (0x000000FFU)
6504 
6505 #define CSL_DSS_VP2_GAMMA_TABLE_9_INDEX_MASK (0xFF000000U)
6506 #define CSL_DSS_VP2_GAMMA_TABLE_9_INDEX_SHIFT (0x00000018U)
6507 #define CSL_DSS_VP2_GAMMA_TABLE_9_INDEX_MAX (0x000000FFU)
6508 
6509 /* GAMMA_TABLE_10 */
6510 
6511 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_B_MASK (0x000000FFU)
6512 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_B_SHIFT (0x00000000U)
6513 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_B_MAX (0x000000FFU)
6514 
6515 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_G_MASK (0x0000FF00U)
6516 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_G_SHIFT (0x00000008U)
6517 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_G_MAX (0x000000FFU)
6518 
6519 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_R_MASK (0x00FF0000U)
6520 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_R_SHIFT (0x00000010U)
6521 #define CSL_DSS_VP2_GAMMA_TABLE_10_VALUE_R_MAX (0x000000FFU)
6522 
6523 #define CSL_DSS_VP2_GAMMA_TABLE_10_INDEX_MASK (0xFF000000U)
6524 #define CSL_DSS_VP2_GAMMA_TABLE_10_INDEX_SHIFT (0x00000018U)
6525 #define CSL_DSS_VP2_GAMMA_TABLE_10_INDEX_MAX (0x000000FFU)
6526 
6527 /* GAMMA_TABLE_11 */
6528 
6529 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_B_MASK (0x000000FFU)
6530 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_B_SHIFT (0x00000000U)
6531 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_B_MAX (0x000000FFU)
6532 
6533 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_G_MASK (0x0000FF00U)
6534 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_G_SHIFT (0x00000008U)
6535 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_G_MAX (0x000000FFU)
6536 
6537 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_R_MASK (0x00FF0000U)
6538 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_R_SHIFT (0x00000010U)
6539 #define CSL_DSS_VP2_GAMMA_TABLE_11_VALUE_R_MAX (0x000000FFU)
6540 
6541 #define CSL_DSS_VP2_GAMMA_TABLE_11_INDEX_MASK (0xFF000000U)
6542 #define CSL_DSS_VP2_GAMMA_TABLE_11_INDEX_SHIFT (0x00000018U)
6543 #define CSL_DSS_VP2_GAMMA_TABLE_11_INDEX_MAX (0x000000FFU)
6544 
6545 /* GAMMA_TABLE_12 */
6546 
6547 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_B_MASK (0x000000FFU)
6548 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_B_SHIFT (0x00000000U)
6549 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_B_MAX (0x000000FFU)
6550 
6551 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_G_MASK (0x0000FF00U)
6552 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_G_SHIFT (0x00000008U)
6553 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_G_MAX (0x000000FFU)
6554 
6555 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_R_MASK (0x00FF0000U)
6556 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_R_SHIFT (0x00000010U)
6557 #define CSL_DSS_VP2_GAMMA_TABLE_12_VALUE_R_MAX (0x000000FFU)
6558 
6559 #define CSL_DSS_VP2_GAMMA_TABLE_12_INDEX_MASK (0xFF000000U)
6560 #define CSL_DSS_VP2_GAMMA_TABLE_12_INDEX_SHIFT (0x00000018U)
6561 #define CSL_DSS_VP2_GAMMA_TABLE_12_INDEX_MAX (0x000000FFU)
6562 
6563 /* GAMMA_TABLE_13 */
6564 
6565 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_B_MASK (0x000000FFU)
6566 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_B_SHIFT (0x00000000U)
6567 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_B_MAX (0x000000FFU)
6568 
6569 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_G_MASK (0x0000FF00U)
6570 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_G_SHIFT (0x00000008U)
6571 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_G_MAX (0x000000FFU)
6572 
6573 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_R_MASK (0x00FF0000U)
6574 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_R_SHIFT (0x00000010U)
6575 #define CSL_DSS_VP2_GAMMA_TABLE_13_VALUE_R_MAX (0x000000FFU)
6576 
6577 #define CSL_DSS_VP2_GAMMA_TABLE_13_INDEX_MASK (0xFF000000U)
6578 #define CSL_DSS_VP2_GAMMA_TABLE_13_INDEX_SHIFT (0x00000018U)
6579 #define CSL_DSS_VP2_GAMMA_TABLE_13_INDEX_MAX (0x000000FFU)
6580 
6581 /* GAMMA_TABLE_14 */
6582 
6583 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_B_MASK (0x000000FFU)
6584 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_B_SHIFT (0x00000000U)
6585 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_B_MAX (0x000000FFU)
6586 
6587 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_G_MASK (0x0000FF00U)
6588 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_G_SHIFT (0x00000008U)
6589 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_G_MAX (0x000000FFU)
6590 
6591 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_R_MASK (0x00FF0000U)
6592 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_R_SHIFT (0x00000010U)
6593 #define CSL_DSS_VP2_GAMMA_TABLE_14_VALUE_R_MAX (0x000000FFU)
6594 
6595 #define CSL_DSS_VP2_GAMMA_TABLE_14_INDEX_MASK (0xFF000000U)
6596 #define CSL_DSS_VP2_GAMMA_TABLE_14_INDEX_SHIFT (0x00000018U)
6597 #define CSL_DSS_VP2_GAMMA_TABLE_14_INDEX_MAX (0x000000FFU)
6598 
6599 /* GAMMA_TABLE_15 */
6600 
6601 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_B_MASK (0x000000FFU)
6602 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_B_SHIFT (0x00000000U)
6603 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_B_MAX (0x000000FFU)
6604 
6605 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_G_MASK (0x0000FF00U)
6606 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_G_SHIFT (0x00000008U)
6607 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_G_MAX (0x000000FFU)
6608 
6609 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_R_MASK (0x00FF0000U)
6610 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_R_SHIFT (0x00000010U)
6611 #define CSL_DSS_VP2_GAMMA_TABLE_15_VALUE_R_MAX (0x000000FFU)
6612 
6613 #define CSL_DSS_VP2_GAMMA_TABLE_15_INDEX_MASK (0xFF000000U)
6614 #define CSL_DSS_VP2_GAMMA_TABLE_15_INDEX_SHIFT (0x00000018U)
6615 #define CSL_DSS_VP2_GAMMA_TABLE_15_INDEX_MAX (0x000000FFU)
6616 
6617 /* DSS_OLDI_CFG */
6618 
6619 #define CSL_DSS_VP2_DSS_OLDI_CFG_ENABLE_MASK (0x00000001U)
6620 #define CSL_DSS_VP2_DSS_OLDI_CFG_ENABLE_SHIFT (0x00000000U)
6621 #define CSL_DSS_VP2_DSS_OLDI_CFG_ENABLE_MAX (0x00000001U)
6622 
6623 #define CSL_DSS_VP2_DSS_OLDI_CFG_ENABLE_VAL_DISABLED (0x0U)
6624 #define CSL_DSS_VP2_DSS_OLDI_CFG_ENABLE_VAL_ENABLED (0x1U)
6625 
6626 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_MASK (0x0000000EU)
6627 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_SHIFT (0x00000001U)
6628 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_MAX (0x00000007U)
6629 
6630 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_VAL_TYPE_A (0x0U)
6631 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_VAL_TYPE_B (0x1U)
6632 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_VAL_TYPE_C (0x2U)
6633 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_VAL_TYPE_D (0x4U)
6634 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_VAL_TYPE_E (0x5U)
6635 #define CSL_DSS_VP2_DSS_OLDI_CFG_MAP_VAL_TYPE_F (0x6U)
6636 
6637 #define CSL_DSS_VP2_DSS_OLDI_CFG_SRC_MASK (0x00000010U)
6638 #define CSL_DSS_VP2_DSS_OLDI_CFG_SRC_SHIFT (0x00000004U)
6639 #define CSL_DSS_VP2_DSS_OLDI_CFG_SRC_MAX (0x00000001U)
6640 
6641 #define CSL_DSS_VP2_DSS_OLDI_CFG_SRC_VAL_CHANNEL0 (0x0U)
6642 #define CSL_DSS_VP2_DSS_OLDI_CFG_SRC_VAL_CHANNEL1 (0x1U)
6643 
6644 #define CSL_DSS_VP2_DSS_OLDI_CFG_MODE_MASK (0x00000020U)
6645 #define CSL_DSS_VP2_DSS_OLDI_CFG_MODE_SHIFT (0x00000005U)
6646 #define CSL_DSS_VP2_DSS_OLDI_CFG_MODE_MAX (0x00000001U)
6647 
6648 #define CSL_DSS_VP2_DSS_OLDI_CFG_MODE_VAL_SINGLE (0x0U)
6649 #define CSL_DSS_VP2_DSS_OLDI_CFG_MODE_VAL_DUPLICATE (0x1U)
6650 
6651 #define CSL_DSS_VP2_DSS_OLDI_CFG_MASTERSLAVE_MASK (0x00000040U)
6652 #define CSL_DSS_VP2_DSS_OLDI_CFG_MASTERSLAVE_SHIFT (0x00000006U)
6653 #define CSL_DSS_VP2_DSS_OLDI_CFG_MASTERSLAVE_MAX (0x00000001U)
6654 
6655 #define CSL_DSS_VP2_DSS_OLDI_CFG_MASTERSLAVE_VAL_MASTER (0x0U)
6656 #define CSL_DSS_VP2_DSS_OLDI_CFG_MASTERSLAVE_VAL_SLAVE (0x1U)
6657 
6658 #define CSL_DSS_VP2_DSS_OLDI_CFG_DEPOL_MASK (0x00000080U)
6659 #define CSL_DSS_VP2_DSS_OLDI_CFG_DEPOL_SHIFT (0x00000007U)
6660 #define CSL_DSS_VP2_DSS_OLDI_CFG_DEPOL_MAX (0x00000001U)
6661 
6662 #define CSL_DSS_VP2_DSS_OLDI_CFG_DEPOL_VAL_HIGH (0x0U)
6663 #define CSL_DSS_VP2_DSS_OLDI_CFG_DEPOL_VAL_LOW (0x1U)
6664 
6665 #define CSL_DSS_VP2_DSS_OLDI_CFG_MSB_MASK (0x00000100U)
6666 #define CSL_DSS_VP2_DSS_OLDI_CFG_MSB_SHIFT (0x00000008U)
6667 #define CSL_DSS_VP2_DSS_OLDI_CFG_MSB_MAX (0x00000001U)
6668 
6669 #define CSL_DSS_VP2_DSS_OLDI_CFG_MSB_VAL_18B (0x0U)
6670 #define CSL_DSS_VP2_DSS_OLDI_CFG_MSB_VAL_24B (0x1U)
6671 
6672 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBEN_MASK (0x00000200U)
6673 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBEN_SHIFT (0x00000009U)
6674 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBEN_MAX (0x00000001U)
6675 
6676 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBEN_VAL_DISABLE (0x0U)
6677 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBEN_VAL_ENABLE (0x1U)
6678 
6679 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBDATA_MASK (0x00000400U)
6680 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBDATA_SHIFT (0x0000000AU)
6681 #define CSL_DSS_VP2_DSS_OLDI_CFG_LBDATA_MAX (0x00000001U)
6682 
6683 #define CSL_DSS_VP2_DSS_OLDI_CFG_DUALMODESYNC_MASK (0x00000800U)
6684 #define CSL_DSS_VP2_DSS_OLDI_CFG_DUALMODESYNC_SHIFT (0x0000000BU)
6685 #define CSL_DSS_VP2_DSS_OLDI_CFG_DUALMODESYNC_MAX (0x00000001U)
6686 
6687 #define CSL_DSS_VP2_DSS_OLDI_CFG_DUALMODESYNC_VAL_DISABLE (0x0U)
6688 #define CSL_DSS_VP2_DSS_OLDI_CFG_DUALMODESYNC_VAL_ENABLE (0x1U)
6689 
6690 #define CSL_DSS_VP2_DSS_OLDI_CFG_SOFTRST_MASK (0x00001000U)
6691 #define CSL_DSS_VP2_DSS_OLDI_CFG_SOFTRST_SHIFT (0x0000000CU)
6692 #define CSL_DSS_VP2_DSS_OLDI_CFG_SOFTRST_MAX (0x00000001U)
6693 
6694 #define CSL_DSS_VP2_DSS_OLDI_CFG_SOFTRST_VAL_ASSERT (0x0U)
6695 #define CSL_DSS_VP2_DSS_OLDI_CFG_SOFTRST_VAL_DEASSERT (0x1U)
6696 
6697 #define CSL_DSS_VP2_DSS_OLDI_CFG_TPATCFG_MASK (0x00002000U)
6698 #define CSL_DSS_VP2_DSS_OLDI_CFG_TPATCFG_SHIFT (0x0000000DU)
6699 #define CSL_DSS_VP2_DSS_OLDI_CFG_TPATCFG_MAX (0x00000001U)
6700 
6701 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED_MASK (0xFFFFC000U)
6702 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED_SHIFT (0x0000000EU)
6703 #define CSL_DSS_VP2_DSS_OLDI_CFG_RESERVED_MAX (0x0003FFFFU)
6704 
6705 /* DSS_OLDI_STATUS */
6706 
6707 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVMIN_MASK (0x0000003FU)
6708 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVMIN_SHIFT (0x00000000U)
6709 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVMIN_MAX (0x0000003FU)
6710 
6711 #define CSL_DSS_VP2_DSS_OLDI_STATUS_CUSTOM_MASK (0x000000C0U)
6712 #define CSL_DSS_VP2_DSS_OLDI_STATUS_CUSTOM_SHIFT (0x00000006U)
6713 #define CSL_DSS_VP2_DSS_OLDI_STATUS_CUSTOM_MAX (0x00000003U)
6714 
6715 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVMAJOR_MASK (0x00000700U)
6716 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVMAJOR_SHIFT (0x00000008U)
6717 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVMAJOR_MAX (0x00000007U)
6718 
6719 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVRTL_MASK (0x0000F800U)
6720 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVRTL_SHIFT (0x0000000BU)
6721 #define CSL_DSS_VP2_DSS_OLDI_STATUS_REVRTL_MAX (0x0000001FU)
6722 
6723 #define CSL_DSS_VP2_DSS_OLDI_STATUS_MODID_MASK (0xFFFF0000U)
6724 #define CSL_DSS_VP2_DSS_OLDI_STATUS_MODID_SHIFT (0x00000010U)
6725 #define CSL_DSS_VP2_DSS_OLDI_STATUS_MODID_MAX (0x0000FFFFU)
6726 
6727 /* DSS_OLDI_LB */
6728 
6729 #define CSL_DSS_VP2_DSS_OLDI_LB_LBRDATA_MASK (0x000003FFU)
6730 #define CSL_DSS_VP2_DSS_OLDI_LB_LBRDATA_SHIFT (0x00000000U)
6731 #define CSL_DSS_VP2_DSS_OLDI_LB_LBRDATA_MAX (0x000003FFU)
6732 
6733 #define CSL_DSS_VP2_DSS_OLDI_LB_RESERVED_MASK (0xFFFFFC00U)
6734 #define CSL_DSS_VP2_DSS_OLDI_LB_RESERVED_SHIFT (0x0000000AU)
6735 #define CSL_DSS_VP2_DSS_OLDI_LB_RESERVED_MAX (0x003FFFFFU)
6736 
6737 #ifdef __cplusplus
6738 }
6739 #endif
6740 #endif
CSL_dss_vidRegs::BA_UV_0
volatile uint32_t BA_UV_0
Definition: cslr_dss.h:2607
CSL_dss_vidl1Regs::BA_EXT_0
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:1587
CSL_dss_vidRegs::ACCUH2_0
volatile uint32_t ACCUH2_0
Definition: cslr_dss.h:2597
CSL_dss_vidRegs::CLUT_9
volatile uint32_t CLUT_9
Definition: cslr_dss.h:2657
CSL_dss_vp2Regs::CONFIG
volatile uint32_t CONFIG
Definition: cslr_dss.h:5511
CSL_dss_vidRegs::ACCUH_0
volatile uint32_t ACCUH_0
Definition: cslr_dss.h:2595
CSL_dss_common1Regs::VP_IRQENABLE_0
volatile uint32_t VP_IRQENABLE_0
Definition: cslr_dss.h:971
CSL_dss_vp1Regs::GAMMA_TABLE_3
volatile uint32_t GAMMA_TABLE_3
Definition: cslr_dss.h:4310
CSL_dss_vp1Regs::CONTROL
volatile uint32_t CONTROL
Definition: cslr_dss.h:4276
CSL_dss_commonRegs::DISPC_SECURE_DISABLE
volatile uint32_t DISPC_SECURE_DISABLE
Definition: cslr_dss.h:84
CSL_dss_vidRegs::FIRH2
volatile uint32_t FIRH2
Definition: cslr_dss.h:2619
CSL_dss_vidl1Regs::BA_UV_EXT_1
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:1590
CSL_dss_vidRegs::SAFETY_ATTRIBUTES
volatile uint32_t SAFETY_ATTRIBUTES
Definition: cslr_dss.h:2664
CSL_dss_vidRegs::CLUT_14
volatile uint32_t CLUT_14
Definition: cslr_dss.h:2662
CSL_dss_vidRegs::SAFETY_REF_SIGNATURE
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:2667
CSL_dss_vidl1Regs::SAFETY_LFSR_SEED
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:1616
CSL_dss_vidRegs::LUMAKEY
volatile uint32_t LUMAKEY
Definition: cslr_dss.h:2670
CSL_dss_vp2Regs::GAMMA_TABLE_0
volatile uint32_t GAMMA_TABLE_0
Definition: cslr_dss.h:5543
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volatile uint32_t CLUT_9
Definition: cslr_dss.h:1604
CSL_dss_vp2Regs::GAMMA_TABLE_14
volatile uint32_t GAMMA_TABLE_14
Definition: cslr_dss.h:5557
CSL_dss_vidl1Regs::CLUT_0
volatile uint32_t CLUT_0
Definition: cslr_dss.h:1595
CSL_dss_vp1Regs::GAMMA_TABLE_0
volatile uint32_t GAMMA_TABLE_0
Definition: cslr_dss.h:4307
CSL_dss_vidRegs::CSC_COEF1
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:2612
CSL_dss_vidRegs::ACCUV2_0
volatile uint32_t ACCUV2_0
Definition: cslr_dss.h:2601
CSL_dss_vidRegs::CLUT_0
volatile uint32_t CLUT_0
Definition: cslr_dss.h:2648
CSL_dss_vidRegs::CLUT_11
volatile uint32_t CLUT_11
Definition: cslr_dss.h:2659
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volatile uint32_t VP_IRQSTATUS_0
Definition: cslr_dss.h:74
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volatile uint32_t SAFETY_ATTRIBUTES
Definition: cslr_dss.h:1611
CSL_dss_vp1Regs::GAMMA_TABLE_10
volatile uint32_t GAMMA_TABLE_10
Definition: cslr_dss.h:4317
CSL_dss_vidl1Regs::ROW_INC
volatile uint32_t ROW_INC
Definition: cslr_dss.h:1585
CSL_dss_vidRegs::ACCUV_0
volatile uint32_t ACCUV_0
Definition: cslr_dss.h:2599
CSL_dss_vidRegs::CLUT_6
volatile uint32_t CLUT_6
Definition: cslr_dss.h:2654
CSL_dss_vp1Regs::TIMING_H
volatile uint32_t TIMING_H
Definition: cslr_dss.h:4288
CSL_dss_vp1Regs::LINE_NUMBER
volatile uint32_t LINE_NUMBER
Definition: cslr_dss.h:4284
CSL_dss_vidRegs::BA_EXT_0
volatile uint32_t BA_EXT_0
Definition: cslr_dss.h:2640
CSL_dss_vidRegs::CLUT_3
volatile uint32_t CLUT_3
Definition: cslr_dss.h:2651
CSL_dss_common1Regs::VID_IRQSTATUS_1
volatile uint32_t VID_IRQSTATUS_1
Definition: cslr_dss.h:969
CSL_dss_vidRegs::BUF_SIZE_STATUS
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:2609
CSL_dss_ovr2Regs::CONFIG
volatile uint32_t CONFIG
Definition: cslr_dss.h:4109
CSL_dss_vidRegs::BA_UV_EXT_1
volatile uint32_t BA_UV_EXT_1
Definition: cslr_dss.h:2643
CSL_dss_vp2Regs::DSS_OLDI_CFG
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:5559
CSL_dss_vidRegs::FIRH
volatile uint32_t FIRH
Definition: cslr_dss.h:2618
CSL_dss_vp1Regs::POL_FREQ
volatile uint32_t POL_FREQ
Definition: cslr_dss.h:4286
CSL_dss_commonRegs::VID_IRQENABLE_1
volatile uint32_t VID_IRQENABLE_1
Definition: cslr_dss.h:66
CSL_dss_vp1Regs::DSS_OLDI_LB
volatile uint32_t DSS_OLDI_LB
Definition: cslr_dss.h:4325
CSL_dss_vidRegs::ATTRIBUTES
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:2603
CSL_dss_vp2Regs::GAMMA_TABLE_13
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:5556
CSL_dss_vp2Regs::GAMMA_TABLE_10
volatile uint32_t GAMMA_TABLE_10
Definition: cslr_dss.h:5553
CSL_dss_vp2Regs::LINE_NUMBER
volatile uint32_t LINE_NUMBER
Definition: cslr_dss.h:5520
CSL_dss_vidRegs::SAFETY_POSITION
volatile uint32_t SAFETY_POSITION
Definition: cslr_dss.h:2666
CSL_dss_common1Regs::DISPC_IRQENABLE_CLR
volatile uint32_t DISPC_IRQENABLE_CLR
Definition: cslr_dss.h:963
CSL_dss_ovr2Regs::TRANS_COLOR_MAX
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:4113
CSL_dss_vidl1Regs::ATTRIBUTES
volatile uint32_t ATTRIBUTES
Definition: cslr_dss.h:1562
CSL_dss_commonRegs::DSS_CBA_CFG
volatile uint32_t DSS_CBA_CFG
Definition: cslr_dss.h:80
CSL_dss_vp2Regs::DSS_OLDI_LB
volatile uint32_t DSS_OLDI_LB
Definition: cslr_dss.h:5561
CSL_dss_vidl1Regs::PRELOAD
volatile uint32_t PRELOAD
Definition: cslr_dss.h:1584
CSL_dss_common1Regs::VID_IRQENABLE_1
volatile uint32_t VID_IRQENABLE_1
Definition: cslr_dss.h:965
CSL_dss_ovr1Regs::DEFAULT_COLOR2
volatile uint32_t DEFAULT_COLOR2
Definition: cslr_dss.h:3946
CSL_dss_ovr1Regs
Definition: cslr_dss.h:3942
CSL_dss_common1Regs::VP_IRQENABLE_1
volatile uint32_t VP_IRQENABLE_1
Definition: cslr_dss.h:972
CSL_dss_vidRegs::CLUT_1
volatile uint32_t CLUT_1
Definition: cslr_dss.h:2649
CSL_dss_vidRegs::GLOBAL_ALPHA
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:2630
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volatile uint32_t GAMMA_TABLE_7
Definition: cslr_dss.h:5550
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volatile uint32_t FIRV
Definition: cslr_dss.h:2620
CSL_dss_vidRegs::CLUT_12
volatile uint32_t CLUT_12
Definition: cslr_dss.h:2660
CSL_dss_common1Regs::DISPC_IRQSTATUS_RAW
volatile uint32_t DISPC_IRQSTATUS_RAW
Definition: cslr_dss.h:959
CSL_dss_vidl1Regs::BA_EXT_1
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:1588
CSL_dss_commonRegs::VID_IRQSTATUS_0
volatile uint32_t VID_IRQSTATUS_0
Definition: cslr_dss.h:68
CSL_dss_vidRegs::FIRV2
volatile uint32_t FIRV2
Definition: cslr_dss.h:2621
CSL_dss_vp1Regs
Definition: cslr_dss.h:4274
CSL_dss_vidRegs::SAFETY_LFSR_SEED
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:2669
CSL_dss_commonRegs::DISPC_IRQSTATUS_RAW
volatile uint32_t DISPC_IRQSTATUS_RAW
Definition: cslr_dss.h:60
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volatile uint32_t GAMMA_TABLE_1
Definition: cslr_dss.h:5544
CSL_dss_vp1Regs::CSC_COEF7
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:4294
CSL_dss_commonRegs::DISPC_GLOBAL_BUFFER
volatile uint32_t DISPC_GLOBAL_BUFFER
Definition: cslr_dss.h:79
CSL_dss_vp1Regs::CONFIG
volatile uint32_t CONFIG
Definition: cslr_dss.h:4275
CSL_dss_common1Regs::VP_IRQSTATUS_1
volatile uint32_t VP_IRQSTATUS_1
Definition: cslr_dss.h:975
CSL_dss_vp1Regs::DATA_CYCLE_0
volatile uint32_t DATA_CYCLE_0
Definition: cslr_dss.h:4280
CSL_dss_vidl1Regs
Definition: cslr_dss.h:1560
CSL_dss_vidl1Regs::CLUT_8
volatile uint32_t CLUT_8
Definition: cslr_dss.h:1603
CSL_dss_vp1Regs::DATA_CYCLE_2
volatile uint32_t DATA_CYCLE_2
Definition: cslr_dss.h:4282
CSL_dss_common1Regs::VP_IRQSTATUS_0
volatile uint32_t VP_IRQSTATUS_0
Definition: cslr_dss.h:974
CSL_dss_vp2Regs::SIZE_SCREEN
volatile uint32_t SIZE_SCREEN
Definition: cslr_dss.h:5523
CSL_dss_vidRegs::CSC_COEF0
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:2611
CSL_dss_vidl1Regs::CLUT_2
volatile uint32_t CLUT_2
Definition: cslr_dss.h:1597
CSL_dss_vp2Regs::GAMMA_TABLE_11
volatile uint32_t GAMMA_TABLE_11
Definition: cslr_dss.h:5554
CSL_dss_commonRegs
Definition: cslr_dss.h:53
CSL_dss_vidRegs::CLUT_7
volatile uint32_t CLUT_7
Definition: cslr_dss.h:2655
CSL_dss_vidRegs::ACCUH_1
volatile uint32_t ACCUH_1
Definition: cslr_dss.h:2596
CSL_dss_vp2Regs::GAMMA_TABLE_8
volatile uint32_t GAMMA_TABLE_8
Definition: cslr_dss.h:5551
CSL_dss_commonRegs::DISPC_IRQENABLE_SET
volatile uint32_t DISPC_IRQENABLE_SET
Definition: cslr_dss.h:62
CSL_dss_vp2Regs::GAMMA_TABLE_4
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:5547
CSL_dss_vidl1Regs::ATTRIBUTES2
volatile uint32_t ATTRIBUTES2
Definition: cslr_dss.h:1563
CSL_dss_ovr1Regs::TRANS_COLOR_MIN
volatile uint32_t TRANS_COLOR_MIN
Definition: cslr_dss.h:3949
CSL_dss_vp1Regs::GAMMA_TABLE_4
volatile uint32_t GAMMA_TABLE_4
Definition: cslr_dss.h:4311
CSL_dss_vp2Regs::GAMMA_TABLE_2
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:5545
CSL_dss_vidl1Regs::GLOBAL_ALPHA
volatile uint32_t GLOBAL_ALPHA
Definition: cslr_dss.h:1578
CSL_dss_vp2Regs::CSC_COEF4
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:5527
CSL_dss_ovr1Regs::TRANS_COLOR_MIN2
volatile uint32_t TRANS_COLOR_MIN2
Definition: cslr_dss.h:3950
CSL_dss_commonRegs::DISPC_DBG_STATUS
volatile uint32_t DISPC_DBG_STATUS
Definition: cslr_dss.h:82
CSL_dss_vidl1Regs::CLUT_12
volatile uint32_t CLUT_12
Definition: cslr_dss.h:1607
CSL_dss_vidl1Regs::CSC_COEF0
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:1570
CSL_dss_commonRegs::DISPC_GLOBAL_OUTPUT_ENABLE
volatile uint32_t DISPC_GLOBAL_OUTPUT_ENABLE
Definition: cslr_dss.h:78
CSL_dss_common1Regs::VID_IRQSTATUS_0
volatile uint32_t VID_IRQSTATUS_0
Definition: cslr_dss.h:968
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volatile uint32_t SAFETY_SIZE
Definition: cslr_dss.h:2668
CSL_dss_commonRegs::DISPC_IRQSTATUS
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:61
CSL_dss_commonRegs::DISPC_IRQ_EOI
volatile uint32_t DISPC_IRQ_EOI
Definition: cslr_dss.h:59
CSL_dss_vp2Regs::GAMMA_TABLE_15
volatile uint32_t GAMMA_TABLE_15
Definition: cslr_dss.h:5558
CSL_dss_vp2Regs::DATA_CYCLE_1
volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:5517
CSL_dss_vp2Regs::CONTROL
volatile uint32_t CONTROL
Definition: cslr_dss.h:5512
CSL_dss_vidRegs::BUF_THRESHOLD
volatile uint32_t BUF_THRESHOLD
Definition: cslr_dss.h:2610
CSL_dss_vp2Regs::GAMMA_TABLE_12
volatile uint32_t GAMMA_TABLE_12
Definition: cslr_dss.h:5555
CSL_dss_vp2Regs::DSS_OLDI_STATUS
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:5560
CSL_dss_commonRegs::VP_IRQENABLE_1
volatile uint32_t VP_IRQENABLE_1
Definition: cslr_dss.h:72
CSL_dss_vidRegs::ROW_INC
volatile uint32_t ROW_INC
Definition: cslr_dss.h:2637
CSL_dss_vidRegs::BA_0
volatile uint32_t BA_0
Definition: cslr_dss.h:2605
CSL_dss_vp2Regs::TIMING_V
volatile uint32_t TIMING_V
Definition: cslr_dss.h:5525
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volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:2644
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volatile uint32_t ACCUH2_1
Definition: cslr_dss.h:2598
CSL_dss_vp2Regs::CSC_COEF2
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:5515
CSL_dss_vidl1Regs::CLUT_13
volatile uint32_t CLUT_13
Definition: cslr_dss.h:1608
CSL_dss_vidRegs::CSC_COEF4
volatile uint32_t CSC_COEF4
Definition: cslr_dss.h:2615
CSL_dss_vp2Regs::SAFETY_LFSR_SEED
volatile uint32_t SAFETY_LFSR_SEED
Definition: cslr_dss.h:5541
CSL_dss_vp1Regs::CSC_COEF0
volatile uint32_t CSC_COEF0
Definition: cslr_dss.h:4277
CSL_dss_vidl1Regs::SAFETY_REF_SIGNATURE
volatile uint32_t SAFETY_REF_SIGNATURE
Definition: cslr_dss.h:1614
CSL_dss_vidl1Regs::CLUT_7
volatile uint32_t CLUT_7
Definition: cslr_dss.h:1602
CSL_dss_vidl1Regs::BA_UV_1
volatile uint32_t BA_UV_1
Definition: cslr_dss.h:1567
CSL_dss_vidl1Regs::SAFETY_CAPT_SIGNATURE
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:1612
CSL_dss_common1Regs::DISPC_IRQSTATUS
volatile uint32_t DISPC_IRQSTATUS
Definition: cslr_dss.h:960
CSL_dss_vp1Regs::GAMMA_TABLE_13
volatile uint32_t GAMMA_TABLE_13
Definition: cslr_dss.h:4320
CSL_dss_commonRegs::VID_IRQENABLE_0
volatile uint32_t VID_IRQENABLE_0
Definition: cslr_dss.h:65
CSL_dss_vidl1Regs::BA_0
volatile uint32_t BA_0
Definition: cslr_dss.h:1564
CSL_dss_commonRegs::VP_IRQENABLE_0
volatile uint32_t VP_IRQENABLE_0
Definition: cslr_dss.h:71
CSL_dss_vp2Regs::CSC_COEF6
volatile uint32_t CSC_COEF6
Definition: cslr_dss.h:5529
CSL_dss_vidRegs::SAFETY_CAPT_SIGNATURE
volatile uint32_t SAFETY_CAPT_SIGNATURE
Definition: cslr_dss.h:2665
CSL_dss_vidl1Regs::CLUT_3
volatile uint32_t CLUT_3
Definition: cslr_dss.h:1598
CSL_dss_vp1Regs::DSS_OLDI_CFG
volatile uint32_t DSS_OLDI_CFG
Definition: cslr_dss.h:4323
CSL_dss_vidl1Regs::CSC_COEF3
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:1573
CSL_dss_vidRegs::BA_EXT_1
volatile uint32_t BA_EXT_1
Definition: cslr_dss.h:2641
CSL_dss_vidRegs::CSC_COEF2
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:2613
CSL_dss_ovr2Regs::DEFAULT_COLOR2
volatile uint32_t DEFAULT_COLOR2
Definition: cslr_dss.h:4112
CSL_dss_vp1Regs::GAMMA_TABLE_6
volatile uint32_t GAMMA_TABLE_6
Definition: cslr_dss.h:4313
CSL_dss_vp1Regs::DSS_OLDI_STATUS
volatile uint32_t DSS_OLDI_STATUS
Definition: cslr_dss.h:4324
CSL_dss_vp1Regs::CSC_COEF2
volatile uint32_t CSC_COEF2
Definition: cslr_dss.h:4279
CSL_dss_commonRegs::VID_IRQSTATUS_1
volatile uint32_t VID_IRQSTATUS_1
Definition: cslr_dss.h:69
CSL_dss_vidl1Regs::CLUT_11
volatile uint32_t CLUT_11
Definition: cslr_dss.h:1606
CSL_dss_vp1Regs::GAMMA_TABLE_15
volatile uint32_t GAMMA_TABLE_15
Definition: cslr_dss.h:4322
CSL_dss_ovr1Regs::TRANS_COLOR_MAX
volatile uint32_t TRANS_COLOR_MAX
Definition: cslr_dss.h:3947
CSL_dss_vp2Regs::CSC_COEF3
volatile uint32_t CSC_COEF3
Definition: cslr_dss.h:5526
CSL_dss_vp2Regs::CSC_COEF7
volatile uint32_t CSC_COEF7
Definition: cslr_dss.h:5530
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volatile uint32_t DATA_CYCLE_1
Definition: cslr_dss.h:4281
CSL_dss_vidRegs::ACCUV2_1
volatile uint32_t ACCUV2_1
Definition: cslr_dss.h:2602
CSL_dss_vp1Regs::CSC_COEF1
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:4278
CSL_dss_commonRegs::VP_IRQSTATUS_1
volatile uint32_t VP_IRQSTATUS_1
Definition: cslr_dss.h:75
CSL_dss_vp2Regs::DATA_CYCLE_2
volatile uint32_t DATA_CYCLE_2
Definition: cslr_dss.h:5518
CSL_dss_vp1Regs::SIZE_SCREEN
volatile uint32_t SIZE_SCREEN
Definition: cslr_dss.h:4287
CSL_dss_vp1Regs::TIMING_V
volatile uint32_t TIMING_V
Definition: cslr_dss.h:4289
CSL_dss_vp2Regs::TIMING_H
volatile uint32_t TIMING_H
Definition: cslr_dss.h:5524
CSL_dss_vidl1Regs::BUF_SIZE_STATUS
volatile uint32_t BUF_SIZE_STATUS
Definition: cslr_dss.h:1568
CSL_dss_vp2Regs::GAMMA_TABLE_5
volatile uint32_t GAMMA_TABLE_5
Definition: cslr_dss.h:5548
CSL_dss_vidRegs::PRELOAD
volatile uint32_t PRELOAD
Definition: cslr_dss.h:2636
CSL_dss_vidRegs::PICTURE_SIZE
volatile uint32_t PICTURE_SIZE
Definition: cslr_dss.h:2633
CSL_dss_vp1Regs::GAMMA_TABLE_2
volatile uint32_t GAMMA_TABLE_2
Definition: cslr_dss.h:4309
CSL_dss_vidRegs::BA_UV_EXT_0
volatile uint32_t BA_UV_EXT_0
Definition: cslr_dss.h:2642
CSL_dss_vidRegs::MFLAG_THRESHOLD
volatile uint32_t MFLAG_THRESHOLD
Definition: cslr_dss.h:2632
CSL_dss_vidl1Regs::CSC_COEF1
volatile uint32_t CSC_COEF1
Definition: cslr_dss.h:1571
CSL_dss_vidl1Regs::LUMAKEY
volatile uint32_t LUMAKEY
Definition: cslr_dss.h:1617
CSL_dss_vidl1Regs::BA_1
volatile uint32_t BA_1
Definition: cslr_dss.h:1565
CSL_dss_commonRegs::DISPC_DBG_CONTROL
volatile uint32_t DISPC_DBG_CONTROL
Definition: cslr_dss.h:81
CSL_dss_vidRegs::CLUT_5
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Definition: cslr_dss.h:2653
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Definition: cslr_dss.h:4115
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Definition: cslr_dss.h:1601
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Definition: cslr_dss.h:2617
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Definition: cslr_dss.h:56
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Definition: cslr_dss.h:1580
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Definition: cslr_dss.h:3943
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Definition: cslr_dss.h:1615
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Definition: cslr_dss.h:2638
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Definition: cslr_dss.h:2661
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Definition: cslr_dss.h:1574
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Definition: cslr_dss.h:1575
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Definition: cslr_dss.h:1599
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Definition: cslr_dss.h:4321
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Definition: cslr_dss.h:2614
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Definition: cslr_dss.h:2656
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Definition: cslr_dss.h:4315
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Definition: cslr_dss.h:3948
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Definition: cslr_dss.h:1600
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Definition: cslr_dss.h:5516