Driver Porting Layer (DPL)

Table of Contents

• Introduction

Introduction

This module contains APIs which are used by the drivers to make them agnostic of the underlying OS and CPU architecture.

It consists of below sub-modules

• HW Interrupts
• Semaphore
• Task
• Clock
• Cycle Counter
• Queue
• Cache
• CPUID for ARMv7 (ARM R5)
• MMU for ARMv8 (ARM A53, TI C75)
• MPU for ARMv7 (ARM R5)
• Region based Address Translate
• Heap
• Debug
• Event
• Timer